From nobody Sun Dec 14 06:15:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FEEFE77372 for ; Sat, 30 Sep 2023 12:52:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234184AbjI3MwO (ORCPT ); Sat, 30 Sep 2023 08:52:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234163AbjI3MwL (ORCPT ); Sat, 30 Sep 2023 08:52:11 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 138DB1A4 for ; Sat, 30 Sep 2023 05:52:08 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B07DFC433C7; Sat, 30 Sep 2023 12:52:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696078327; bh=PO36H6jRR8QhXJ+xnlXTqLl+g9y5bq24w4dNdmW+KwE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CoGXAnvWfqasfxJ2+1tOXd6mushKBPwk/rdZ/6ShcRrtT1dgusjMI/Z7X0hG3TIpt GrkBhHQjCj+yD2MFeKQr/oXWqOB1f5WZZId+5KE7niXHbh+OE6sk1+UhbZ4cTi62iz LPKGNDrQnRnIqTNFojocifXICSLMTIHQ1LBqMhDji9H7/mV1ASYGRETmoJPA/TjEGq KczaPvnw8prKwbd7wfisV89bndQoIEZHWz4Rb9tbjyjiS8l7rbaQ8bmYxDPTd6GF8I bpRXBJKFRFRwRASlAptDVQ3GN/yHucwUsa0LfNuhJbnqH8w56pWLMAKGZM36YfywHA T/v5FaUtmigIw== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Anup Patel Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Inochi Amaoto , chao.wei@sophgo.com, xiaoguang.xing@sophgo.com Subject: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree Date: Sat, 30 Sep 2023 20:39:36 +0800 Message-Id: <20230930123937.1551-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230930123937.1551-1-jszhang@kernel.org> References: <20230930123937.1551-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/= sophgo/cv1800b.dtsi new file mode 100644 index 000000000000..8829bebaa017 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include + +/ { + compatible =3D "sophgo,cv1800b"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <25000000>; + + cpu0: cpu@0 { + compatible =3D "thead,c906", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <65536>; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <32768>; + mmu-type =3D "riscv,sv39"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + }; + + osc: oscillator { + compatible =3D "fixed-clock"; + clock-output-names =3D "osc_25m"; + #clock-cells =3D <0>; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <1>; + #size-cells =3D <1>; + dma-noncoherent; + ranges; + + uart0: serial@04140000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04140000 0x100>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart1: serial@04150000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04150000 0x100>; + interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart2: serial@04160000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04160000 0x100>; + interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart3: serial@04170000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x04170000 0x100>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart4: serial@041c0000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x041c0000 0x100>; + interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + plic: interrupt-controller@70000000 { + compatible =3D "sophgo,cv1800b-plic", "thead,c900-plic"; + reg =3D <0x70000000 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + riscv,ndev =3D <101>; + }; + }; +}; --=20 2.40.1