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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:35 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 08/28] clk: renesas: rzg2l: add struct clk_hw_data Date: Fri, 29 Sep 2023 08:38:55 +0300 Message-Id: <20230929053915.1530607-9-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add clk_hw_data struct that keeps the core part of a clock data. The sd_hw_data embeds a member of type struct clk_hw_data along with other members (in the next commits). This commit prepares the field for refactoring the SD MUX clock driver. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - collected tags drivers/clk/renesas/rzg2l-cpg.c | 52 +++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 02058a2d39ca..ac05463d1d98 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -63,13 +63,29 @@ =20 #define MAX_VCLK_FREQ (148500000) =20 -struct sd_hw_data { +/** + * struct clk_hw_data - clock hardware data + * @hw: clock hw + * @conf: clock configuration (register offset, shift, width) + * @priv: CPG private data structure + */ +struct clk_hw_data { struct clk_hw hw; u32 conf; struct rzg2l_cpg_priv *priv; }; =20 -#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw) +#define to_clk_hw_data(_hw) container_of(_hw, struct clk_hw_data, hw) + +/** + * struct sd_hw_data - SD clock hardware data + * @hw_data: clock hw data + */ +struct sd_hw_data { + struct clk_hw_data hw_data; +}; + +#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw_data) =20 struct rzg2l_pll5_param { u32 pl5_fracin; @@ -188,10 +204,10 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk = *core, =20 static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index) { - struct sd_hw_data *hwdata =3D to_sd_hw_data(hw); - struct rzg2l_cpg_priv *priv =3D hwdata->priv; - u32 off =3D GET_REG_OFFSET(hwdata->conf); - u32 shift =3D GET_SHIFT(hwdata->conf); + struct clk_hw_data *clk_hw_data =3D to_clk_hw_data(hw); + struct rzg2l_cpg_priv *priv =3D clk_hw_data->priv; + u32 off =3D GET_REG_OFFSET(clk_hw_data->conf); + u32 shift =3D GET_SHIFT(clk_hw_data->conf); const u32 clk_src_266 =3D 2; u32 msk, val, bitmask; unsigned long flags; @@ -208,7 +224,7 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_h= w *hw, u8 index) * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and * the index to value mapping is done by adding 1 to the index. */ - bitmask =3D (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16; + bitmask =3D (GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0) << shift) << 16; msk =3D off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS; spin_lock_irqsave(&priv->rmw_lock, flags); if (index !=3D clk_src_266) { @@ -237,12 +253,12 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk= _hw *hw, u8 index) =20 static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw) { - struct sd_hw_data *hwdata =3D to_sd_hw_data(hw); - struct rzg2l_cpg_priv *priv =3D hwdata->priv; - u32 val =3D readl(priv->base + GET_REG_OFFSET(hwdata->conf)); + struct clk_hw_data *clk_hw_data =3D to_clk_hw_data(hw); + struct rzg2l_cpg_priv *priv =3D clk_hw_data->priv; + u32 val =3D readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf)); =20 - val >>=3D GET_SHIFT(hwdata->conf); - val &=3D GENMASK(GET_WIDTH(hwdata->conf) - 1, 0); + val >>=3D GET_SHIFT(clk_hw_data->conf); + val &=3D GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0); =20 return val ? val - 1 : 0; } @@ -258,17 +274,17 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_c= lk *core, void __iomem *base, struct rzg2l_cpg_priv *priv) { - struct sd_hw_data *clk_hw_data; + struct sd_hw_data *sd_hw_data; struct clk_init_data init; struct clk_hw *clk_hw; int ret; =20 - clk_hw_data =3D devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL); - if (!clk_hw_data) + sd_hw_data =3D devm_kzalloc(priv->dev, sizeof(*sd_hw_data), GFP_KERNEL); + if (!sd_hw_data) return ERR_PTR(-ENOMEM); =20 - clk_hw_data->priv =3D priv; - clk_hw_data->conf =3D core->conf; + sd_hw_data->hw_data.priv =3D priv; + sd_hw_data->hw_data.conf =3D core->conf; =20 init.name =3D core->name; init.ops =3D &rzg2l_cpg_sd_clk_mux_ops; @@ -276,7 +292,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk= *core, init.num_parents =3D core->num_parents; init.parent_names =3D core->parent_names; =20 - clk_hw =3D &clk_hw_data->hw; + clk_hw =3D &sd_hw_data->hw_data.hw; clk_hw->init =3D &init; =20 ret =3D devm_clk_hw_register(priv->dev, clk_hw); --=20 2.39.2