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([82.78.167.177]) by smtp.gmail.com with ESMTPSA id z19-20020a1709063ad300b009a1a653770bsm11971992ejd.87.2023.09.28.22.39.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 22:39:49 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 15/28] pinctrl: renesas: rzg2l: adapt for different SD/PWPR register offsets Date: Fri, 29 Sep 2023 08:39:02 +0300 Message-Id: <20230929053915.1530607-16-claudiu.beznea@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea SD, PWPR power registers have different offsets b/w RZ/G2L and RZ/G3S. Commit adds a per SoC configuration data structure that is initialized with proper register offset for individual SoCs. The struct rzg2l_hwcfg will be further extended in next commits. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - collected tags drivers/pinctrl/renesas/pinctrl-rzg2l.c | 52 ++++++++++++++++++++----- 1 file changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 96fd829131bd..7256d99fd552 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -98,8 +98,7 @@ #define IOLH(off) (0x1000 + (off) * 8) #define IEN(off) (0x1800 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) -#define PWPR (0x3014) -#define SD_CH(n) (0x3000 + (n) * 4) +#define SD_CH(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) =20 #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -124,6 +123,24 @@ #define RZG2L_TINT_IRQ_START_INDEX 9 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) =20 +/** + * struct rzg2l_register_offsets - specific register offsets + * @pwpr: PWPR register offset + * @sd_ch: SD_CH register offset + */ +struct rzg2l_register_offsets { + u16 pwpr; + u16 sd_ch; +}; + +/** + * struct rzg2l_hwcfg - hardware configuration data structure + * @regs: hardware specific register offsets + */ +struct rzg2l_hwcfg { + const struct rzg2l_register_offsets regs; +}; + struct rzg2l_dedicated_configs { const char *name; u32 config; @@ -136,6 +153,7 @@ struct rzg2l_pinctrl_data { const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; + const struct rzg2l_hwcfg *hwcfg; }; =20 struct rzg2l_pinctrl { @@ -163,6 +181,7 @@ static const unsigned int iolh_groupb_oi[] =3D { 100, 6= 6, 50, 33 }; static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { + const struct rzg2l_register_offsets *regs =3D &pctrl->data->hwcfg->regs; unsigned long flags; u32 reg; =20 @@ -178,8 +197,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pin= ctrl *pctrl, writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); =20 /* Set the PWPR register to allow PFC register to write */ - writel(0x0, pctrl->base + PWPR); /* B0WI=3D0, PFCWE=3D0 */ - writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=3D0, PFCWE=3D1 */ + writel(0x0, pctrl->base + regs->pwpr); /* B0WI=3D0, PFCWE=3D0 */ + writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=3D0, PFCWE=3D1 */ =20 /* Select Pin function mode with PFC register */ reg =3D readl(pctrl->base + PFC(off)); @@ -187,8 +206,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pin= ctrl *pctrl, writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); =20 /* Set the PWPR register to be write-protected */ - writel(0x0, pctrl->base + PWPR); /* B0WI=3D0, PFCWE=3D0 */ - writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=3D1, PFCWE=3D0 */ + writel(0x0, pctrl->base + regs->pwpr); /* B0WI=3D0, PFCWE=3D0 */ + writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=3D1, PFCWE=3D0 */ =20 /* Switch to Peripheral pin function with PMC register */ reg =3D readb(pctrl->base + PMC(off)); @@ -527,6 +546,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev= *pctldev, { struct rzg2l_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param =3D pinconf_to_config_param(*config); + const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; const struct pinctrl_pin_desc *pin =3D &pctrl->desc.pins[_pin]; unsigned int *pin_data =3D pin->drv_data; unsigned int arg =3D 0; @@ -562,9 +583,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev= *pctldev, u32 pwr_reg =3D 0x0; =20 if (cfg & PIN_CFG_IO_VMC_SD0) - pwr_reg =3D SD_CH(0); + pwr_reg =3D SD_CH(regs->sd_ch, 0); else if (cfg & PIN_CFG_IO_VMC_SD1) - pwr_reg =3D SD_CH(1); + pwr_reg =3D SD_CH(regs->sd_ch, 1); else if (cfg & PIN_CFG_IO_VMC_QSPI) pwr_reg =3D QSPI; else @@ -616,6 +637,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev= *pctldev, struct rzg2l_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); const struct pinctrl_pin_desc *pin =3D &pctrl->desc.pins[_pin]; unsigned int *pin_data =3D pin->drv_data; + const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; enum pin_config_param param; unsigned long flags; void __iomem *addr; @@ -659,9 +682,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev= *pctldev, return -EINVAL; =20 if (cfg & PIN_CFG_IO_VMC_SD0) - pwr_reg =3D SD_CH(0); + pwr_reg =3D SD_CH(regs->sd_ch, 0); else if (cfg & PIN_CFG_IO_VMC_SD1) - pwr_reg =3D SD_CH(1); + pwr_reg =3D SD_CH(regs->sd_ch, 1); else if (cfg & PIN_CFG_IO_VMC_QSPI) pwr_reg =3D QSPI; else @@ -1531,6 +1554,13 @@ static int rzg2l_pinctrl_probe(struct platform_devic= e *pdev) return 0; } =20 +static const struct rzg2l_hwcfg rzg2l_hwcfg =3D { + .regs =3D { + .pwpr =3D 0x3014, + .sd_ch =3D 0x3000, + }, +}; + static struct rzg2l_pinctrl_data r9a07g043_data =3D { .port_pins =3D rzg2l_gpio_names, .port_pin_configs =3D r9a07g043_gpio_configs, @@ -1538,6 +1568,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data =3D { .dedicated_pins =3D rzg2l_dedicated_pins.common, .n_port_pins =3D ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins =3D ARRAY_SIZE(rzg2l_dedicated_pins.common), + .hwcfg =3D &rzg2l_hwcfg, }; =20 static struct rzg2l_pinctrl_data r9a07g044_data =3D { @@ -1548,6 +1579,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data =3D { .n_port_pins =3D ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins =3D ARRAY_SIZE(rzg2l_dedicated_pins.common) + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), + .hwcfg =3D &rzg2l_hwcfg, }; =20 static const struct of_device_id rzg2l_pinctrl_of_table[] =3D { --=20 2.39.2