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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Starting from HW version 3.2 the IRQ_ENABLE bit has moved to the IRQ_i_CFG register and requires a change of the driver to avoid writing into an undefined register address. Get the HW version from registers and set the IRQ_ENABLE bit to the correct register depending on the HW version. Reviewed-by: Maulik Shah Acked-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/irqchip/qcom-pdc.c | 69 ++++++++++++++++++++++++++++++++++--------= ---- 1 file changed, 51 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index a32c0d28d038..74b2f124116e 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -22,9 +22,20 @@ =20 #define PDC_MAX_GPIO_IRQS 256 =20 +/* Valid only on HW version < 3.2 */ #define IRQ_ENABLE_BANK 0x10 #define IRQ_i_CFG 0x110 =20 +/* Valid only on HW version >=3D 3.2 */ +#define IRQ_i_CFG_IRQ_ENABLE 3 + +#define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0) + +#define PDC_VERSION_REG 0x1000 + +/* Notable PDC versions */ +#define PDC_VERSION_3_2 0x30200 + struct pdc_pin_region { u32 pin_base; u32 parent_base; @@ -37,6 +48,7 @@ static DEFINE_RAW_SPINLOCK(pdc_lock); static void __iomem *pdc_base; static struct pdc_pin_region *pdc_region; static int pdc_region_cnt; +static unsigned int pdc_version; =20 static void pdc_reg_write(int reg, u32 i, u32 val) { @@ -48,20 +60,32 @@ static u32 pdc_reg_read(int reg, u32 i) return readl_relaxed(pdc_base + reg + i * sizeof(u32)); } =20 -static void pdc_enable_intr(struct irq_data *d, bool on) +static void __pdc_enable_intr(int pin_out, bool on) { - int pin_out =3D d->hwirq; unsigned long enable; - unsigned long flags; - u32 index, mask; =20 - index =3D pin_out / 32; - mask =3D pin_out % 32; + if (pdc_version < PDC_VERSION_3_2) { + u32 index, mask; + + index =3D pin_out / 32; + mask =3D pin_out % 32; + + enable =3D pdc_reg_read(IRQ_ENABLE_BANK, index); + __assign_bit(mask, &enable, on); + pdc_reg_write(IRQ_ENABLE_BANK, index, enable); + } else { + enable =3D pdc_reg_read(IRQ_i_CFG, pin_out); + __assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on); + pdc_reg_write(IRQ_i_CFG, pin_out, enable); + } +} + +static void pdc_enable_intr(struct irq_data *d, bool on) +{ + unsigned long flags; =20 raw_spin_lock_irqsave(&pdc_lock, flags); - enable =3D pdc_reg_read(IRQ_ENABLE_BANK, index); - __assign_bit(mask, &enable, on); - pdc_reg_write(IRQ_ENABLE_BANK, index, enable); + __pdc_enable_intr(d->hwirq, on); raw_spin_unlock_irqrestore(&pdc_lock, flags); } =20 @@ -142,6 +166,7 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, un= signed int type) } =20 old_pdc_type =3D pdc_reg_read(IRQ_i_CFG, d->hwirq); + pdc_type |=3D (old_pdc_type & ~IRQ_i_CFG_TYPE_MASK); pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); =20 ret =3D irq_chip_set_type_parent(d, type); @@ -246,7 +271,6 @@ static const struct irq_domain_ops qcom_pdc_ops =3D { static int pdc_setup_pin_mapping(struct device_node *np) { int ret, n, i; - u32 irq_index, reg_index, val; =20 n =3D of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); if (n <=3D 0 || n % 3) @@ -276,29 +300,38 @@ static int pdc_setup_pin_mapping(struct device_node *= np) if (ret) return ret; =20 - for (i =3D 0; i < pdc_region[n].cnt; i++) { - reg_index =3D (i + pdc_region[n].pin_base) >> 5; - irq_index =3D (i + pdc_region[n].pin_base) & 0x1f; - val =3D pdc_reg_read(IRQ_ENABLE_BANK, reg_index); - val &=3D ~BIT(irq_index); - pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val); - } + for (i =3D 0; i < pdc_region[n].cnt; i++) + __pdc_enable_intr(i + pdc_region[n].pin_base, 0); } =20 return 0; } =20 +#define QCOM_PDC_SIZE 0x30000 + static int qcom_pdc_init(struct device_node *node, struct device_node *par= ent) { struct irq_domain *parent_domain, *pdc_domain; + resource_size_t res_size; + struct resource res; int ret; =20 - pdc_base =3D of_iomap(node, 0); + /* compat with old sm8150 DT which had very small region for PDC */ + if (of_address_to_resource(node, 0, &res)) + return -EINVAL; + + res_size =3D max_t(resource_size_t, resource_size(&res), QCOM_PDC_SIZE); + if (res_size > resource_size(&res)) + pr_warn("%pOF: invalid reg size, please fix DT\n", node); + + pdc_base =3D ioremap(res.start, res_size); if (!pdc_base) { pr_err("%pOF: unable to map PDC registers\n", node); return -ENXIO; } =20 + pdc_version =3D pdc_reg_read(PDC_VERSION_REG, 0); + parent_domain =3D irq_find_host(parent); if (!parent_domain) { pr_err("%pOF: unable to find PDC's parent domain\n", node); --=20 2.34.1 From nobody Wed Dec 17 08:12:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34082E743C0 for ; Fri, 29 Sep 2023 03:44:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232662AbjI2DoX (ORCPT ); Thu, 28 Sep 2023 23:44:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232178AbjI2DoL (ORCPT ); Thu, 28 Sep 2023 23:44:11 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBC4A19C for ; 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Thu, 28 Sep 2023 20:44:07 -0700 (PDT) From: neil.armstrong@linaro.org Date: Fri, 29 Sep 2023 05:44:01 +0200 Subject: [PATCH v5 2/2] arm64: dts: qcom: sm8150: extend the size of the PDC resource MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230929-topic-sm8x50-upstream-pdc-ver-v5-2-800111572104@linaro.org> References: <20230929-topic-sm8x50-upstream-pdc-ver-v5-0-800111572104@linaro.org> In-Reply-To: <20230929-topic-sm8x50-upstream-pdc-ver-v5-0-800111572104@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Thomas Gleixner , Marc Zyngier Cc: "Maulik Shah (mkshah)" , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Dmitry Baryshkov X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1064; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=sP+r4e04X8jecgSE+GdyYs6YDv2q2USTYBLqb/XeWBc=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlFkgE6Hat4o6gljT/wwjabnHx41yjh0M4fp+eFEZV R9Llmj+JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZRZIBAAKCRB33NvayMhJ0QirEA Cd7dhmXO7B5MbxvUn1DThRdtFTqIQfglZ/bsMPwx0O2uHdI35FikKiKDwtVLUavDjNi1uyflj/2IOX hXhJyUK8LV73Ar8G+bS4706y/f1l1LRKgIlJwlNkjsP6/tEBF4/MCXA6C4DeZva3JRuI7Ei5T4YwaA IMNOXL924ahXGMxPSNEy/Juok/EIwo6StODJV62Or9CGxNe563AtBV3fTPGwwWGqdQvmCO2DtSgtl6 qmJWIPmbjy3ZP202NJfndcgFG4NeMlYwNd9lNqQQIumbjWo7dOChFQCnVEqNIpmCrUhx1OdPvrljtG 4LjywL2ZjXgsU+HQDKzjpUflWMn0ks3xtUqrBeUSjJT/EHc2OvjlZlSL8pcAmsHVXcjUsY0Atbaw/d 8l4qgo8RtVXXjp3ZSu9wqZOTYDukT5sFq38EA1Vy5hKuGWhAWSsu+mnMwnoWCpgwAKKUqfqBJVJhoj QFo0kUCXw6ry1MEoWO/khc+CWBCHRFga3cwXoN9fAD1MBDzuNKDRGpDxqvckcw1j1su7+dOyms++VE 3VMCbWqyPaJ+ZNc2slQrU3YhooRpXvfo/ZuICwyAnxv0JC4n5dXU6pOixqGBwSJm3digwGT7ViRThu qbOK1/ZWpMUIP/eU23Ps7TgsPrrMopMIZkv1BU/Maasrz1OrYuIkn0dgnR5A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Baryshkov Follow the example of other platforms and extend the PDC resource region to 0x30000, so that the PDC driver can read the PDC_VERSION register. Fixes: 397ad94668c1 ("arm64: dts: qcom: sm8150: Add pdc interrupt controlle= r node") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index a7c3020a5de4..06c53000bb74 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3958,7 +3958,7 @@ dispcc: clock-controller@af00000 { =20 pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8150-pdc", "qcom,pdc"; - reg =3D <0 0x0b220000 0 0x400>; + reg =3D <0 0x0b220000 0 0x30000>; qcom,pdc-ranges =3D <0 480 94>, <94 609 31>, <125 63 1>; #interrupt-cells =3D <2>; --=20 2.34.1