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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id j6-20020aa7ca46000000b0052889d090bfsm10825040edt.79.2023.09.29.01.01.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Sep 2023 01:01:07 -0700 (PDT) From: Luca Weiss Date: Fri, 29 Sep 2023 10:01:05 +0200 Subject: [PATCH 1/3] dt-bindings: i2c: qcom-cci: Document SC7280 compatible MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230929-sc7280-cci-v1-1-16c7d386f062@fairphone.com> References: <20230929-sc7280-cci-v1-0-16c7d386f062@fairphone.com> In-Reply-To: <20230929-sc7280-cci-v1-0-16c7d386f062@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the compatible for the CCI block found on SC7280 SoC. Signed-off-by: Luca Weiss Reviewed-by: Bryan O'Donoghue --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Docu= mentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 042d4dc636ee..158588236749 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -25,6 +25,7 @@ properties: =20 - items: - enum: + - qcom,sc7280-cci - qcom,sdm845-cci - qcom,sm6350-cci - qcom,sm8250-cci --=20 2.42.0 From nobody Wed Dec 17 08:13:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC16AE743F2 for ; Fri, 29 Sep 2023 08:01:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232859AbjI2IB0 (ORCPT ); Fri, 29 Sep 2023 04:01:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232819AbjI2IBN (ORCPT ); Fri, 29 Sep 2023 04:01:13 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4B5D1B8 for ; Fri, 29 Sep 2023 01:01:10 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-5362bcc7026so2566654a12.1 for ; Fri, 29 Sep 2023 01:01:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1695974469; x=1696579269; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EYzKGHRYLJ6g+A5OXZ4xV/Es8JjR1AM+0LwhrF0kzy4=; b=aig+9hcZnVthGb4gyq2ydfqHOpzS9esCDegx9CQ8vn1pcjxo+Bvf/EetqGbsmnDKdX L21wmhc62T16A5VDZQJOdjsAXg/zON/XvFVsjhVi5FzwSQZQXfA4yiNG325zqh5m7WmN YliRVbRFPXySfVL7qy7VwHPVjufmhA4EWWaI7JBaTwNPff21GLLoTfvS122a/nj1aCz+ nQ3AXcO/WEXTX1oVhplUUej9JthHsqRTSPpkB9/fvznpOeQcObVU0ow+mNwjmnzvqy2Q yJssgM4nvoaENshjmHx/DS0LOemq3sbpAESFB1+Q38vHUYQ9ts01iVP4pBMjA8HM0f1P HBXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695974469; x=1696579269; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EYzKGHRYLJ6g+A5OXZ4xV/Es8JjR1AM+0LwhrF0kzy4=; b=KWO5ScmfcuYpEBdA8KrEbS5zAtz8JIMuwQ3K+WjnRW22YgwKVrDKt6F88D3xi8YTGF f6qPv2x2vX+nKHeFFhHCAr5ZnSKxQf0sS7SOrOzZQ5B/7YjSy3oHXo8i9oBE0KiXhWRl gOq/Gc9wJ8KMr/pEym1QoWutIp1DlOOWnx6cjTEvIGPdLE6Ad646RFD6RylW21+k0koh qfwS7peEu+fQUO9dieYOD+AJOwcreUJdvqSKA2t8nM1QETDf7WZhX3VJwko3OWLD1meG AWrvOStDWqDoNrhNUyqetFgl3Ah6ktL5X5SASto3gCMvpbtxLTVKPd1qjsi9et3h/Uqm WWWA== X-Gm-Message-State: AOJu0YwXPFO778Isru3jvNmwZblExLQsNJ9E50InnXLQeoqWa+SGcqYk xnSti1tsZn6ck5jwnUXOtJ6xEg== X-Google-Smtp-Source: AGHT+IHJBvE2q/+7hRsyhn1O0y4IxujNTuvfrEPD8B7LeqjNrRbB7ab95rqVG4rYWD0lWKFme/7IpA== X-Received: by 2002:aa7:c409:0:b0:531:1455:7528 with SMTP id j9-20020aa7c409000000b0053114557528mr2896677edq.40.1695974469074; Fri, 29 Sep 2023 01:01:09 -0700 (PDT) Received: from otso.luca.vpn.lucaweiss.eu (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id j6-20020aa7ca46000000b0052889d090bfsm10825040edt.79.2023.09.29.01.01.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Sep 2023 01:01:08 -0700 (PDT) From: Luca Weiss Date: Fri, 29 Sep 2023 10:01:06 +0200 Subject: [PATCH 2/3] arm64: dts: qcom: sc7280: Add Camera Control Interface busses MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230929-sc7280-cci-v1-2-16c7d386f062@fairphone.com> References: <20230929-sc7280-cci-v1-0-16c7d386f062@fairphone.com> In-Reply-To: <20230929-sc7280-cci-v1-0-16c7d386f062@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the CCI busses found on sc7280 and their pinctrl states. Signed-off-by: Luca Weiss Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 136 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 136 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 66f1eb83cca7..65550de2e4ff 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3793,6 +3793,86 @@ videocc: clock-controller@aaf0000 { #power-domain-cells =3D <1>; }; =20 + cci0: cci@ac4a000 { + compatible =3D "qcom,sc7280-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac4a000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names =3D "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + pinctrl-0 =3D <&cci0_default &cci1_default>; + pinctrl-1 =3D <&cci0_sleep &cci1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible =3D "qcom,sc7280-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac4b000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names =3D "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + pinctrl-0 =3D <&cci2_default &cci3_default>; + pinctrl-1 =3D <&cci2_sleep &cci3_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camcc: clock-controller@ad00000 { compatible =3D "qcom,sc7280-camcc"; reg =3D <0 0x0ad00000 0 0x10000>; @@ -4298,6 +4378,62 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 175>; wakeup-parent =3D <&pdc>; =20 + cci0_default: cci0-default-state { + pins =3D "gpio69", "gpio70"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + pins =3D "gpio69", "gpio70"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + pins =3D "gpio71", "gpio72"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + pins =3D "gpio71", "gpio72"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci2_default: cci2-default-state { + pins =3D "gpio73", "gpio74"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci2_sleep: cci2-sleep-state { + pins =3D "gpio73", "gpio74"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci3_default: cci3-default-state { + pins =3D "gpio75", "gpio76"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci3_sleep: cci3-sleep-state { + pins =3D "gpio75", "gpio76"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + dp_hot_plug_det: dp-hot-plug-det-state { pins =3D "gpio47"; function =3D "dp_hot"; --=20 2.42.0 From nobody Wed Dec 17 08:13:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60520E743F3 for ; Fri, 29 Sep 2023 08:01:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232849AbjI2IBX (ORCPT ); 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id j6-20020aa7ca46000000b0052889d090bfsm10825040edt.79.2023.09.29.01.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Sep 2023 01:01:09 -0700 (PDT) From: Luca Weiss Date: Fri, 29 Sep 2023 10:01:07 +0200 Subject: [PATCH 3/3] arm64: dts: qcom: qcm6490-fairphone-fp5: Enable CCI busses MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230929-sc7280-cci-v1-3-16c7d386f062@fairphone.com> References: <20230929-sc7280-cci-v1-0-16c7d386f062@fairphone.com> In-Reply-To: <20230929-sc7280-cci-v1-0-16c7d386f062@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable the CCI busses where sensors are connected to. Not covered here is the regulator used for pull-up on the I2C busses. This would be pm8008_l6 (L6P). Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 20 ++++++++++++++++++= ++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm6= 4/boot/dts/qcom/qcm6490-fairphone-fp5.dts index c8e7e6689b20..3fc0b3f7dc31 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -388,6 +388,26 @@ vreg_bob: bob { }; }; =20 +&cci0 { + status =3D "okay"; +}; + +&cci0_i2c0 { + /* IMX800 @ 1a */ +}; + +&cci0_i2c1 { + /* IMX858 @ 29 */ +}; + +&cci1 { + status =3D "okay"; +}; + +&cci1_i2c1 { + /* S5KJN1SQ03 @ 10 */ +}; + &dispcc { /* Disable for now so simple-framebuffer continues working */ status =3D "disabled"; --=20 2.42.0