From nobody Fri Dec 19 16:04:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11C21E732FD for ; Thu, 28 Sep 2023 17:58:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230501AbjI1R6e (ORCPT ); Thu, 28 Sep 2023 13:58:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229870AbjI1R6d (ORCPT ); Thu, 28 Sep 2023 13:58:33 -0400 X-Greylist: delayed 60 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Thu, 28 Sep 2023 10:58:24 PDT Received: from smtpcmd0986.aruba.it (smtpcmd0986.aruba.it [62.149.156.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 601A019E for ; Thu, 28 Sep 2023 10:58:24 -0700 (PDT) Received: from localhost.localdomain ([146.241.127.78]) by Aruba Outgoing Smtp with ESMTPSA id lvGJqRkNrbrLalvGJqINWv; Thu, 28 Sep 2023 19:57:21 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1695923841; bh=W26aS+AEwmr6PQiOcPGzMXEAcfiPOUrQ2EpC+Nm6EpI=; h=From:To:Subject:Date:MIME-Version; b=mj/kkz4Nrd3UabDB+nyN4rgAjMW3yKV+LcWLUR7LeoKIsZJlBjXNvTzf84OA11tQf 6JIb6jf3bv3oxDxiw4OuyT8GzUNM5UsT5K3d8He+fso6eT9FjPsc9x69yaucUsswjn 3wg+lRezKzRAac/YghKjWAsXXonL3BYnRiFN4Zsw+BMoZ59OPU43arrl8rPt6MlEQH v/o+9etR+qMve/x5q5jR6QY3VkBJbGLF5vnwQdQdH7St7jtFXBzKOmXdaK8pSOh/J0 tGwpk3RMYB+uVFnJjKbcCuATmcFfPoG9wtmaCsbSJVzpl0Za5gm7r8xxKx4fbEouHb f2sKAO83SRNMg== From: Giulio Benetti To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Broadcom internal kernel review list , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, Giulio Benetti , Jim Reinhart , James Autry , Matthew Maron Subject: [PATCH v2] net: phy: broadcom: add support for BCM5221 phy Date: Thu, 28 Sep 2023 19:57:18 +0200 Message-Id: <20230928175718.1729663-1-giulio.benetti@benettiengineering.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMAE-Envelope: MS4xfEtVQI+8AswZVM7FBMIiT663AomCA+jyxGTyH5WEGFNtNARxp0taB4lgjfgtjVhvS82aDRmQ+OwDTTmNoYOcavwqKM92r54ONmRc0u51dEtbkOHe/w8P UmnLedEw2stXHFH9ZPexR/FCvfXKn5tBj2Mtek2gdictfnHqmutQIyMWxwsa8GnDNQ4JmhXnKXpa0YFfrvyQLxP+46aHjnfxi6jroTyEl03CtESf+Y6yzT3W 8TRvDsrq1P2ZfwP7o3IoZyoxQ1RQd7q8drdoQyRpMFzb79RqM+N6N3/AQj045ioyTIfbHqkCWsCxiBAwfyR4+iI90VCMeVZR/ec2GvQPDoKwn+XEajsnYCXr geRoaFEvrRxf0/IHMlUGy8PqZjlLjG4j+9OfBPayodxi6A/r5Wd+Di86N6lBQ1UfUMnzbII4opO8G03cGvxQ2ysk9ISnOzTaBjny9bsLOVCpK8yphNXDck2w /Wk2Asbn9/h1+w9qwg74VQI+Bv0O7rpwsNJCoM8aF4ncjU+uZqjZv8v4Z90h/d06GaoNHACMFY9oWho67Vmu9KrZbmlrbEMZYLcAlXZ0pCk2Y8cUH+8mqc7s Ur/Ezz5IalO2uPsnkZi9NXI+CIXTBvBlCVEsaVchEfDjMz+aDkDKG0zau3nkKhIt7nPATqIVVSNiRmWtzjhqUnTyUr9YYGPpb2qQLDgSqL7PBU+i0Q3kxH7r efNxEdBxbX0= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Giulio Benetti This patch adds the BCM5221 PHY support by reusing brcm_fet_*() callbacks and adding quirks for BCM5221 when needed. Cc: Jim Reinhart Cc: James Autry Cc: Matthew Maron Signed-off-by: Giulio Benetti --- V1->V2: Suggested by Andrew Lunn: * handle mdix_ctrl adding bcm5221_config_aneg() and bcm5221_read_status() * reorder PHY_ID_BCM5241 in broadcom_tbl[] Suggested by Russell King: * add comment on phy_read(..., MII_BRCM_FET_INTREG) * lock mdio bus when in shadow mode Suggested by Florian Fainelli: * reuse brcm_fet_*() callbacks checking for phy_id =3D=3D PHY_ID_BCM5221 --- drivers/net/phy/broadcom.c | 155 +++++++++++++++++++++++++++++-------- include/linux/brcmphy.h | 10 +++ 2 files changed, 132 insertions(+), 33 deletions(-) diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 6f5e8be73d9a..4b71207037d0 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -648,16 +648,21 @@ static int brcm_fet_config_init(struct phy_device *ph= ydev) if (err < 0 && err !=3D -EIO) return err; =20 + /* Read to clear status bits */ reg =3D phy_read(phydev, MII_BRCM_FET_INTREG); if (reg < 0) return reg; =20 /* Unmask events we are interested in and mask interrupts globally. */ - reg =3D MII_BRCM_FET_IR_DUPLEX_EN | - MII_BRCM_FET_IR_SPEED_EN | - MII_BRCM_FET_IR_LINK_EN | - MII_BRCM_FET_IR_ENABLE | - MII_BRCM_FET_IR_MASK; + if (phydev->phy_id =3D=3D PHY_ID_BCM5221) + reg =3D MII_BRCM_FET_IR_ENABLE | + MII_BRCM_FET_IR_MASK; + else + reg =3D MII_BRCM_FET_IR_DUPLEX_EN | + MII_BRCM_FET_IR_SPEED_EN | + MII_BRCM_FET_IR_LINK_EN | + MII_BRCM_FET_IR_ENABLE | + MII_BRCM_FET_IR_MASK; =20 err =3D phy_write(phydev, MII_BRCM_FET_INTREG, reg); if (err < 0) @@ -670,42 +675,50 @@ static int brcm_fet_config_init(struct phy_device *ph= ydev) =20 reg =3D brcmtest | MII_BRCM_FET_BT_SRE; =20 - err =3D phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); - if (err < 0) - return err; + phy_lock_mdio_bus(phydev); =20 - /* Set the LED mode */ - reg =3D phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); - if (reg < 0) { - err =3D reg; - goto done; + err =3D __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); + if (err < 0) { + phy_unlock_mdio_bus(phydev); + return err; } =20 - reg &=3D ~MII_BRCM_FET_SHDW_AM4_LED_MASK; - reg |=3D MII_BRCM_FET_SHDW_AM4_LED_MODE1; + if (phydev->phy_id !=3D PHY_ID_BCM5221) { + /* Set the LED mode */ + reg =3D __phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); + if (reg < 0) { + err =3D reg; + goto done; + } =20 - err =3D phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); - if (err < 0) - goto done; + reg &=3D ~MII_BRCM_FET_SHDW_AM4_LED_MASK; + reg |=3D MII_BRCM_FET_SHDW_AM4_LED_MODE1; =20 - /* Enable auto MDIX */ - err =3D phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL, - MII_BRCM_FET_SHDW_MC_FAME); - if (err < 0) - goto done; + err =3D __phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); + if (err < 0) + goto done; + + /* Enable auto MDIX */ + err =3D __phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL, + MII_BRCM_FET_SHDW_MC_FAME); + if (err < 0) + goto done; + } =20 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) { /* Enable auto power down */ - err =3D phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, - MII_BRCM_FET_SHDW_AS2_APDE); + err =3D __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, + MII_BRCM_FET_SHDW_AS2_APDE); } =20 done: /* Disable shadow register access */ - err2 =3D phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); + err2 =3D __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); if (!err) err =3D err2; =20 + phy_unlock_mdio_bus(phydev); + return err; } =20 @@ -784,23 +797,86 @@ static int brcm_fet_suspend(struct phy_device *phydev) =20 reg =3D brcmtest | MII_BRCM_FET_BT_SRE; =20 - err =3D phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); - if (err < 0) + phy_lock_mdio_bus(phydev); + + err =3D __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); + if (err < 0) { + phy_unlock_mdio_bus(phydev); return err; + } + + if (phydev->phy_id =3D=3D PHY_ID_BCM5221) + /* Force Low Power Mode with clock enabled */ + reg =3D BCM5221_SHDW_AM4_EN_CLK_LPM | BCM5221_SHDW_AM4_FORCE_LPM; + else + /* Set standby mode */ + reg =3D MII_BRCM_FET_SHDW_AM4_STANDBY; =20 - /* Set standby mode */ - err =3D phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4, - MII_BRCM_FET_SHDW_AM4_STANDBY, - MII_BRCM_FET_SHDW_AM4_STANDBY); + err =3D __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); =20 /* Disable shadow register access */ - err2 =3D phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); + err2 =3D __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); if (!err) err =3D err2; =20 + phy_unlock_mdio_bus(phydev); + return err; } =20 +static int bcm5221_config_aneg(struct phy_device *phydev) +{ + int ret, val; + + ret =3D genphy_config_aneg(phydev); + if (ret) + return ret; + + switch (phydev->mdix_ctrl) { + case ETH_TP_MDI: + val =3D BCM5221_AEGSR_MDIX_DIS; + break; + case ETH_TP_MDI_X: + val =3D BCM5221_AEGSR_MDIX_DIS | BCM5221_AEGSR_MDIX_MAN_SWAP; + break; + case ETH_TP_MDI_AUTO: + val =3D 0; + break; + default: + return 0; + } + + return phy_modify(phydev, BCM5221_AEGSR, BCM5221_AEGSR_MDIX_MAN_SWAP | + BCM5221_AEGSR_MDIX_DIS, + val); +} + +static int bcm5221_read_status(struct phy_device *phydev) +{ + int ret; + + /* Read MDIX status */ + ret =3D phy_read(phydev, BCM5221_AEGSR); + if (ret < 0) + return ret; + + if (ret & BCM5221_AEGSR_MDIX_DIS) { + if (ret & BCM5221_AEGSR_MDIX_MAN_SWAP) + phydev->mdix_ctrl =3D ETH_TP_MDI_X; + else + phydev->mdix_ctrl =3D ETH_TP_MDI; + } else { + phydev->mdix_ctrl =3D ETH_TP_MDI_AUTO; + } + + if (ret & BCM5221_AEGSR_MDIX_STATUS) + phydev->mdix =3D ETH_TP_MDI_X; + else + phydev->mdix =3D ETH_TP_MDI; + + return genphy_read_status(phydev); +} + static int bcm54xx_phy_probe(struct phy_device *phydev) { struct bcm54xx_phy_priv *priv; @@ -1082,6 +1158,18 @@ static struct phy_driver broadcom_drivers[] =3D { .handle_interrupt =3D brcm_fet_handle_interrupt, .suspend =3D brcm_fet_suspend, .resume =3D brcm_fet_config_init, +}, { + .phy_id =3D PHY_ID_BCM5221, + .phy_id_mask =3D 0xfffffff0, + .name =3D "Broadcom BCM5221", + /* PHY_BASIC_FEATURES */ + .config_init =3D brcm_fet_config_init, + .config_intr =3D brcm_fet_config_intr, + .handle_interrupt =3D brcm_fet_handle_interrupt, + .suspend =3D brcm_fet_suspend, + .resume =3D brcm_fet_config_init, + .config_aneg =3D bcm5221_config_aneg, + .read_status =3D bcm5221_read_status, }, { .phy_id =3D PHY_ID_BCM5395, .phy_id_mask =3D 0xfffffff0, @@ -1154,6 +1242,7 @@ static struct mdio_device_id __maybe_unused broadcom_= tbl[] =3D { { PHY_ID_BCM50610M, 0xfffffff0 }, { PHY_ID_BCM57780, 0xfffffff0 }, { PHY_ID_BCMAC131, 0xfffffff0 }, + { PHY_ID_BCM5221, 0xfffffff0 }, { PHY_ID_BCM5241, 0xfffffff0 }, { PHY_ID_BCM5395, 0xfffffff0 }, { PHY_ID_BCM53125, 0xfffffff0 }, diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h index 9e77165f3ef6..ee1c8160e4d5 100644 --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h @@ -12,6 +12,7 @@ #define PHY_ID_BCM50610 0x0143bd60 #define PHY_ID_BCM50610M 0x0143bd70 #define PHY_ID_BCM5241 0x0143bc30 +#define PHY_ID_BCM5221 0x004061e0 #define PHY_ID_BCMAC131 0x0143bc70 #define PHY_ID_BCM5481 0x0143bca0 #define PHY_ID_BCM5395 0x0143bcf0 @@ -272,6 +273,15 @@ #define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34) #define BCM54612E_LED4_CLK125OUT_EN (1 << 1) =20 +/* BCM5221 Registers */ +#define BCM5221_AEGSR 0x1C +#define BCM5221_AEGSR_MDIX_STATUS BIT(13) +#define BCM5221_AEGSR_MDIX_MAN_SWAP BIT(12) +#define BCM5221_AEGSR_MDIX_DIS BIT(11) + +#define BCM5221_SHDW_AM4_EN_CLK_LPM BIT(2) +#define BCM5221_SHDW_AM4_FORCE_LPM BIT(1) + /*************************************************************************= ****/ /* Fast Ethernet Transceiver definitions. */ /*************************************************************************= ****/ --=20 2.34.1