From nobody Thu Dec 18 00:47:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6784DE732C7 for ; Thu, 28 Sep 2023 12:25:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231897AbjI1MZT (ORCPT ); Thu, 28 Sep 2023 08:25:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230476AbjI1MZQ (ORCPT ); Thu, 28 Sep 2023 08:25:16 -0400 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 547EA191; Thu, 28 Sep 2023 05:25:15 -0700 (PDT) Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38S8T5Rp005266; Thu, 28 Sep 2023 14:24:46 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=Murv1XK1UiktKIyTFV+yWE0qG+F/vgc4NPP2uXsTpV0=; b=tf 0b7t1hQ4zJsQwtkMVzVK+xkVf7RkuBjEReBfUQKpE1IeYR05jI+CBLLJu6zlQ+OK GEITtXGeRiTpqFOHynK9PjVFPoCeP0IA+SrGofx4qslPJGGt+5mGsFPFgSfSGWtp vpHAbD3nxPRhHYkE1dNNZR4cNIgfXfGkOa5bcNWEO74hl8hIA2smWDkL7nq1IAJs Et6N3Yeh05vNImszFzLz+Y00iy1D//Tlq/tuM3WzzSSZt1CEB/jtVVpm2J/reee8 9YA4VZVHwKBdHUJ9Kj8erdnBXfnSVkWoay2po6tHnOJhk2wvInW/RCeQy3gFzGvo RqAChAa7wErlU4r4NxXA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3taayhvsxs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Sep 2023 14:24:46 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 60713100058; Thu, 28 Sep 2023 14:24:33 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 23CBB2309DA; Thu, 28 Sep 2023 14:24:33 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Sep 2023 14:24:32 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 01/12] dt-bindings: net: add STM32MP13 compatible in documentation for stm32 Date: Thu, 28 Sep 2023 14:24:16 +0200 Message-ID: <20230928122427.313271-2-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" New STM32 SOC have 2 GMACs instances. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier --- .../devicetree/bindings/net/stm32-dwmac.yaml | 78 +++++++++++++++++-- 1 file changed, 70 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Docum= entation/devicetree/bindings/net/stm32-dwmac.yaml index fc8c96b08d7dc..ca976281bfc22 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -22,18 +22,17 @@ select: enum: - st,stm32-dwmac - st,stm32mp1-dwmac + - st,stm32mp13-dwmac required: - compatible =20 -allOf: - - $ref: snps,dwmac.yaml# - properties: compatible: oneOf: - items: - enum: - st,stm32mp1-dwmac + - st,stm32mp13-dwmac - const: snps,dwmac-4.20a - items: - enum: @@ -74,13 +73,10 @@ properties: =20 st,syscon: $ref: /schemas/types.yaml#/definitions/phandle-array - items: - - items: - - description: phandle to the syscon node which encompases the g= lue register - - description: offset of the control register description: Should be phandle/offset pair. The phandle to the syscon node which - encompases the glue register, and the offset of the control register + encompases the glue register, the offset of the control register and + the mask to set bitfield in control register =20 st,eth-clk-sel: description: @@ -101,6 +97,38 @@ required: =20 unevaluatedProperties: false =20 +allOf: + - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-dwmac + - st,stm32-dwmac + then: + properties: + st,syscon: + items: + items: + - description: phandle to the syscon node which encompases t= he glue register + - description: offset of the control register + + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp13-dwmac + then: + properties: + st,syscon: + items: + items: + - description: phandle to the syscon node which encompases t= he glue register + - description: offset of the control register + - description: field to set mask in register + examples: - | #include @@ -161,3 +189,37 @@ examples: snps,pbl =3D <8>; phy-mode =3D "mii"; }; + + - | + #include + #include + #include + #include + //Example 4 + ethernet3: ethernet@5800a000 { + compatible =3D "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg =3D <0x5800a000 0x2000>; + reg-names =3D "stmmaceth"; + interrupts-extended =3D <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "macirq", + "eth_wake_irq"; + clock-names =3D "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "eth-ck", + "ptp_ref", + "ethstp"; + clocks =3D <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHCK_K>, + <&rcc ETHPTP_K>, + <&rcc ETHSTP>; + st,syscon =3D <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl =3D <2>; + snps,axi-config =3D <&stmmac_axi_config_1>; + snps,tso; + phy-mode =3D "rmii"; + }; --=20 2.25.1