From nobody Wed Dec 17 03:02:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8EB3E732C5 for ; Thu, 28 Sep 2023 12:27:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232483AbjI1M1d (ORCPT ); Thu, 28 Sep 2023 08:27:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231752AbjI1M12 (ORCPT ); Thu, 28 Sep 2023 08:27:28 -0400 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2DBE619F; Thu, 28 Sep 2023 05:27:25 -0700 (PDT) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38S8WhQu001851; Thu, 28 Sep 2023 14:27:04 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=cI/WmtnEw+3W8sSwXOwhncPTGGl8x+aav3Xbrt5l6oA=; b=I+ HsJdvK7cPlX8hxnQmvuE1T+OW2TfnJTo48gzAuswOZ2wOetG4/XjmDtKOP/RCg8/ AmQOLLWxPkAgW/OdlJ19Mkj1ff+jOwMuCDuT3PFqo0VCGL7oxUW3cJov3d/c/91e lbii4GW/UPB0Fcblz/F3MWavrzZa+tarYAXQVGA0WbKKJh1uxykaLN+CDgYmekpN CIeoTEu9Cw6yf2HzykEk55h52Yc9MCIwRYlAhSZqFttMxuSC9DGjILHc6SvRBedK GnTnIu7ZalUCx1zP8m2HL5DFEBk+wyjPPOcggZh/83w60q+z292jB9S35I7/SSMO 0uQRB9010SmMUYANyXdA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3t9pwdf4jb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Sep 2023 14:27:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id F24F9100057; Thu, 28 Sep 2023 14:27:03 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E8DB822F7B0; Thu, 28 Sep 2023 14:27:03 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Sep 2023 14:27:01 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 11/12] ARM: dts: stm32: add ethernet1 and ethernet2 for STM32MP135F-DK board Date: Thu, 28 Sep 2023 14:24:26 +0200 Message-ID: <20230928122427.313271-12-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dual Ethernet: -Ethernet1: RMII with crystal -Ethernet2: RMII without crystal PHYs used are SMSC (LAN8742A) With Ethernet1, we can performed WoL from PHY instead of GMAC point of view. (in this case IRQ for WoL is managed as wakeup pin and configured in OS secure). Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 48 +++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st= /stm32mp135f-dk.dts index eea740d097c72..1316cc16f8dd9 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -19,6 +19,8 @@ / { compatible =3D "st,stm32mp135f-dk", "st,stm32mp135"; =20 aliases { + ethernet0 =3D ðernet1; + ethernet1 =3D ðernet2; serial0 =3D &uart4; serial1 =3D &usart1; serial2 =3D &uart8; @@ -93,6 +95,52 @@ channel@12 { }; }; =20 +ðernet1 { + status =3D "okay"; + pinctrl-0 =3D <ð1_rmii_pins_a>; + pinctrl-1 =3D <ð1_rmii_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + phy-mode =3D "rmii"; + max-speed =3D <100>; + phy-handle =3D <&phy0_eth1>; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy0_eth1: ethernet-phy@0 { + compatible =3D "ethernet-phy-id0007.c131"; + reset-gpios =3D <&mcp23017 9 GPIO_ACTIVE_LOW>; + reg =3D <0>; + wakeup-source; + }; + }; +}; + +ðernet2 { + status =3D "okay"; + pinctrl-0 =3D <ð2_rmii_pins_a>; + pinctrl-1 =3D <ð2_rmii_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + phy-mode =3D "rmii"; + max-speed =3D <100>; + phy-handle =3D <&phy0_eth2>; + st,ext-phyclk; + phy-supply =3D <&scmi_v3v3_sw>; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + phy0_eth2: ethernet-phy@0 { + compatible =3D "ethernet-phy-id0007.c131"; + reset-gpios =3D <&mcp23017 10 GPIO_ACTIVE_LOW>; + reg =3D <0>; + }; + }; +}; + &i2c1 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&i2c1_pins_a>; --=20 2.25.1