From nobody Wed Dec 17 11:33:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A011CE7AF8 for ; Thu, 28 Sep 2023 06:13:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230322AbjI1GNX (ORCPT ); Thu, 28 Sep 2023 02:13:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230320AbjI1GNO (ORCPT ); Thu, 28 Sep 2023 02:13:14 -0400 Received: from mail-il1-x135.google.com (mail-il1-x135.google.com [IPv6:2607:f8b0:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09D51CC8 for ; Wed, 27 Sep 2023 23:13:09 -0700 (PDT) Received: by mail-il1-x135.google.com with SMTP id e9e14a558f8ab-34fcd361e91so40292505ab.3 for ; Wed, 27 Sep 2023 23:13:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695881588; x=1696486388; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2RNpF/CWjVyq2jAidq9g4JrMuQdRaRtl2xGmvH6ydPA=; b=JJJIj228h3I63YzUl5CpR1kZCAw2t5ZVK9s5fEZqautPwLVZQsnhe9bWsIP9xFx8u9 yRRAsM3d458XQBfEL12NVQkwvrlB+pYF/GqzdGl36bidlDtLKEZCrJ8d+Gm7J9uoTXPf 1Ew+YsQ/z/oi1V1rbPm1HmSgch/cmt9tXGUA+To8qCC9vygPPQBojp+cKtABnvjoMpLI J4GrPNWI7W8TYDAdaFXuYgijPBTS0b1gWyzAleVQlcj5Y7k+SSjzMDoqPziLDnc77Zy0 UVFxxu6I5yqSRqskyeEd0QadWtWn1vTUhezBV3gZBc8i6FFp5YYOiJ84gRmKEd9pR02p j94Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695881588; x=1696486388; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2RNpF/CWjVyq2jAidq9g4JrMuQdRaRtl2xGmvH6ydPA=; b=m6hw8H+CjeTUcWVXer/hfoE3mgnEdnQY3ugNkFH37zOyT5AUw+o3D9MwqxdKJHgib7 PD1De55N1dXJrFEuvk2RfCdVpARxqQsgcaELWBgW2hcUmSnFlKbW7cFXFQVBw/qm4c+U 8cu3ijvS/Nz197kHNs2zceJyVu4MPl5VKj2Ha8diKKQMCTnmzdAUhgaCNPYpoRuaP42w Jvgjyw5Wakvgq19/94VPIxLovUDivLUWRWwOLaPqh/AaUW7VTjtWQTu5KnIh+C+ic8OW KlP/wfas2xVDdUwzSz9cISnag84dBAFgLncaOxisUvLk+yrw8l0yTiAVhkR6FrM+9qKO 8Vnw== X-Gm-Message-State: AOJu0YwY51klfCFkKZh451l488IiyNwd7EVDvd3kyEeCIGrxZu1szJgf I2pXPz8GrGIpbztBybaXkNOZkA== X-Google-Smtp-Source: AGHT+IEotbOVXUCkqSio+ScJRog1NdMBtHM4sprozsR+N8OisZeWL+yYTB9LK6keDhR+05tqLZzJ9w== X-Received: by 2002:a05:6e02:ca5:b0:350:f510:3990 with SMTP id 5-20020a056e020ca500b00350f5103990mr229352ilg.2.1695881588242; Wed, 27 Sep 2023 23:13:08 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id x6-20020a92d306000000b003506f457d70sm4774467ila.63.2023.09.27.23.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 23:13:07 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v9 06/15] irqchip/riscv-intc: Add support for RISC-V AIA Date: Thu, 28 Sep 2023 11:41:58 +0530 Message-Id: <20230928061207.1841513-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230928061207.1841513-1-apatel@ventanamicro.com> References: <20230928061207.1841513-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V advanced interrupt architecture (AIA) extends the per-HART local interrupts in following ways: 1. Minimum 64 local interrupts for both RV32 and RV64 2. Ability to process multiple pending local interrupts in same interrupt handler 3. Priority configuration for each local interrupts 4. Special CSRs to configure/access the per-HART MSI controller We add support for #1 and #2 described above in the RISC-V intc driver. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-intc.c | 34 ++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index e8d01b14ccdd..bab536bbaf2c 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 static struct irq_domain *intc_domain; =20 @@ -30,6 +31,15 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *re= gs) generic_handle_domain_irq(intc_domain, cause); } =20 +static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs) +{ + unsigned long topi; + + while ((topi =3D csr_read(CSR_TOPI))) + generic_handle_domain_irq(intc_domain, + topi >> TOPI_IID_SHIFT); +} + /* * On RISC-V systems local interrupts are masked or unmasked by writing * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written @@ -39,12 +49,18 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *r= egs) =20 static void riscv_intc_irq_mask(struct irq_data *d) { - csr_clear(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >=3D BITS_PER_LONG) + csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_clear(CSR_IE, BIT(d->hwirq)); } =20 static void riscv_intc_irq_unmask(struct irq_data *d) { - csr_set(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >=3D BITS_PER_LONG) + csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_set(CSR_IE, BIT(d->hwirq)); } =20 static void riscv_intc_irq_eoi(struct irq_data *d) @@ -115,16 +131,20 @@ static struct fwnode_handle *riscv_intc_hwnode(void) =20 static int __init riscv_intc_init_common(struct fwnode_handle *fn) { - int rc; + int rc, nr_irqs =3D riscv_isa_extension_available(NULL, SxAIA) ? + 64 : BITS_PER_LONG; =20 - intc_domain =3D irq_domain_create_linear(fn, BITS_PER_LONG, + intc_domain =3D irq_domain_create_linear(fn, nr_irqs, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; } =20 - rc =3D set_handle_irq(&riscv_intc_irq); + if (riscv_isa_extension_available(NULL, SxAIA)) + rc =3D set_handle_irq(&riscv_intc_aia_irq); + else + rc =3D set_handle_irq(&riscv_intc_irq); if (rc) { pr_err("failed to set irq handler\n"); return rc; @@ -132,7 +152,9 @@ static int __init riscv_intc_init_common(struct fwnode_= handle *fn) =20 riscv_set_intc_hwnode_fn(riscv_intc_hwnode); =20 - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + pr_info("%d local interrupts mapped%s\n", + nr_irqs, riscv_isa_extension_available(NULL, SxAIA) ? + " using AIA" : ""); =20 return 0; } --=20 2.34.1