From nobody Wed Dec 17 11:33:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55D59CE7AF8 for ; Thu, 28 Sep 2023 06:13:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229758AbjI1GNQ (ORCPT ); Thu, 28 Sep 2023 02:13:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230286AbjI1GNE (ORCPT ); Thu, 28 Sep 2023 02:13:04 -0400 Received: from mail-il1-x134.google.com (mail-il1-x134.google.com [IPv6:2607:f8b0:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11735198 for ; Wed, 27 Sep 2023 23:13:02 -0700 (PDT) Received: by mail-il1-x134.google.com with SMTP id e9e14a558f8ab-3513c435465so21635545ab.0 for ; Wed, 27 Sep 2023 23:13:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695881581; x=1696486381; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1kZdHbQi5V7lhsIUGs26feO8O90Ud7R7H4FmzjD+o+k=; b=XtXt77Fc7uF8cuyPrGBYQgJChh9Ao/50v+Z2G8IwF18wejbKFPXlW+JAUQAwra5noA A9RBXCJKCFV7fbv0nUVQehHOgMkm4xDILEpcV+PdmaFCuJnhOl4Sm10rvM+5zqHHYCGJ cp7wI7nObt5FppudNeS9y9d/Mh76fUILjIc9LnoM9atF3orkgh3o6Ak0L4vjUlvuJz72 YNFRFwpeJPKmKsOC6xKNDf21ogq4lsOw/jhtAIbOhqGyPkLRZOZZm1I23NuEpDDdJaOF ohfM5bxxcbOlGzJDiD5SPfNb4kx6TITMFyHqMiHvOJ4H+MHMUj3fFsCAQASLStieV+/W z1Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695881581; x=1696486381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1kZdHbQi5V7lhsIUGs26feO8O90Ud7R7H4FmzjD+o+k=; b=Q+K56+jPPqilGnQpdLkvsl83K8By/u3wmQ+ypIcsGFKTlvYToGWJWskpHeROHfzN6z WrdM4H2y6dCdaYSQoBKJht4+kyTOLw72HXC+VC9adbkDoXnb4Bdl3IV7PkOYjv6nHoDu iTAbJbASBcyYoHpcUbOhY+xqyk+2OwgQl5FoFotRlXqowPCYTBmybakhL9YkWvIFezLQ Ef34ti/1QQ3QD/CkOZKSPKRlVjVmnSFnfikYTTO+1xkimzchObZCczaZOFRUTbAjLPbZ m9sFywApBEV5ndkZrpfrPS8uRRaSURU9g7us9GeeOFpczQCGk/6v2z9UvVwv5DBA0zEu MrIg== X-Gm-Message-State: AOJu0YwKNQNEUA1PY9NAsmpWZtCxrf4yUukmIcSE8NGNwm43l/YYA+o1 t4ayRtRmBX4SGnw42tmc6WezPw== X-Google-Smtp-Source: AGHT+IGk52HzjyJAa11hyFx+NISxkwfu/DTaVvtwknu16hUlY5TmRPZeLmgFL4oZr3l4uJzha07SUQ== X-Received: by 2002:a05:6e02:1d16:b0:34f:65b0:7f1b with SMTP id i22-20020a056e021d1600b0034f65b07f1bmr331909ila.6.1695881581241; Wed, 27 Sep 2023 23:13:01 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id x6-20020a92d306000000b003506f457d70sm4774467ila.63.2023.09.27.23.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 23:13:00 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v9 05/15] irqchip/sifive-plic: Convert PLIC driver into a platform driver Date: Thu, 28 Sep 2023 11:41:57 +0530 Message-Id: <20230928061207.1841513-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230928061207.1841513-1-apatel@ventanamicro.com> References: <20230928061207.1841513-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The PLIC driver does not require very early initialization so let us convert it into a platform driver. As part of the conversion, the PLIC probing undergoes the following changes: 1. Use dev_info(), dev_err() and dev_warn() instead of pr_info(), pr_err() and pr_warn() 2. Use devm_xyz() APIs wherever applicable 3. PLIC is now probed after CPUs are brought-up so we have to setup cpuhp state after context handler of all online CPUs are initialized otherwise we see crash on multi-socket systems Signed-off-by: Anup Patel --- drivers/irqchip/irq-sifive-plic.c | 242 +++++++++++++++++++----------- 1 file changed, 154 insertions(+), 88 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 5b7bc4fd9517..6f0af8b688f8 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -3,7 +3,6 @@ * Copyright (C) 2017 SiFive * Copyright (C) 2018 Christoph Hellwig */ -#define pr_fmt(fmt) "plic: " fmt #include #include #include @@ -64,6 +63,7 @@ #define PLIC_QUIRK_EDGE_INTERRUPT 0 =20 struct plic_priv { + struct device *dev; struct cpumask lmask; struct irq_domain *irqdomain; void __iomem *regs; @@ -85,7 +85,6 @@ struct plic_handler { struct plic_priv *priv; }; static int plic_parent_irq __ro_after_init; -static bool plic_cpuhp_setup_done __ro_after_init; static DEFINE_PER_CPU(struct plic_handler, plic_handlers); =20 static int plic_irq_set_type(struct irq_data *d, unsigned int type); @@ -371,7 +370,8 @@ static void plic_handle_irq(struct irq_desc *desc) int err =3D generic_handle_domain_irq(handler->priv->irqdomain, hwirq); if (unlikely(err)) - pr_warn_ratelimited("can't find mapping for hwirq %lu\n", + dev_warn_ratelimited(handler->priv->dev, + "can't find mapping for hwirq %lu\n", hwirq); } =20 @@ -406,57 +406,126 @@ static int plic_starting_cpu(unsigned int cpu) return 0; } =20 -static int __init __plic_init(struct device_node *node, - struct device_node *parent, - unsigned long plic_quirks) +static const struct of_device_id plic_match[] =3D { + { .compatible =3D "sifive,plic-1.0.0" }, + { .compatible =3D "riscv,plic0" }, + { .compatible =3D "andestech,nceplic100", + .data =3D (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, + { .compatible =3D "thead,c900-plic", + .data =3D (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) }, + {} +}; + +static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev, + u32 *nr_irqs, u32 *nr_contexts) { - int error =3D 0, nr_contexts, nr_handlers =3D 0, i; - u32 nr_irqs; - struct plic_priv *priv; + struct device *dev =3D &pdev->dev; + int rc; + + /* + * Currently, only OF fwnode is supported so extend this + * function for ACPI support. + */ + if (!is_of_node(dev->fwnode)) + return -EINVAL; + + rc =3D of_property_read_u32(to_of_node(dev->fwnode), + "riscv,ndev", nr_irqs); + if (rc) { + dev_err(dev, "riscv,ndev property not available\n"); + return rc; + } + + *nr_contexts =3D of_irq_count(to_of_node(dev->fwnode)); + if (WARN_ON(!(*nr_contexts))) { + dev_err(dev, "no PLIC context available\n"); + return -EINVAL; + } + + return 0; +} + +static int plic_parse_context_parent_hwirq(struct platform_device *pdev, + u32 context, u32 *parent_hwirq, + unsigned long *parent_hartid) +{ + struct device *dev =3D &pdev->dev; + struct of_phandle_args parent; + int rc; + + /* + * Currently, only OF fwnode is supported so extend this + * function for ACPI support. + */ + if (!is_of_node(dev->fwnode)) + return -EINVAL; + + rc =3D of_irq_parse_one(to_of_node(dev->fwnode), context, &parent); + if (rc) + return rc; + + rc =3D riscv_of_parent_hartid(parent.np, parent_hartid); + if (rc) + return rc; + + *parent_hwirq =3D parent.args[0]; + return 0; +} + +static int plic_probe(struct platform_device *pdev) +{ + int rc, nr_contexts, nr_handlers =3D 0, i, cpu; + unsigned long plic_quirks =3D 0, hartid; + struct device *dev =3D &pdev->dev; struct plic_handler *handler; - unsigned int cpu; + u32 nr_irqs, parent_hwirq; + struct irq_domain *domain; + struct plic_priv *priv; + irq_hw_number_t hwirq; + struct resource *res; + bool cpuhp_setup; =20 - priv =3D kzalloc(sizeof(*priv), GFP_KERNEL); + if (is_of_node(dev->fwnode)) { + const struct of_device_id *id; + + id =3D of_match_node(plic_match, to_of_node(dev->fwnode)); + if (id) + plic_quirks =3D (unsigned long)id->data; + } + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; - + priv->dev =3D dev; priv->plic_quirks =3D plic_quirks; =20 - priv->regs =3D of_iomap(node, 0); - if (WARN_ON(!priv->regs)) { - error =3D -EIO; - goto out_free_priv; + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "failed to get MMIO resource\n"); + return -EINVAL; + } + priv->regs =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!priv->regs) { + dev_err(dev, "failed map MMIO registers\n"); + return -EIO; } =20 - error =3D -EINVAL; - of_property_read_u32(node, "riscv,ndev", &nr_irqs); - if (WARN_ON(!nr_irqs)) - goto out_iounmap; - + rc =3D plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts); + if (rc) { + dev_err(dev, "failed to parse irqs and contexts\n"); + return rc; + } priv->nr_irqs =3D nr_irqs; =20 - priv->prio_save =3D bitmap_alloc(nr_irqs, GFP_KERNEL); + priv->prio_save =3D devm_bitmap_zalloc(dev, nr_irqs, GFP_KERNEL); if (!priv->prio_save) - goto out_free_priority_reg; - - nr_contexts =3D of_irq_count(node); - if (WARN_ON(!nr_contexts)) - goto out_free_priority_reg; - - error =3D -ENOMEM; - priv->irqdomain =3D irq_domain_add_linear(node, nr_irqs + 1, - &plic_irqdomain_ops, priv); - if (WARN_ON(!priv->irqdomain)) - goto out_free_priority_reg; + return -ENOMEM; =20 for (i =3D 0; i < nr_contexts; i++) { - struct of_phandle_args parent; - irq_hw_number_t hwirq; - int cpu; - unsigned long hartid; - - if (of_irq_parse_one(node, i, &parent)) { - pr_err("failed to parse parent for context %d.\n", i); + rc =3D plic_parse_context_parent_hwirq(pdev, i, + &parent_hwirq, &hartid); + if (rc) { + dev_warn(dev, "hwirq for context%d not found\n", i); continue; } =20 @@ -464,7 +533,7 @@ static int __init __plic_init(struct device_node *node, * Skip contexts other than external interrupts for our * privilege level. */ - if (parent.args[0] !=3D RV_IRQ_EXT) { + if (parent_hwirq !=3D RV_IRQ_EXT) { /* Disable S-mode enable bits if running in M-mode. */ if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { void __iomem *enable_base =3D priv->regs + @@ -477,21 +546,17 @@ static int __init __plic_init(struct device_node *nod= e, continue; } =20 - error =3D riscv_of_parent_hartid(parent.np, &hartid); - if (error < 0) { - pr_warn("failed to parse hart ID for context %d.\n", i); - continue; - } - cpu =3D riscv_hartid_to_cpuid(hartid); if (cpu < 0) { - pr_warn("Invalid cpuid for context %d\n", i); + dev_warn(dev, "Invalid cpuid for context %d\n", i); continue; } =20 /* Find parent domain and register chained handler */ - if (!plic_parent_irq && irq_find_host(parent.np)) { - plic_parent_irq =3D irq_of_parse_and_map(node, i); + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), + DOMAIN_BUS_ANY); + if (!plic_parent_irq && domain) { + plic_parent_irq =3D irq_create_mapping(domain, RV_IRQ_EXT); if (plic_parent_irq) irq_set_chained_handler(plic_parent_irq, plic_handle_irq); @@ -504,7 +569,7 @@ static int __init __plic_init(struct device_node *node, */ handler =3D per_cpu_ptr(&plic_handlers, cpu); if (handler->present) { - pr_warn("handler already present for context %d.\n", i); + dev_warn(dev, "handler already present for context%d.\n", i); plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD); goto done; } @@ -518,10 +583,13 @@ static int __init __plic_init(struct device_node *nod= e, i * CONTEXT_ENABLE_SIZE; handler->priv =3D priv; =20 - handler->enable_save =3D kcalloc(DIV_ROUND_UP(nr_irqs, 32), - sizeof(*handler->enable_save), GFP_KERNEL); + handler->enable_save =3D devm_kcalloc(dev, + DIV_ROUND_UP(nr_irqs, 32), + sizeof(*handler->enable_save), + GFP_KERNEL); if (!handler->enable_save) - goto out_free_enable_reg; + return -ENOMEM; + done: for (hwirq =3D 1; hwirq <=3D nr_irqs; hwirq++) { plic_toggle(handler, hwirq, 0); @@ -531,52 +599,50 @@ static int __init __plic_init(struct device_node *nod= e, nr_handlers++; } =20 + priv->irqdomain =3D irq_domain_create_linear(dev->fwnode, nr_irqs + 1, + &plic_irqdomain_ops, priv); + if (WARN_ON(!priv->irqdomain)) + return -ENOMEM; + /* * We can have multiple PLIC instances so setup cpuhp state - * and register syscore operations only when context handler - * for current/boot CPU is present. + * and register syscore operations only after context handlers + * of all online CPUs are initialized. */ - handler =3D this_cpu_ptr(&plic_handlers); - if (handler->present && !plic_cpuhp_setup_done) { + cpuhp_setup =3D true; + for_each_online_cpu(cpu) { + handler =3D per_cpu_ptr(&plic_handlers, cpu); + if (!handler->present) { + cpuhp_setup =3D false; + break; + } + } + if (cpuhp_setup) { cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, "irqchip/sifive/plic:starting", plic_starting_cpu, plic_dying_cpu); register_syscore_ops(&plic_irq_syscore_ops); - plic_cpuhp_setup_done =3D true; } =20 - pr_info("%pOFP: mapped %d interrupts with %d handlers for" - " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts); + dev_info(dev, "mapped %d interrupts with %d handlers for" + " %d contexts.\n", nr_irqs, nr_handlers, nr_contexts); return 0; - -out_free_enable_reg: - for_each_cpu(cpu, cpu_present_mask) { - handler =3D per_cpu_ptr(&plic_handlers, cpu); - kfree(handler->enable_save); - } -out_free_priority_reg: - kfree(priv->prio_save); -out_iounmap: - iounmap(priv->regs); -out_free_priv: - kfree(priv); - return error; -} - -static int __init plic_init(struct device_node *node, - struct device_node *parent) -{ - return __plic_init(node, parent, 0); } =20 -IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); -IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy syst= ems */ +static struct platform_driver plic_driver =3D { + .driver =3D { + .name =3D "riscv-plic", + .of_match_table =3D plic_match, + }, + .probe =3D plic_probe, +}; =20 -static int __init plic_edge_init(struct device_node *node, - struct device_node *parent) +static int __init plic_init(void) { - return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT)); + /* + * Register PLIC driver as early as possible so that PLIC + * platform device is probed as soon as it is created. + */ + return platform_driver_register(&plic_driver); } - -IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_in= it); -IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init); +core_initcall(plic_init); --=20 2.34.1