From nobody Wed Dec 17 11:37:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D626CE7AFD for ; Thu, 28 Sep 2023 06:14:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230254AbjI1GOD (ORCPT ); Thu, 28 Sep 2023 02:14:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230363AbjI1GNt (ORCPT ); Thu, 28 Sep 2023 02:13:49 -0400 Received: from mail-il1-x136.google.com (mail-il1-x136.google.com [IPv6:2607:f8b0:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88170CD9 for ; Wed, 27 Sep 2023 23:13:46 -0700 (PDT) Received: by mail-il1-x136.google.com with SMTP id e9e14a558f8ab-35133097583so30272175ab.1 for ; Wed, 27 Sep 2023 23:13:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695881626; x=1696486426; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TYQsgV6mmNiNxm7fkk00HaM0IkP9BeYIjrigTOut9Eg=; b=M6KklU3pBNzLl5WmoH3yCRVU5VHFhXvgu+f2wE5eg6hj6NdUC8Fm9YRwu7KeTEMsxl fOmVVjzxeHUzJBBNBZZpoFDIOv9d9YZHWAwmsxTayLuKR3oH75dtPieOzedrKZhMUFx9 3ISAd1AwDiV87ZIJzZ1mQFoS4KMZ/mrTSWDKFtQ0Qa884+brdk7hYmTdA4mOJFwDq/qw TgltUtwJ/l3IhF9H5FEqYHBn0+hv7GW7jJVtGJ86V5PWqI6RiZicEV7fd96R8P6gKdYM RdaXxL7Szse8x6IyXq4cwmZaMhNpCi7o41ty6dzcOLWNzaao0mYFp2nWpFurdn7GkYFH Pxhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695881626; x=1696486426; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TYQsgV6mmNiNxm7fkk00HaM0IkP9BeYIjrigTOut9Eg=; b=GoP7VPWZBsCnFe+ZtOo5hRTkH3GhFbpN101cpOa/G5CZXdSN2mfcAjFVgTvd8oHamL 4wp+8CiFsp4pJKbHoh8MCB5nX9RHJCV+hcPkqYaNsQGoo8MFtfE13b8/yD8OCyKm54s5 cICWbKlazu8yS2Bex/sKlShTM18R1XwGtI40dDHywxkILhPDMe2R2BZX9dUhxLCH0GuK Vs0makEvOPXkSx8aPvXcgedOxvfp+ZGJTXnlLjcp0zzGiNZjF9PfOX8MaWrzFcqkoZi0 gsB1dRE5Qu7WHAGUj6f+oX/ToFGw1YrsJ/NPpTt1vBD4+zrBTWXMnIOtItovEDLxXhlF iikA== X-Gm-Message-State: AOJu0Yyl7kTUV2bVqOGnvu3gwVtv8pmHSs4U1p5/XZxAfJiTv1xj/9Wo S1Clvzb1C0KdN8uZcMKUNTp6+Q== X-Google-Smtp-Source: AGHT+IFHxRlB8KG13J5812BYrEYwvK3uWjNG9IhzS5X1exjc7sk/2qLrrEFhTfu4tyhJ/jo9ArWW6Q== X-Received: by 2002:a05:6e02:1646:b0:34b:ad80:61c1 with SMTP id v6-20020a056e02164600b0034bad8061c1mr299476ilu.26.1695881625655; Wed, 27 Sep 2023 23:13:45 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id x6-20020a92d306000000b003506f457d70sm4774467ila.63.2023.09.27.23.13.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 23:13:45 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Conor Dooley Subject: [PATCH v9 11/15] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Date: Thu, 28 Sep 2023 11:42:03 +0530 Message-Id: <20230928061207.1841513-12-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230928061207.1841513-1-apatel@ventanamicro.com> References: <20230928061207.1841513-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add DT bindings document for RISC-V advanced platform level interrupt controller (APLIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley --- .../interrupt-controller/riscv,aplic.yaml | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,aplic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,a= plic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,ap= lic.yaml new file mode 100644 index 000000000000..190a6499c932 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.ya= ml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Advanced Platform Level Interrupt Controller (APLIC) + +maintainers: + - Anup Patel + +description: + The RISC-V advanced interrupt architecture (AIA) defines an advanced + platform level interrupt controller (APLIC) for handling wired interrupts + in a RISC-V platform. The RISC-V AIA specification can be found at + https://github.com/riscv/riscv-aia. + + The RISC-V APLIC is implemented as hierarchical APLIC domains where all + interrupt sources connect to the root APLIC domain and a parent APLIC + domain can delegate interrupt sources to it's child APLIC domains. There + is one device tree node for each APLIC domain. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + items: + - enum: + - qemu,aplic + - const: riscv,aplic + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts-extended: + minItems: 1 + maxItems: 16384 + description: + Given APLIC domain directly injects external interrupts to a set of + RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-i= ntc + node, which has a CPU node (i.e. RISC-V HART) as parent. + + msi-parent: + description: + Given APLIC domain forwards wired interrupts as MSIs to a AIA incomi= ng + message signaled interrupt controller (IMSIC). If both "msi-parent" = and + "interrupts-extended" properties are present then it means the APLIC + domain supports both MSI mode and Direct mode in HW. In this case, t= he + APLIC driver has to choose between MSI mode or Direct mode. + + riscv,num-sources: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 1023 + description: + Specifies the number of wired interrupt sources supported by this + APLIC domain. + + riscv,children: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + maxItems: 1 + description: + A list of child APLIC domains for the given APLIC domain. Each child + APLIC domain is assigned a child index in increasing order, with the + first child APLIC domain assigned child index 0. The APLIC domain ch= ild + index is used by firmware to delegate interrupts from the given APLIC + domain to a particular child APLIC domain. + + riscv,delegation: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + items: + - description: child APLIC domain phandle + - description: first interrupt number of the parent APLIC domain (= inclusive) + - description: last interrupt number of the parent APLIC domain (i= nclusive) + description: + A interrupt delegation list where each entry is a triple consisting + of child APLIC domain phandle, first interrupt number of the parent + APLIC domain, and last interrupt number of the parent APLIC domain. + Firmware must configure interrupt delegation registers based on + interrupt delegation list. + +dependencies: + riscv,delegation: [ "riscv,children" ] + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - riscv,num-sources + +anyOf: + - required: + - interrupts-extended + - required: + - msi-parent + +unevaluatedProperties: false + +examples: + - | + // Example 1 (APLIC domains directly injecting interrupt to HARTs): + + interrupt-controller@c000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu1_intc 11>, + <&cpu2_intc 11>, + <&cpu3_intc 11>, + <&cpu4_intc 11>; + reg =3D <0xc000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + riscv,children =3D <&aplic1>, <&aplic2>; + riscv,delegation =3D <&aplic1 1 63>; + }; + + aplic1: interrupt-controller@d000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu1_intc 9>, + <&cpu2_intc 9>; + reg =3D <0xd000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; + + aplic2: interrupt-controller@e000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu3_intc 9>, + <&cpu4_intc 9>; + reg =3D <0xe000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; + + - | + // Example 2 (APLIC domains forwarding interrupts as MSIs): + + interrupt-controller@c000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + msi-parent =3D <&imsic_mlevel>; + reg =3D <0xc000000 0x4000>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + riscv,children =3D <&aplic3>; + riscv,delegation =3D <&aplic3 1 63>; + }; + + aplic3: interrupt-controller@d000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + msi-parent =3D <&imsic_slevel>; + reg =3D <0xd000000 0x4000>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; +... --=20 2.34.1