From nobody Wed Dec 17 11:33:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1A49CE7AFD for ; Thu, 28 Sep 2023 06:14:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230238AbjI1GOB (ORCPT ); Thu, 28 Sep 2023 02:14:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230324AbjI1GNk (ORCPT ); Thu, 28 Sep 2023 02:13:40 -0400 Received: from mail-il1-x131.google.com (mail-il1-x131.google.com [IPv6:2607:f8b0:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A18B1B8 for ; Wed, 27 Sep 2023 23:13:39 -0700 (PDT) Received: by mail-il1-x131.google.com with SMTP id e9e14a558f8ab-35135f69de2so27611395ab.2 for ; Wed, 27 Sep 2023 23:13:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695881618; x=1696486418; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JoIL0Jbseu5eDdAqizehsVqw8hc2kpCMN0j94MZf3VE=; b=bMjPchngA5GYA0L3ZR4aqTl/q/1KmbUQ/HcfMyL7PNiMtNhrBR8KciyaZsC2K/ynUn qihXdm9JCDhXp2gTa4BYjZ/X3AXnvXT+ddaDeDnPi5Cc3467Y1st0pxg6ClTtZr7vnRb dmhNWOD7uTEgfFj/hhb+lTbARZ78rwsjWApucmu20AGBE7zwer0Nf2s3F940GTZQqdw8 GFozfn//2r2NW/uanSTGYbP6sNq2IxA0c1A40FvGOEowiwc5RZy1lfEOOUOjQqrG064h LhHCeDQWorKUKb2glg64M8n6ig/bckFsScQU41bt8loyqbdf3caPrhai9tLE7qhiDwf+ wgtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695881618; x=1696486418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JoIL0Jbseu5eDdAqizehsVqw8hc2kpCMN0j94MZf3VE=; b=QiDF00bq6Ksgi3LyjvNkFmglxdEM6A6+XKYIFX2ovuRRUR1w2lqzQP2isMOjm1oQsZ TqNkfRnRetw46zh7wa/XkaAqJBSs27lIyhq+++mI+Zg7yODj/8rVwX8awns9M2nEQWin BPY6kh1b7jIot0BN4yixjQPhlfMeVgc/0vuPNQiKleGI3v0WC0my56s4Q+r0nP1eFfu/ ixTWWqWzOX2DtbwQ6RVSXO9bZeWHZIDNCxVatO9Abeq0HY9daOD+DDWE1FTB5Xt3ZyQK TeB205Y9sJorzscGHXok6TCK7hz7AE6DLq/rdas6zjJrEBJKWwWhYJUykLuejFHv/Swo rX4g== X-Gm-Message-State: AOJu0YyEzDTt4ai2mEjO4jQfdSs3guKMxx1c8/yfbqviSND8nY3zORoC lZA0EkQsHILi3LYsG/F0bHFVZw== X-Google-Smtp-Source: AGHT+IGdD6X9RPc5QmfMm/xZzpNZ7869FVoao2wFVWLH0UL/EtMhXXLxISL14XYAdn3sOjv4dptsfg== X-Received: by 2002:a05:6e02:2148:b0:348:ba80:5a37 with SMTP id d8-20020a056e02214800b00348ba805a37mr396167ilv.0.1695881618314; Wed, 27 Sep 2023 23:13:38 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id x6-20020a92d306000000b003506f457d70sm4774467ila.63.2023.09.27.23.13.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 23:13:37 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v9 10/15] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Date: Thu, 28 Sep 2023 11:42:02 +0530 Message-Id: <20230928061207.1841513-11-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230928061207.1841513-1-apatel@ventanamicro.com> References: <20230928061207.1841513-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Linux PCI framework requires it's own dedicated MSI irqdomain so let us create PCI MSI irqdomain as child of the IMSIC base irqdomain. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 ++++ drivers/irqchip/irq-riscv-imsic-platform.c | 48 ++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 1 + 3 files changed, 56 insertions(+) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index bdd80716114d..c1d69b418dfb 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -552,6 +552,13 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_MSI_IRQ =20 +config RISCV_IMSIC_PCI + bool + depends on RISCV_IMSIC + depends on PCI + depends on PCI_MSI + default RISCV_IMSIC + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index b78f1b2ee3dc..ff737b4e195f 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -184,6 +185,39 @@ static const struct irq_domain_ops imsic_base_domain_o= ps =3D { .free =3D imsic_irq_domain_free, }; =20 +#ifdef CONFIG_RISCV_IMSIC_PCI + +static void imsic_pci_mask_irq(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void imsic_pci_unmask_irq(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static struct irq_chip imsic_pci_irq_chip =3D { + .name =3D "IMSIC-PCI", + .irq_mask =3D imsic_pci_mask_irq, + .irq_unmask =3D imsic_pci_unmask_irq, + .irq_eoi =3D irq_chip_eoi_parent, +}; + +static struct msi_domain_ops imsic_pci_domain_ops =3D { +}; + +static struct msi_domain_info imsic_pci_domain_info =3D { + .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), + .ops =3D &imsic_pci_domain_ops, + .chip =3D &imsic_pci_irq_chip, +}; + +#endif + static struct irq_chip imsic_plat_irq_chip =3D { .name =3D "IMSIC-PLAT", }; @@ -208,12 +242,26 @@ static int imsic_irq_domains_init(struct device *dev) } irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); =20 +#ifdef CONFIG_RISCV_IMSIC_PCI + /* Create PCI MSI domain */ + imsic->pci_domain =3D pci_msi_create_irq_domain(dev->fwnode, + &imsic_pci_domain_info, + imsic->base_domain); + if (!imsic->pci_domain) { + dev_err(dev, "failed to create IMSIC PCI domain\n"); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } +#endif + /* Create Platform MSI domain */ imsic->plat_domain =3D platform_msi_create_irq_domain(dev->fwnode, &imsic_plat_domain_info, imsic->base_domain); if (!imsic->plat_domain) { dev_err(dev, "failed to create IMSIC platform domain\n"); + if (imsic->pci_domain) + irq_domain_remove(imsic->pci_domain); irq_domain_remove(imsic->base_domain); return -ENOMEM; } diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-= riscv-imsic-state.h index 3170018949a8..ff3c377b9b33 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -31,6 +31,7 @@ struct imsic_priv { =20 /* IRQ domains (created by platform driver) */ struct irq_domain *base_domain; + struct irq_domain *pci_domain; struct irq_domain *plat_domain; }; =20 --=20 2.34.1