From nobody Fri Sep 12 11:38:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AF6EE82CB7 for ; Thu, 28 Sep 2023 01:14:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229945AbjI1BN7 (ORCPT ); Wed, 27 Sep 2023 21:13:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229437AbjI1BN6 (ORCPT ); Wed, 27 Sep 2023 21:13:58 -0400 Received: from out30-112.freemail.mail.aliyun.com (out30-112.freemail.mail.aliyun.com [115.124.30.112]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 049CCBF for ; Wed, 27 Sep 2023 18:13:55 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R111e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046051;MF=yang.lee@linux.alibaba.com;NM=1;PH=DS;RN=7;SR=0;TI=SMTPD_---0Vt.c2tB_1695863632; Received: from localhost(mailfrom:yang.lee@linux.alibaba.com fp:SMTPD_---0Vt.c2tB_1695863632) by smtp.aliyun-inc.com; Thu, 28 Sep 2023 09:13:53 +0800 From: Yang Li To: alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yang Li Subject: [PATCH -next] drm/amd/display: clean up some inconsistent indentings Date: Thu, 28 Sep 2023 09:13:51 +0800 Message-Id: <20230928011351.110093-1-yang.lee@linux.alibaba.com> X-Mailer: git-send-email 2.20.1.7.g153144c MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn35/dcn35_fpu.c:261 dcn35_up= date_bw_bounding_box_fpu() warn: inconsistent indenting Signed-off-by: Yang Li --- .../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 144 +++++++++--------- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers= /gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index 4d5ee2aad9e4..4f284c31de5d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -258,85 +258,85 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc, =20 dc_assert_fp_enabled(); =20 - dcn3_5_ip.max_num_otg =3D - dc->res_pool->res_cap->num_timing_generator; - dcn3_5_ip.max_num_dpp =3D dc->res_pool->pipe_count; - dcn3_5_soc.num_chans =3D bw_params->num_channels; - - ASSERT(clk_table->num_entries); - - /* Prepass to find max clocks independent of voltage level. */ - for (i =3D 0; i < clk_table->num_entries; ++i) { - if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) - max_dispclk_mhz =3D clk_table->entries[i].dispclk_mhz; - if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) - max_dppclk_mhz =3D clk_table->entries[i].dppclk_mhz; - } + dcn3_5_ip.max_num_otg =3D + dc->res_pool->res_cap->num_timing_generator; + dcn3_5_ip.max_num_dpp =3D dc->res_pool->pipe_count; + dcn3_5_soc.num_chans =3D bw_params->num_channels; + + ASSERT(clk_table->num_entries); + + /* Prepass to find max clocks independent of voltage level. */ + for (i =3D 0; i < clk_table->num_entries; ++i) { + if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) + max_dispclk_mhz =3D clk_table->entries[i].dispclk_mhz; + if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) + max_dppclk_mhz =3D clk_table->entries[i].dppclk_mhz; + } =20 - for (i =3D 0; i < clk_table->num_entries; i++) { - /* loop backwards*/ - for (closest_clk_lvl =3D 0, j =3D dcn3_5_soc.num_states - 1; - j >=3D 0; j--) { - if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <=3D - clk_table->entries[i].dcfclk_mhz) { - closest_clk_lvl =3D j; - break; - } - } - if (clk_table->num_entries =3D=3D 1) { - /*smu gives one DPM level, let's take the highest one*/ - closest_clk_lvl =3D dcn3_5_soc.num_states - 1; + for (i =3D 0; i < clk_table->num_entries; i++) { + /* loop backwards*/ + for (closest_clk_lvl =3D 0, j =3D dcn3_5_soc.num_states - 1; + j >=3D 0; j--) { + if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <=3D + clk_table->entries[i].dcfclk_mhz) { + closest_clk_lvl =3D j; + break; } + } + if (clk_table->num_entries =3D=3D 1) { + /*smu gives one DPM level, let's take the highest one*/ + closest_clk_lvl =3D dcn3_5_soc.num_states - 1; + } =20 - clock_limits[i].state =3D i; - - /* Clocks dependent on voltage level. */ - clock_limits[i].dcfclk_mhz =3D clk_table->entries[i].dcfclk_mhz; - if (clk_table->num_entries =3D=3D 1 && - clock_limits[i].dcfclk_mhz < - dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { - /*SMU fix not released yet*/ - clock_limits[i].dcfclk_mhz =3D - dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; - } + clock_limits[i].state =3D i; =20 - clock_limits[i].fabricclk_mhz =3D - clk_table->entries[i].fclk_mhz; - clock_limits[i].socclk_mhz =3D - clk_table->entries[i].socclk_mhz; - - if (clk_table->entries[i].memclk_mhz && - clk_table->entries[i].wck_ratio) - clock_limits[i].dram_speed_mts =3D - clk_table->entries[i].memclk_mhz * 2 * - clk_table->entries[i].wck_ratio; - - /* Clocks independent of voltage level. */ - clock_limits[i].dispclk_mhz =3D max_dispclk_mhz ? - max_dispclk_mhz : - dcn3_5_soc.clock_limits[closest_clk_lvl].dispclk_mhz; - - clock_limits[i].dppclk_mhz =3D max_dppclk_mhz ? - max_dppclk_mhz : - dcn3_5_soc.clock_limits[closest_clk_lvl].dppclk_mhz; - - clock_limits[i].dram_bw_per_chan_gbps =3D - dcn3_5_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; - clock_limits[i].dscclk_mhz =3D - dcn3_5_soc.clock_limits[closest_clk_lvl].dscclk_mhz; - clock_limits[i].dtbclk_mhz =3D - dcn3_5_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; - clock_limits[i].phyclk_d18_mhz =3D - dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; - clock_limits[i].phyclk_mhz =3D - dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_mhz; + /* Clocks dependent on voltage level. */ + clock_limits[i].dcfclk_mhz =3D clk_table->entries[i].dcfclk_mhz; + if (clk_table->num_entries =3D=3D 1 && + clock_limits[i].dcfclk_mhz < + dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { + /*SMU fix not released yet*/ + clock_limits[i].dcfclk_mhz =3D + dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; } =20 - memcpy(dcn3_5_soc.clock_limits, clock_limits, - sizeof(dcn3_5_soc.clock_limits)); + clock_limits[i].fabricclk_mhz =3D + clk_table->entries[i].fclk_mhz; + clock_limits[i].socclk_mhz =3D + clk_table->entries[i].socclk_mhz; + + if (clk_table->entries[i].memclk_mhz && + clk_table->entries[i].wck_ratio) + clock_limits[i].dram_speed_mts =3D + clk_table->entries[i].memclk_mhz * 2 * + clk_table->entries[i].wck_ratio; + + /* Clocks independent of voltage level. */ + clock_limits[i].dispclk_mhz =3D max_dispclk_mhz ? + max_dispclk_mhz : + dcn3_5_soc.clock_limits[closest_clk_lvl].dispclk_mhz; + + clock_limits[i].dppclk_mhz =3D max_dppclk_mhz ? + max_dppclk_mhz : + dcn3_5_soc.clock_limits[closest_clk_lvl].dppclk_mhz; + + clock_limits[i].dram_bw_per_chan_gbps =3D + dcn3_5_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; + clock_limits[i].dscclk_mhz =3D + dcn3_5_soc.clock_limits[closest_clk_lvl].dscclk_mhz; + clock_limits[i].dtbclk_mhz =3D + dcn3_5_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; + clock_limits[i].phyclk_d18_mhz =3D + dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; + clock_limits[i].phyclk_mhz =3D + dcn3_5_soc.clock_limits[closest_clk_lvl].phyclk_mhz; + } + + memcpy(dcn3_5_soc.clock_limits, clock_limits, + sizeof(dcn3_5_soc.clock_limits)); =20 - if (clk_table->num_entries) - dcn3_5_soc.num_states =3D clk_table->num_entries; + if (clk_table->num_entries) + dcn3_5_soc.num_states =3D clk_table->num_entries; =20 if (max_dispclk_mhz) { dcn3_5_soc.dispclk_dppclk_vco_speed_mhz =3D max_dispclk_mhz * 2; --=20 2.20.1.7.g153144c