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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF0001A104.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.14 via Frontend Transport; Wed, 27 Sep 2023 15:46:55 +0000 Received: from rric.localdomain (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 27 Sep 2023 10:46:52 -0500 From: Robert Richter To: Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , Dan Williams , "Davidlohr Bueso" , Jonathan Cameron , Dave Jiang CC: , , Bjorn Helgaas , Terry Bowman , Robert Richter Subject: [PATCH v11 14/20] cxl/pci: Map RCH downstream AER registers for logging protocol errors Date: Wed, 27 Sep 2023 17:43:33 +0200 Message-ID: <20230927154339.1600738-15-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230927154339.1600738-1-rrichter@amd.com> References: <20230927154339.1600738-1-rrichter@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A104:EE_|DS0PR12MB7630:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a2f7cd2-7fc3-4fea-5c28-08dbbf70f9ef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Sep 2023 15:46:55.2731 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0a2f7cd2-7fc3-4fea-5c28-08dbbf70f9ef X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7630 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Terry Bowman The restricted CXL host (RCH) error handler will log protocol errors using AER and RAS status registers. The AER and RAS registers need to be virtually memory mapped before enabling interrupts. Create the initializer function devm_cxl_setup_parent_dport() for this when the endpoint is connected with the dport. The initialization sets up the RCH RAS and AER mappings. Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to the RCH downstream port's AER and RAS registers. Co-developed-by: Robert Richter Signed-off-by: Terry Bowman Signed-off-by: Robert Richter Reviewed-by: Jonathan Cameron --- drivers/cxl/core/pci.c | 36 ++++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 10 ++++++++++ 2 files changed, 46 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 2b8883288539..2af7ad77b273 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -730,6 +731,38 @@ static bool cxl_handle_endpoint_ras(struct cxl_dev_sta= te *cxlds) =20 #ifdef CONFIG_PCIEAER_CXL =20 +static void cxl_dport_map_rch_aer(struct cxl_dport *dport) +{ + struct cxl_rcrb_info *ri =3D &dport->rcrb; + void __iomem *dport_aer =3D NULL; + resource_size_t aer_phys; + struct device *host; + + if (dport->rch && ri->aer_cap) { + host =3D dport->reg_map.host; + aer_phys =3D ri->aer_cap + ri->base; + dport_aer =3D devm_cxl_iomap_block(host, aer_phys, + sizeof(struct aer_capability_regs)); + } + + dport->regs.dport_aer =3D dport_aer; +} + +static void cxl_dport_map_regs(struct cxl_dport *dport) +{ + struct cxl_register_map *map =3D &dport->reg_map; + struct device *dev =3D dport->dport_dev; + + if (!map->component_map.ras.valid) + dev_dbg(dev, "RAS registers not found\n"); + else if (cxl_map_component_regs(map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(dev, "Failed to map RAS capability.\n"); + + if (dport->rch) + cxl_dport_map_rch_aer(dport); +} + void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dp= ort) { struct device *dport_dev =3D dport->dport_dev; @@ -738,6 +771,9 @@ void devm_cxl_setup_parent_dport(struct device *host, s= truct cxl_dport *dport) host_bridge =3D to_pci_host_bridge(dport_dev); if (host_bridge->native_cxl_error) dport->rcrb.aer_cap =3D cxl_rcrb_to_aer(dport_dev, dport->rcrb.base); + + dport->reg_map.host =3D host; + cxl_dport_map_regs(dport); } EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL); =20 diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index cfa2f6bede41..7c2c195592d6 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -221,6 +221,14 @@ struct cxl_regs { struct_group_tagged(cxl_pmu_regs, pmu_regs, void __iomem *pmu; ); + + /* + * RCH downstream port specific RAS register + * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB + */ + struct_group_tagged(cxl_rch_regs, rch_regs, + void __iomem *dport_aer; + ); }; =20 struct cxl_reg_map { @@ -623,6 +631,7 @@ struct cxl_rcrb_info { * @rcrb: Data about the Root Complex Register Block layout * @rch: Indicate whether this dport was enumerated in RCH or VH mode * @port: reference to cxl_port that contains this downstream port + * @regs: Dport parsed register blocks */ struct cxl_dport { struct device *dport_dev; @@ -631,6 +640,7 @@ struct cxl_dport { struct cxl_rcrb_info rcrb; bool rch; struct cxl_port *port; + struct cxl_regs regs; }; =20 /** --=20 2.30.2