From nobody Fri Feb 13 10:59:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1982E80A81 for ; Wed, 27 Sep 2023 04:36:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229561AbjI0Eg5 (ORCPT ); Wed, 27 Sep 2023 00:36:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229705AbjI0Efo (ORCPT ); Wed, 27 Sep 2023 00:35:44 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE3137EC6; Tue, 26 Sep 2023 19:37:48 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 38R2beGF128592; Tue, 26 Sep 2023 21:37:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1695782260; bh=MD8cXZlJBb4QIOG4MyaF1RucgKVjkTnOrvtM6DvwSkc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SuSzg6XFPmyvKADtBjq/SoqZFr/j+LWflGEdyuRoQ6nBjN7HD0mAWKGVE24LyI9IT +mRrjjoofr9Kma46jUfOUOz92K2KfgPqE26A5ZVrsok/m9jJCM3Nytk38vlVDbupoI OoOq45TwIbl54QMzaYlA6Vt6yKHSMSCe98r63mGA= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 38R2beXg026236 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 26 Sep 2023 21:37:40 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 26 Sep 2023 21:37:40 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 26 Sep 2023 21:37:40 -0500 Received: from localhost.localdomain (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 38R2bL7W013228; Tue, 26 Sep 2023 21:37:36 -0500 From: Keerthy To: , , , , , CC: , , , , Subject: [PATCH v6 4/7] arm64: dts: ti: k3-j784s4-main: Add the main domain watchdog instances Date: Wed, 27 Sep 2023 08:03:54 +0530 Message-ID: <20230927023357.9883-5-j-keerthy@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230927023357.9883-1-j-keerthy@ti.com> References: <20230927023357.9883-1-j-keerthy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are totally 19 instances of watchdog module. One each for the 8 A72 cores, one each for the 4 C7x cores, 1 for the GPU, 1 each for the 6 R5F cores in the main domain. The non-A72 instances are coupled with the R5Fs, C7x & GPU instances. Disabling them as they are not used by Linux & will be used by their respective firmware. Signed-off-by: Keerthy --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 187 +++++++++++++++++++++ 1 file changed, 187 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 26dc3776f911..852f4ef64fd8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1576,4 +1576,191 @@ <695>; bootph-pre-ram; }; + + watchdog0: watchdog@2200000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2200000 0x00 0x100>; + clocks =3D <&k3_clks 348 1>; + power-domains =3D <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 348 0>; + assigned-clock-parents =3D <&k3_clks 348 4>; + }; + + watchdog1: watchdog@2210000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2210000 0x00 0x100>; + clocks =3D <&k3_clks 349 1>; + power-domains =3D <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 349 0>; + assigned-clock-parents =3D <&k3_clks 349 4>; + }; + + watchdog2: watchdog@2220000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2220000 0x00 0x100>; + clocks =3D <&k3_clks 350 1>; + power-domains =3D <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 350 0>; + assigned-clock-parents =3D <&k3_clks 350 4>; + }; + + watchdog3: watchdog@2230000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2230000 0x00 0x100>; + clocks =3D <&k3_clks 351 1>; + power-domains =3D <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 351 0>; + assigned-clock-parents =3D <&k3_clks 351 4>; + }; + + watchdog4: watchdog@2240000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2240000 0x00 0x100>; + clocks =3D <&k3_clks 352 1>; + power-domains =3D <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 352 0>; + assigned-clock-parents =3D <&k3_clks 352 4>; + }; + + watchdog5: watchdog@2250000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2250000 0x00 0x100>; + clocks =3D <&k3_clks 353 1>; + power-domains =3D <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 353 0>; + assigned-clock-parents =3D <&k3_clks 353 4>; + }; + + watchdog6: watchdog@2260000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2260000 0x00 0x100>; + clocks =3D <&k3_clks 354 1>; + power-domains =3D <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 354 0>; + assigned-clock-parents =3D <&k3_clks 354 4>; + }; + + watchdog7: watchdog@2270000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2270000 0x00 0x100>; + clocks =3D <&k3_clks 355 1>; + power-domains =3D <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 355 0>; + assigned-clock-parents =3D <&k3_clks 355 4>; + }; + + /* + * The following RTI instances are coupled with MCU R5Fs, c7x and + * GPU so keeping them disabled as these will be used by their + * respective firmware + */ + watchdog16: watchdog@2300000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2300000 0x00 0x100>; + clocks =3D <&k3_clks 356 1>; + power-domains =3D <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 356 0>; + assigned-clock-parents =3D <&k3_clks 356 4>; + status =3D "disabled"; + }; + + watchdog17: watchdog@2310000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2310000 0x00 0x100>; + clocks =3D <&k3_clks 357 1>; + power-domains =3D <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 357 0>; + assigned-clock-parents =3D <&k3_clks 357 4>; + status =3D "disabled"; + }; + + watchdog18: watchdog@2320000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2320000 0x00 0x100>; + clocks =3D <&k3_clks 358 1>; + power-domains =3D <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 358 0>; + assigned-clock-parents =3D <&k3_clks 358 4>; + status =3D "disabled"; + }; + + watchdog19: watchdog@2330000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2330000 0x00 0x100>; + clocks =3D <&k3_clks 359 1>; + power-domains =3D <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 359 0>; + assigned-clock-parents =3D <&k3_clks 359 4>; + status =3D "disabled"; + }; + + watchdog15: watchdog@22f0000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x22f0000 0x00 0x100>; + clocks =3D <&k3_clks 360 1>; + power-domains =3D <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 360 0>; + assigned-clock-parents =3D <&k3_clks 360 4>; + status =3D "disabled"; + }; + + watchdog28: watchdog@23c0000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x23c0000 0x00 0x100>; + clocks =3D <&k3_clks 361 1>; + power-domains =3D <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 361 0>; + assigned-clock-parents =3D <&k3_clks 361 4>; + status =3D "disabled"; + }; + + watchdog29: watchdog@23d0000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x23d0000 0x00 0x100>; + clocks =3D <&k3_clks 362 1>; + power-domains =3D <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 362 0>; + assigned-clock-parents =3D <&k3_clks 362 4>; + status =3D "disabled"; + }; + + watchdog30: watchdog@23e0000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x23e0000 0x00 0x100>; + clocks =3D <&k3_clks 363 1>; + power-domains =3D <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 363 0>; + assigned-clock-parents =3D <&k3_clks 363 4>; + status =3D "disabled"; + }; + + watchdog31: watchdog@23f0000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x23f0000 0x00 0x100>; + clocks =3D <&k3_clks 364 1>; + power-domains =3D <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 364 0>; + assigned-clock-parents =3D <&k3_clks 364 4>; + status =3D "disabled"; + }; + + watchdog32: watchdog@2540000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2540000 0x00 0x100>; + clocks =3D <&k3_clks 365 1>; + power-domains =3D <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 365 0>; + assigned-clock-parents =3D <&k3_clks 366 4>; + status =3D "disabled"; + }; + + watchdog33: watchdog@2550000 { + compatible =3D "ti,j7-rti-wdt"; + reg =3D <0x00 0x2550000 0x00 0x100>; + clocks =3D <&k3_clks 366 1>; + power-domains =3D <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks =3D <&k3_clks 366 0>; + assigned-clock-parents =3D <&k3_clks 366 4>; + status =3D "disabled"; + }; }; --=20 2.17.1