From nobody Fri Feb 13 09:49:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7998E7E649 for ; Tue, 26 Sep 2023 15:04:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235007AbjIZPEG (ORCPT ); Tue, 26 Sep 2023 11:04:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232070AbjIZPEB (ORCPT ); Tue, 26 Sep 2023 11:04:01 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38B7C10E for ; Tue, 26 Sep 2023 08:03:54 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3200b181b67so1192065f8f.0 for ; Tue, 26 Sep 2023 08:03:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1695740632; x=1696345432; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XQDAxN5g1vMcAJWLoIEgGtbs3vH3NsC3JS3eiLLd1tc=; b=RSu2dlzSLD/MQbHRXs/I7tNPqUsZIF4qAWabMji12OIWw1ls8Th9dnbWmSBGZrj5Bm /IB+CXnhMk6tBmfylXPjM5MDd77T1fnYghsehbVWjN/iioPqMcIcup7OYXr/l4WXpAM0 I7A9P3ZR1Fe1bsv33FnFXHXIcBCfIIo6s4sr2CIm+mg3pOeaKSoVf51gPsRNk7GFlDC3 IN47s+g5kNiZMvK0qJkAzTFHty/i2HfBtsZlJbezzHqV5tFHjN7dqvAEue5ti5dggiuW MKzVB20JM+aE54eP4bHOeuWwKvHfmQPQ15+OilLLABdvS6ioqC7G5d/5pxYUaOx928No ha0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695740632; x=1696345432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XQDAxN5g1vMcAJWLoIEgGtbs3vH3NsC3JS3eiLLd1tc=; b=W+1+9vGbHgCO7Na/mf/sdA90dvDkE4Y/uciqMvcy6ig1Ss7dz4mmJ/As6KdNDIawe9 XaamRdlpluFqezBCOATZyENw2tm33eLqMrq3krahrbuuQhKbI617KmOVvBcTjZdvV5r9 5GclXlE/VaIlKfJCWUf1PB6CzoVfdgevlqM509j59FK5VYlEnr93+bhiahDqBStCcDZu jZ/oN2zFkt+VtoNToroxmWhgj4IDgki4dtVZjqUHYMT38lffktyjREexobFRp+C1yG2p dCaK0LwzSSFwNk+CxiJeLld8Ma/qszv2/GBzZDUPnIeUqUSckWtBbAVE3gBUosXJhNHZ QZlQ== X-Gm-Message-State: AOJu0Yy1IFYOq/hZpJcMK9VNCAlO6HcnbGThhj7g0EcD05lbACSWub2e T/XCenNMObDZlkL4vpk4yEf+ew== X-Google-Smtp-Source: AGHT+IH9PRCXtJEPxMLZQ5j5Z5+cpNGCxbKpqseY8qd18eONWrD2LaNnzT+g47bz5kOVc9HeGDcZ5g== X-Received: by 2002:adf:a456:0:b0:323:2df9:618f with SMTP id e22-20020adfa456000000b003232df9618fmr3634053wra.0.1695740632703; Tue, 26 Sep 2023 08:03:52 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:2b3d:6c70:9dbf:5ede]) by smtp.gmail.com with ESMTPSA id x11-20020a5d650b000000b00318147fd2d3sm14926060wru.41.2023.09.26.08.03.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 08:03:52 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Atish Patra , Andrew Jones , Evan Green , =?UTF-8?q?Bj=C3=B6rn=20Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski Subject: [PATCH 1/7] riscv: remove unused functions in traps_misaligned.c Date: Tue, 26 Sep 2023 17:03:10 +0200 Message-Id: <20230926150316.1129648-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com> References: <20230926150316.1129648-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Replace macros by the only two function calls that are done from this file, store_u8() and load_u8(). Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/traps_misaligned.c | 46 +++++----------------------- 1 file changed, 7 insertions(+), 39 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 378f5b151443..e7bfb33089c1 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -151,51 +151,19 @@ #define PRECISION_S 0 #define PRECISION_D 1 =20 -#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \ -static inline type load_##type(const type *addr) \ -{ \ - type val; \ - asm (#insn " %0, %1" \ - : "=3D&r" (val) : "m" (*addr)); \ - return val; \ -} +static inline u8 load_u8(const u8 *addr) +{ + u8 val; =20 -#define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn) \ -static inline void store_##type(type *addr, type val) \ -{ \ - asm volatile (#insn " %0, %1\n" \ - : : "r" (val), "m" (*addr)); \ -} + asm volatile("lbu %0, %1" : "=3D&r" (val) : "m" (*addr)); =20 -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u8, sb) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u16, sh) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u32, sw) -#if defined(CONFIG_64BIT) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64, sd) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld) -#else -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw) - -static inline u64 load_u64(const u64 *addr) -{ - return load_u32((u32 *)addr) - + ((u64)load_u32((u32 *)addr + 1) << 32); + return val; } =20 -static inline void store_u64(u64 *addr, u64 val) +static inline void store_u8(u8 *addr, u8 val) { - store_u32((u32 *)addr, val); - store_u32((u32 *)addr + 1, val >> 32); + asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr)); } -#endif =20 static inline ulong get_insn(ulong mepc) { --=20 2.40.1 From nobody Fri Feb 13 09:49:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 982E6E7E649 for ; Tue, 26 Sep 2023 15:04:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235035AbjIZPEK (ORCPT ); Tue, 26 Sep 2023 11:04:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234878AbjIZPED (ORCPT ); Tue, 26 Sep 2023 11:04:03 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 730BC11F for ; Tue, 26 Sep 2023 08:03:55 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4047ef37f55so25470145e9.1 for ; Tue, 26 Sep 2023 08:03:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1695740634; x=1696345434; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BMCaPvwZIrQsZFzVwV8aZpdb+qmaO/RzFW3CFL/diT8=; b=KHJP7mQ8XrDCX9sn41SFqFoOTAIO3VMIUUF2mdaTtrstH26iw3Zv5Mi5/ryaL/MMUi t8TurkiR9IlnAcXAwOPfPer8KJnq07fwp71EFkAq+sOsfK8ySPjqB/VdAY7wQc/SaVOo lBKnFgfySxMzNItCOCqAhIO1yuV9d1JP1FriOC5CL5SxorVkIi648xspjqSqOTzLZKPn 1vrjTpVct8L6YjVOPOgOyxl8Dn1OZt6ZKqFHo22DV7lNwcNJTccSLIgbSHJ5aU39/ZaD iV1mWK5hD4a6G0PFs6cU2br4Y3hkpy0Hr63rZUfL/p4nLpDF/P8W7ZqR5CD3PFaxtNOk cXng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695740634; x=1696345434; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BMCaPvwZIrQsZFzVwV8aZpdb+qmaO/RzFW3CFL/diT8=; b=aYHEUZNEXU1ixkn0yVTr4AhtFildCTZvx89+VOQhnJfQEAqe50ylOdsM3d+0BtHxip 4prvMtcWpxnIe628ZyzSWLJzDEGjG1XHtKtf5QR69qsQUQ7/J+G1osgJ9RxXzONGDJhO kppwBMIQ+OVvxcfoTOhNzliaSHzfZMJ+7nRI7Jvazg5KPoCD60lBo/TdJL2zKCW34zs5 70MrzjdntLuCfszWt1oQ73AytiAezY7Tn5q6RvQA+qmag/+rLd1/ft4t2yKgt6TV532i XTmGp2WNqgOKJYsGgETp6i8FU6lOQ16/mYv160m1P07iU1Qndtw46CNwBpO8nFPs3OjK EWxw== X-Gm-Message-State: AOJu0YxhBXivupayO0dnmmCebnV9tpSzj5wl9EJ9pti+4obTSBscWFDC UE4/pN/lfsORV2Q4PEXihb1LGQ== X-Google-Smtp-Source: AGHT+IHgZfAP6fasdZg9oDt8icOVA1g4Bij886aSrDFQJWBHit0z1Qc3vpUlrZpy4M6ivgyVAPjxHA== X-Received: by 2002:a5d:584a:0:b0:323:2b68:e0e0 with SMTP id i10-20020a5d584a000000b003232b68e0e0mr5172766wrf.0.1695740633754; Tue, 26 Sep 2023 08:03:53 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:2b3d:6c70:9dbf:5ede]) by smtp.gmail.com with ESMTPSA id x11-20020a5d650b000000b00318147fd2d3sm14926060wru.41.2023.09.26.08.03.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 08:03:53 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Atish Patra , Andrew Jones , Evan Green , =?UTF-8?q?Bj=C3=B6rn=20Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski Subject: [PATCH 2/7] riscv: add support for misaligned handling in S-mode Date: Tue, 26 Sep 2023 17:03:11 +0200 Message-Id: <20230926150316.1129648-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com> References: <20230926150316.1129648-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Misalignment handling is only supported for M-mode and uses direct accesses to user memory. In S-mode, when handlnig usermode fault, this requires to use the get_user()/put_user() accessors. Implement load_u8(), store_u8() and get_insn() using these accessors. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/entry-common.h | 3 + arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/traps.c | 9 -- arch/riscv/kernel/traps_misaligned.c | 119 +++++++++++++++++++++++--- 4 files changed, 110 insertions(+), 23 deletions(-) diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm= /entry-common.h index 6e4dee49d84b..58e9e2976e1b 100644 --- a/arch/riscv/include/asm/entry-common.h +++ b/arch/riscv/include/asm/entry-common.h @@ -8,4 +8,7 @@ void handle_page_fault(struct pt_regs *regs); void handle_break(struct pt_regs *regs); =20 +int handle_misaligned_load(struct pt_regs *regs); +int handle_misaligned_store(struct pt_regs *regs); + #endif /* _ASM_RISCV_ENTRY_COMMON_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 95cf25d48405..ccdfd029c511 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -56,10 +56,10 @@ obj-y +=3D riscv_ksyms.o obj-y +=3D stacktrace.o obj-y +=3D cacheinfo.o obj-y +=3D patch.o +obj-y +=3D traps_misaligned.o obj-y +=3D probes/ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ =20 -obj-$(CONFIG_RISCV_M_MODE) +=3D traps_misaligned.o obj-$(CONFIG_FPU) +=3D fpu.o obj-$(CONFIG_RISCV_ISA_V) +=3D vector.o obj-$(CONFIG_SMP) +=3D smpboot.o diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 19807c4d3805..d69779e4b967 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -179,14 +179,6 @@ asmlinkage __visible __trap_section void do_trap_insn_= illegal(struct pt_regs *re =20 DO_ERROR_INFO(do_trap_load_fault, SIGSEGV, SEGV_ACCERR, "load access fault"); -#ifndef CONFIG_RISCV_M_MODE -DO_ERROR_INFO(do_trap_load_misaligned, - SIGBUS, BUS_ADRALN, "Oops - load address misaligned"); -DO_ERROR_INFO(do_trap_store_misaligned, - SIGBUS, BUS_ADRALN, "Oops - store (or AMO) address misaligned"); -#else -int handle_misaligned_load(struct pt_regs *regs); -int handle_misaligned_store(struct pt_regs *regs); =20 asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt= _regs *regs) { @@ -229,7 +221,6 @@ asmlinkage __visible __trap_section void do_trap_store_= misaligned(struct pt_regs irqentry_nmi_exit(regs, state); } } -#endif DO_ERROR_INFO(do_trap_store_fault, SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault"); DO_ERROR_INFO(do_trap_ecall_s, diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index e7bfb33089c1..9daed7d756ae 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 #define INSN_MATCH_LB 0x3 #define INSN_MASK_LB 0x707f @@ -151,21 +152,25 @@ #define PRECISION_S 0 #define PRECISION_D 1 =20 -static inline u8 load_u8(const u8 *addr) +#ifdef CONFIG_RISCV_M_MODE +static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val) { u8 val; =20 asm volatile("lbu %0, %1" : "=3D&r" (val) : "m" (*addr)); + *r_val =3D val; =20 - return val; + return 0; } =20 -static inline void store_u8(u8 *addr, u8 val) +static inline int store_u8(struct pt_regs *regs, u8 *addr, u8 val) { asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr)); + + return 0; } =20 -static inline ulong get_insn(ulong mepc) +static inline int get_insn(struct pt_regs *regs, ulong mepc, ulong *r_insn) { register ulong __mepc asm ("a2") =3D mepc; ulong val, rvc_mask =3D 3, tmp; @@ -194,9 +199,87 @@ static inline ulong get_insn(ulong mepc) : [addr] "r" (__mepc), [rvc_mask] "r" (rvc_mask), [xlen_minus_16] "i" (XLEN_MINUS_16)); =20 - return val; + *r_insn =3D val; + + return 0; +} +#else +static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val) +{ + if (user_mode(regs)) { + return __get_user(*r_val, addr); + } else { + *r_val =3D *addr; + return 0; + } } =20 +static inline int store_u8(struct pt_regs *regs, u8 *addr, u8 val) +{ + if (user_mode(regs)) { + return __put_user(val, addr); + } else { + *addr =3D val; + return 0; + } +} + +#define __read_insn(regs, insn, insn_addr) \ +({ \ + int __ret; \ + \ + if (user_mode(regs)) { \ + __ret =3D __get_user(insn, insn_addr); \ + } else { \ + insn =3D *insn_addr; \ + __ret =3D 0; \ + } \ + \ + __ret; \ +}) + +static inline int get_insn(struct pt_regs *regs, ulong epc, ulong *r_insn) +{ + ulong insn =3D 0; + + if (epc & 0x2) { + ulong tmp =3D 0; + u16 __user *insn_addr =3D (u16 __user *)epc; + + if (__read_insn(regs, insn, insn_addr)) + return -EFAULT; + /* __get_user() uses regular "lw" which sign extend the loaded + * value make sure to clear higher order bits in case we "or" it + * below with the upper 16 bits half. + */ + insn &=3D GENMASK(15, 0); + if ((insn & __INSN_LENGTH_MASK) !=3D __INSN_LENGTH_32) { + *r_insn =3D insn; + return 0; + } + insn_addr++; + if (__read_insn(regs, tmp, insn_addr)) + return -EFAULT; + *r_insn =3D (tmp << 16) | insn; + + return 0; + } else { + u32 __user *insn_addr =3D (u32 __user *)epc; + + if (__read_insn(regs, insn, insn_addr)) + return -EFAULT; + if ((insn & __INSN_LENGTH_MASK) =3D=3D __INSN_LENGTH_32) { + *r_insn =3D insn; + return 0; + } + insn &=3D GENMASK(15, 0); + *r_insn =3D insn; + + return 0; + } +} +#endif + union reg_data { u8 data_bytes[8]; ulong data_ulong; @@ -207,10 +290,13 @@ int handle_misaligned_load(struct pt_regs *regs) { union reg_data val; unsigned long epc =3D regs->epc; - unsigned long insn =3D get_insn(epc); - unsigned long addr =3D csr_read(mtval); + unsigned long insn; + unsigned long addr =3D regs->badaddr; int i, fp =3D 0, shift =3D 0, len =3D 0; =20 + if (get_insn(regs, epc, &insn)) + return -1; + regs->epc =3D 0; =20 if ((insn & INSN_MASK_LW) =3D=3D INSN_MATCH_LW) { @@ -274,8 +360,10 @@ int handle_misaligned_load(struct pt_regs *regs) } =20 val.data_u64 =3D 0; - for (i =3D 0; i < len; i++) - val.data_bytes[i] =3D load_u8((void *)(addr + i)); + for (i =3D 0; i < len; i++) { + if (load_u8(regs, (void *)(addr + i), &val.data_bytes[i])) + return -1; + } =20 if (fp) return -1; @@ -290,10 +378,13 @@ int handle_misaligned_store(struct pt_regs *regs) { union reg_data val; unsigned long epc =3D regs->epc; - unsigned long insn =3D get_insn(epc); - unsigned long addr =3D csr_read(mtval); + unsigned long insn; + unsigned long addr =3D regs->badaddr; int i, len =3D 0; =20 + if (get_insn(regs, epc, &insn)) + return -1; + regs->epc =3D 0; =20 val.data_ulong =3D GET_RS2(insn, regs); @@ -327,8 +418,10 @@ int handle_misaligned_store(struct pt_regs *regs) return -1; } =20 - for (i =3D 0; i < len; i++) - store_u8((void *)(addr + i), val.data_bytes[i]); + for (i =3D 0; i < len; i++) { + if (store_u8(regs, (void *)(addr + i), val.data_bytes[i])) + return -1; + } =20 regs->epc =3D epc + INSN_LEN(insn); =20 --=20 2.40.1 From nobody Fri Feb 13 09:49:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9241BE7E648 for ; Tue, 26 Sep 2023 15:04:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233699AbjIZPEI (ORCPT ); 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([2a01:e0a:999:a3a0:2b3d:6c70:9dbf:5ede]) by smtp.gmail.com with ESMTPSA id x11-20020a5d650b000000b00318147fd2d3sm14926060wru.41.2023.09.26.08.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 08:03:54 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Atish Patra , Andrew Jones , Evan Green , =?UTF-8?q?Bj=C3=B6rn=20Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski Subject: [PATCH 3/7] riscv: report perf event for misaligned fault Date: Tue, 26 Sep 2023 17:03:12 +0200 Message-Id: <20230926150316.1129648-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com> References: <20230926150316.1129648-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add missing calls to account for misaligned fault event using perf_sw_event(). Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/traps_misaligned.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 9daed7d756ae..804f6c5e0e44 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include =20 @@ -294,6 +295,8 @@ int handle_misaligned_load(struct pt_regs *regs) unsigned long addr =3D regs->badaddr; int i, fp =3D 0, shift =3D 0, len =3D 0; =20 + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (get_insn(regs, epc, &insn)) return -1; =20 @@ -382,6 +385,8 @@ int handle_misaligned_store(struct pt_regs *regs) unsigned long addr =3D regs->badaddr; int i, len =3D 0; =20 + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (get_insn(regs, epc, &insn)) return -1; =20 --=20 2.40.1 From nobody Fri Feb 13 09:49:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D66D7E7E64B for ; Tue, 26 Sep 2023 15:04:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234984AbjIZPEP (ORCPT ); Tue, 26 Sep 2023 11:04:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234991AbjIZPEE (ORCPT ); Tue, 26 Sep 2023 11:04:04 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6022210E for ; Tue, 26 Sep 2023 08:03:57 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-32163c3ece5so1120017f8f.1 for ; Tue, 26 Sep 2023 08:03:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1695740636; x=1696345436; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/uuvfJ5AANk2b1H7qXwiqMjtZ5fx5LwQZGgrS2bH6zQ=; b=IvpG+fJbcpybBzYIchFjWpENMuIq3Vx6KOoTvLMPxnr5iL1A7Zn6JQI47IWz0KtEjF rpow7Mz0NFNh95y3GcAWUoaseXtO6RoF2KGcMxppbx40JcOwrdWCI4DKoC7BEP3ETuPp rtatnnjn4BNBN5xiematBqXKl3f6NXzaSX1FfTQYaTIoRshvB5pIxfNxSNQm0r+T0OVs 6RrALLyHrQgHGLkXE0qRsPsahTIHvrnu1pubMDl/LLgs73EANRrj6rAv+eW2N94hbu6a 4DBr2RppX45l02lOoDfzkmU/g7FMbTAm6oPtEg7zziACdVR9OGIl+Gg8gM47E4DCj/YF f5VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695740636; x=1696345436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/uuvfJ5AANk2b1H7qXwiqMjtZ5fx5LwQZGgrS2bH6zQ=; b=AkREh6fLpIJJhG8sh6iY2AgaN1f9GDi/MisL9iIjuQL/NPjs7dQIlJREWJfftJCoNk llEexLa+B4+eZsVKuLneZ47K6y/aHeMegNeMEqA65q2lB/MA4j9tukNWKR0cuk4pvucO 3V+CwidZW1w8xMuwydc0F2FTb++dRJhPLuAnLSlqtyb14tjOlTCWIVnCUBdU7QmoFp4W +VSTnSwYsY5L3OT6jlQ/W2RxpwaE/P+ukwowDBtumDdLizIDrtiaEA3R8Tln7a0kMSlU 0Na3gNXj64KbhEoYXPL/rwhXeQlOWs64LfKlUobVX7Xg5TTamU1A8SVAdoq8BeaZnFfG kEcQ== X-Gm-Message-State: AOJu0YyA1yKO1mX5e4aT1JvLF8xwojZhNxtRnag/80fCCNtV3wKLBPhM EQCdk8yyF0e8e5ww6cpHwvw4Fg== X-Google-Smtp-Source: AGHT+IE8kK7m+adK60EJSFNwZFOqJSMd+4wvMQfHEfjOwfK+qxITAch3QRj6sfjlQtjyWNy3/S6QzA== X-Received: by 2002:adf:ed84:0:b0:322:c494:d481 with SMTP id c4-20020adfed84000000b00322c494d481mr9917893wro.0.1695740635757; Tue, 26 Sep 2023 08:03:55 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:2b3d:6c70:9dbf:5ede]) by smtp.gmail.com with ESMTPSA id x11-20020a5d650b000000b00318147fd2d3sm14926060wru.41.2023.09.26.08.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 08:03:55 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Atish Patra , Andrew Jones , Evan Green , =?UTF-8?q?Bj=C3=B6rn=20Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski Subject: [PATCH 4/7] riscv: add floating point insn support to misaligned access emulation Date: Tue, 26 Sep 2023 17:03:13 +0200 Message-Id: <20230926150316.1129648-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com> References: <20230926150316.1129648-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This support is partially based of openSBI misaligned emulation floating point instruction support. It provides support for the existing floating point instructions (both for 32/64 bits as well as compressed ones). Since floating point registers are not part of the pt_regs struct, we need to modify them directly using some assembly. We also dirty the pt_regs status in case we modify them to be sure context switch will save FP state. With this support, Linux is on par with openSBI support. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/fpu.S | 117 +++++++++++++++++++++ arch/riscv/kernel/traps_misaligned.c | 152 ++++++++++++++++++++++++++- 2 files changed, 265 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/fpu.S b/arch/riscv/kernel/fpu.S index dd2205473de7..2785badb247c 100644 --- a/arch/riscv/kernel/fpu.S +++ b/arch/riscv/kernel/fpu.S @@ -104,3 +104,120 @@ ENTRY(__fstate_restore) csrc CSR_STATUS, t1 ret ENDPROC(__fstate_restore) + +#define get_f32(which) fmv.x.s a0, which; j 2f +#define put_f32(which) fmv.s.x which, a1; j 2f +#if __riscv_xlen =3D=3D 64 +# define get_f64(which) fmv.x.d a0, which; j 2f +# define put_f64(which) fmv.d.x which, a1; j 2f +#else +# define get_f64(which) fsd which, 0(a1); j 2f +# define put_f64(which) fld which, 0(a1); j 2f +#endif + +.macro fp_access_prologue + /* + * Compute jump offset to store the correct FP register since we don't + * have indirect FP register access + */ + sll t0, a0, 3 + la t2, 1f + add t0, t0, t2 + li t1, SR_FS + csrs CSR_STATUS, t1 + jr t0 +1: +.endm + +.macro fp_access_epilogue +2: + csrc CSR_STATUS, t1 + ret +.endm + +#define fp_access_body(__access_func) \ + __access_func(f0); \ + __access_func(f1); \ + __access_func(f2); \ + __access_func(f3); \ + __access_func(f4); \ + __access_func(f5); \ + __access_func(f6); \ + __access_func(f7); \ + __access_func(f8); \ + __access_func(f9); \ + __access_func(f10); \ + __access_func(f11); \ + __access_func(f12); \ + __access_func(f13); \ + __access_func(f14); \ + __access_func(f15); \ + __access_func(f16); \ + __access_func(f17); \ + __access_func(f18); \ + __access_func(f19); \ + __access_func(f20); \ + __access_func(f21); \ + __access_func(f22); \ + __access_func(f23); \ + __access_func(f24); \ + __access_func(f25); \ + __access_func(f26); \ + __access_func(f27); \ + __access_func(f28); \ + __access_func(f29); \ + __access_func(f30); \ + __access_func(f31) + + +/* + * Disable compressed instructions set to keep a constant offset between FP + * load/store/move instructions + */ +.option norvc +/* + * put_f32_reg - Set a FP register from a register containing the value + * a0 =3D FP register index to be set + * a1 =3D value to be loaded in the FP register + */ +SYM_FUNC_START(put_f32_reg) + fp_access_prologue + fp_access_body(put_f32) + fp_access_epilogue +SYM_FUNC_END(put_f32_reg) + +/* + * get_f32_reg - Get a FP register value and return it + * a0 =3D FP register index to be retrieved + */ +SYM_FUNC_START(get_f32_reg) + fp_access_prologue + fp_access_body(get_f32) + fp_access_epilogue +SYM_FUNC_END(put_f32_reg) + +/* + * put_f64_reg - Set a 64 bits FP register from a value or a pointer. + * a0 =3D FP register index to be set + * a1 =3D value/pointer to be loaded in the FP register (when xlen =3D=3D = 32 bits, we + * load the value to a pointer). + */ +SYM_FUNC_START(put_f64_reg) + fp_access_prologue + fp_access_body(put_f64) + fp_access_epilogue +SYM_FUNC_END(put_f64_reg) + +/* + * put_f64_reg - Get a 64 bits FP register value and returned it or store = it to + * a pointer. + * a0 =3D FP register index to be retrieved + * a1 =3D If xlen =3D=3D 32, pointer which should be loaded with the FP re= gister value + * or unused if xlen =3D=3D 64. In which case the FP register value is ret= urned + * through a0 + */ +SYM_FUNC_START(get_f64_reg) + fp_access_prologue + fp_access_body(get_f64) + fp_access_epilogue +SYM_FUNC_END(get_f64_reg) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 804f6c5e0e44..041fd2dbd955 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -153,6 +153,115 @@ #define PRECISION_S 0 #define PRECISION_D 1 =20 +#ifdef CONFIG_FPU + +#define FP_GET_RD(insn) (insn >> 7 & 0x1F) + +extern void put_f32_reg(unsigned long fp_reg, unsigned long value); + +static int set_f32_rd(unsigned long insn, struct pt_regs *regs, + unsigned long val) +{ + unsigned long fp_reg =3D FP_GET_RD(insn); + + put_f32_reg(fp_reg, val); + regs->status |=3D SR_FS_DIRTY; + + return 0; +} + +extern void put_f64_reg(unsigned long fp_reg, unsigned long value); + +static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) +{ + unsigned long fp_reg =3D FP_GET_RD(insn); + unsigned long value; + +#if __riscv_xlen =3D=3D 32 + value =3D (unsigned long) &val; +#else + value =3D val; +#endif + put_f64_reg(fp_reg, value); + regs->status |=3D SR_FS_DIRTY; + + return 0; +} + +#if __riscv_xlen =3D=3D 32 +extern void get_f64_reg(unsigned long fp_reg, u64 *value); + +static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + unsigned long fp_reg =3D (insn >> fp_reg_offset) & 0x1F; + u64 val; + + get_f64_reg(fp_reg, &val); + regs->status |=3D SR_FS_DIRTY; + + return val; +} +#else + +extern unsigned long get_f64_reg(unsigned long fp_reg); + +static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + unsigned long fp_reg =3D (insn >> fp_reg_offset) & 0x1F; + unsigned long val; + + val =3D get_f64_reg(fp_reg); + regs->status |=3D SR_FS_DIRTY; + + return val; +} + +#endif + +extern unsigned long get_f32_reg(unsigned long fp_reg); + +static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + unsigned long fp_reg =3D (insn >> fp_reg_offset) & 0x1F; + unsigned long val; + + val =3D get_f32_reg(fp_reg); + regs->status |=3D SR_FS_DIRTY; + + return val; +} + +#else /* CONFIG_FPU */ +static void set_f32_rd(unsigned long insn, struct pt_regs *regs, + unsigned long val) {} + +static void set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) = {} + +static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + return 0; +} + +static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + return 0; +} + +#endif + +#define GET_F64_RS2(insn, regs) (get_f64_rs(insn, 20, regs)) +#define GET_F64_RS2C(insn, regs) (get_f64_rs(insn, 2, regs)) +#define GET_F64_RS2S(insn, regs) (get_f64_rs(RVC_RS2S(insn), 0, regs)) + +#define GET_F32_RS2(insn, regs) (get_f32_rs(insn, 20, regs)) +#define GET_F32_RS2C(insn, regs) (get_f32_rs(insn, 2, regs)) +#define GET_F32_RS2S(insn, regs) (get_f32_rs(RVC_RS2S(insn), 0, regs)) + #ifdef CONFIG_RISCV_M_MODE static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val) { @@ -362,15 +471,21 @@ int handle_misaligned_load(struct pt_regs *regs) return -1; } =20 + if (!IS_ENABLED(CONFIG_FPU) && fp) + return -EOPNOTSUPP; + val.data_u64 =3D 0; for (i =3D 0; i < len; i++) { if (load_u8(regs, (void *)(addr + i), &val.data_bytes[i])) return -1; } =20 - if (fp) - return -1; - SET_RD(insn, regs, val.data_ulong << shift >> shift); + if (!fp) + SET_RD(insn, regs, val.data_ulong << shift >> shift); + else if (len =3D=3D 8) + set_f64_rd(insn, regs, val.data_u64); + else + set_f32_rd(insn, regs, val.data_ulong); =20 regs->epc =3D epc + INSN_LEN(insn); =20 @@ -383,7 +498,7 @@ int handle_misaligned_store(struct pt_regs *regs) unsigned long epc =3D regs->epc; unsigned long insn; unsigned long addr =3D regs->badaddr; - int i, len =3D 0; + int i, len =3D 0, fp =3D 0; =20 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); =20 @@ -400,6 +515,14 @@ int handle_misaligned_store(struct pt_regs *regs) } else if ((insn & INSN_MASK_SD) =3D=3D INSN_MATCH_SD) { len =3D 8; #endif + } else if ((insn & INSN_MASK_FSD) =3D=3D INSN_MATCH_FSD) { + fp =3D 1; + len =3D 8; + val.data_u64 =3D GET_F64_RS2(insn, regs); + } else if ((insn & INSN_MASK_FSW) =3D=3D INSN_MATCH_FSW) { + fp =3D 1; + len =3D 4; + val.data_ulong =3D GET_F32_RS2(insn, regs); } else if ((insn & INSN_MASK_SH) =3D=3D INSN_MATCH_SH) { len =3D 2; #if defined(CONFIG_64BIT) @@ -418,11 +541,32 @@ int handle_misaligned_store(struct pt_regs *regs) ((insn >> SH_RD) & 0x1f)) { len =3D 4; val.data_ulong =3D GET_RS2C(insn, regs); + } else if ((insn & INSN_MASK_C_FSD) =3D=3D INSN_MATCH_C_FSD) { + fp =3D 1; + len =3D 8; + val.data_u64 =3D GET_F64_RS2S(insn, regs); + } else if ((insn & INSN_MASK_C_FSDSP) =3D=3D INSN_MATCH_C_FSDSP) { + fp =3D 1; + len =3D 8; + val.data_u64 =3D GET_F64_RS2C(insn, regs); +#if !defined(CONFIG_64BIT) + } else if ((insn & INSN_MASK_C_FSW) =3D=3D INSN_MATCH_C_FSW) { + fp =3D 1; + len =3D 4; + val.data_ulong =3D GET_F32_RS2S(insn, regs); + } else if ((insn & INSN_MASK_C_FSWSP) =3D=3D INSN_MATCH_C_FSWSP) { + fp =3D 1; + len =3D 4; + val.data_ulong =3D GET_F32_RS2C(insn, regs); +#endif } else { regs->epc =3D epc; return -1; } =20 + if (!IS_ENABLED(CONFIG_FPU) && fp) + return -EOPNOTSUPP; + for (i =3D 0; i < len; i++) { if (store_u8(regs, (void *)(addr + i), val.data_bytes[i])) return -1; --=20 2.40.1 From nobody Fri Feb 13 09:49:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF353E7E64C for ; Tue, 26 Sep 2023 15:04:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235050AbjIZPET (ORCPT ); Tue, 26 Sep 2023 11:04:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234996AbjIZPEE (ORCPT ); Tue, 26 Sep 2023 11:04:04 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B600120 for ; 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([2a01:e0a:999:a3a0:2b3d:6c70:9dbf:5ede]) by smtp.gmail.com with ESMTPSA id x11-20020a5d650b000000b00318147fd2d3sm14926060wru.41.2023.09.26.08.03.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 08:03:56 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Atish Patra , Andrew Jones , Evan Green , =?UTF-8?q?Bj=C3=B6rn=20Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski Subject: [PATCH 5/7] riscv: add support for sysctl unaligned_enabled control Date: Tue, 26 Sep 2023 17:03:14 +0200 Message-Id: <20230926150316.1129648-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com> References: <20230926150316.1129648-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This sysctl tuning option allows the user to disable misaligned access handling globally on the system. This will also be used by misaligned detection code to temporarily disable misaligned access handling. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/traps_misaligned.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d607ab0f7c6d..3515510fe418 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -157,6 +157,7 @@ config RISCV select RISCV_TIMER if RISCV_SBI select SIFIVE_PLIC select SPARSE_IRQ + select SYSCTL_ARCH_UNALIGN_ALLOW select SYSCTL_EXCEPTION_TRACE select THREAD_INFO_IN_TASK select TRACE_IRQFLAGS_SUPPORT diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 041fd2dbd955..b5fb1ff078e3 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -396,6 +396,9 @@ union reg_data { u64 data_u64; }; =20 +/* sysctl hooks */ +int unaligned_enabled __read_mostly =3D 1; /* Enabled by default */ + int handle_misaligned_load(struct pt_regs *regs) { union reg_data val; @@ -406,6 +409,9 @@ int handle_misaligned_load(struct pt_regs *regs) =20 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); =20 + if (!unaligned_enabled) + return -1; + if (get_insn(regs, epc, &insn)) return -1; =20 @@ -502,6 +508,9 @@ int handle_misaligned_store(struct pt_regs *regs) =20 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); =20 + if (!unaligned_enabled) + return -1; + if (get_insn(regs, epc, &insn)) return -1; =20 --=20 2.40.1 From nobody Fri Feb 13 09:49:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1974DE7E64A for ; Tue, 26 Sep 2023 15:04:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235052AbjIZPEY (ORCPT ); Tue, 26 Sep 2023 11:04:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235006AbjIZPEG (ORCPT ); Tue, 26 Sep 2023 11:04:06 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 257BF10A for ; Tue, 26 Sep 2023 08:03:59 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-405d70d19bcso6057335e9.0 for ; Tue, 26 Sep 2023 08:03:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1695740637; x=1696345437; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cTRkIgCqvbOvq5WltvgZniNquXqWMppNcycuOTnJ1ME=; b=x79bgUMJe5UqQP4AUlj+09IEnJWhjCCeCBQu2ZsIN/vtaylYZUGwDHtOkcr9mtmqws vHvrCQKLHay24gpPqrv6akdx6jbziOJj1q/vg/rZ/3/Niyuzk3o/ShaJ45tnYVSrWLVF mc0xJbHd1XN43TgAIUU6PVtnBFdZm/aDDtiD9t3LT+sIl0EL/RaoUX/eNi0a1Yinvnvn nu8dy5JNnd0GFnwA/av6f/GzRD7uK7+CiVvMg1ipkZToLlkJigglqzYwolqBpzgE5Bj1 H4cVUTkzTLATbTM9fewbYePqpHCOQhGVMqxwHNznNxMvDRJek4ZjjBsB/3L0g96JUdy6 ZBRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695740637; x=1696345437; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cTRkIgCqvbOvq5WltvgZniNquXqWMppNcycuOTnJ1ME=; b=KmGX7405fznQcHu5QYXPl94elu0JTRs8A+LJppmGFre5YnVpNt6RnqUGbmcUY+9qIW hy+TlHD4ioY2bWj/qYEF0HQlsm2TLDNvoAio3y6C36/tznEGKJMnrt0gsZ5WRc7wu+Xx GnkL75HngatuawGkO201n+P9Cxm21zWQ7QtX9FZuAl417Qe8/26e2IphOppX9vHn+N8h S9VgGR0UP+9bt+QN9MOMwHY52XGgsloAJDdqD7peC9ZMvEc2uzu5E+MPbxk7fgpoRJJF wvoNa3GRGY7hMOvNldZUJxyQOiasQ6v26SxwwkuvOt5VtJ77UMB2l7TkuFu1srvV9rwZ gNfQ== X-Gm-Message-State: AOJu0YytXLQ/FQU2pZKs1OW2RrmIkIX/xLKEYFwkm4yFmGX7HLaNyIql fyQXEO+2BrSwxa6amGbzT1Jm7g== X-Google-Smtp-Source: AGHT+IF3tl133AyKMYwdf3JEZLgsj3bubF0UkQguDXYTyEpNjLdmnD+OMwVORcOYpBaWMoc41tZGgQ== X-Received: by 2002:adf:e945:0:b0:31a:e29f:5eab with SMTP id m5-20020adfe945000000b0031ae29f5eabmr8963359wrn.7.1695740637664; Tue, 26 Sep 2023 08:03:57 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:2b3d:6c70:9dbf:5ede]) by smtp.gmail.com with ESMTPSA id x11-20020a5d650b000000b00318147fd2d3sm14926060wru.41.2023.09.26.08.03.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 08:03:57 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Atish Patra , Andrew Jones , Evan Green , =?UTF-8?q?Bj=C3=B6rn=20Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski Subject: [PATCH 6/7] riscv: report misaligned accesses emulation to hwprobe Date: Tue, 26 Sep 2023 17:03:15 +0200 Message-Id: <20230926150316.1129648-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com> References: <20230926150316.1129648-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org hwprobe provides a way to report if misaligned access are emulated. In order to correctly populate that feature, we can check if it actually traps when doing a misaligned access. This can be checked using an exception table entry which will actually be used when a misaligned access is done from kernel mode. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/cpufeature.h | 6 +++ arch/riscv/kernel/cpufeature.c | 6 ++- arch/riscv/kernel/setup.c | 1 + arch/riscv/kernel/traps_misaligned.c | 63 +++++++++++++++++++++++++++- 4 files changed, 74 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index d0345bd659c9..c1f0ef02cd7d 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -8,6 +8,7 @@ =20 #include #include +#include =20 /* * These are probed via a device_initcall(), via either the SBI or directly @@ -32,4 +33,9 @@ extern struct riscv_isainfo hart_isa[NR_CPUS]; =20 void check_unaligned_access(int cpu); =20 +bool unaligned_ctl_available(void); + +bool check_unaligned_access_emulated(int cpu); +void unaligned_emulation_finish(void); + #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1cfbba65d11a..fbbde800bc21 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -568,6 +568,9 @@ void check_unaligned_access(int cpu) void *src; long speed =3D RISCV_HWPROBE_MISALIGNED_SLOW; =20 + if (check_unaligned_access_emulated(cpu)) + return; + page =3D alloc_pages(GFP_NOWAIT, get_order(MISALIGNED_BUFFER_SIZE)); if (!page) { pr_warn("Can't alloc pages to measure memcpy performance"); @@ -645,9 +648,10 @@ void check_unaligned_access(int cpu) __free_pages(page, get_order(MISALIGNED_BUFFER_SIZE)); } =20 -static int check_unaligned_access_boot_cpu(void) +static int __init check_unaligned_access_boot_cpu(void) { check_unaligned_access(0); + unaligned_emulation_finish(); return 0; } =20 diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index e600aab116a4..3af6ad4df7cf 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index b5fb1ff078e3..fa81f6952fa4 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -9,11 +9,14 @@ #include #include #include +#include =20 #include #include #include #include +#include +#include =20 #define INSN_MATCH_LB 0x3 #define INSN_MASK_LB 0x707f @@ -396,8 +399,10 @@ union reg_data { u64 data_u64; }; =20 +static bool unaligned_ctl __read_mostly; + /* sysctl hooks */ -int unaligned_enabled __read_mostly =3D 1; /* Enabled by default */ +int unaligned_enabled __read_mostly; =20 int handle_misaligned_load(struct pt_regs *regs) { @@ -412,6 +417,9 @@ int handle_misaligned_load(struct pt_regs *regs) if (!unaligned_enabled) return -1; =20 + if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS)) + return -1; + if (get_insn(regs, epc, &insn)) return -1; =20 @@ -511,6 +519,9 @@ int handle_misaligned_store(struct pt_regs *regs) if (!unaligned_enabled) return -1; =20 + if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS)) + return -1; + if (get_insn(regs, epc, &insn)) return -1; =20 @@ -585,3 +596,53 @@ int handle_misaligned_store(struct pt_regs *regs) =20 return 0; } + +bool check_unaligned_access_emulated(int cpu) +{ + unsigned long emulated =3D 1, tmp_var; + + /* Use a fixup to detect if misaligned access triggered an exception */ + __asm__ __volatile__ ( + "1:\n" + " "REG_L" %[tmp], 1(%[ptr])\n" + " li %[emulated], 0\n" + "2:\n" + _ASM_EXTABLE(1b, 2b) + : [emulated] "+r" (emulated), [tmp] "=3Dr" (tmp_var) + : [ptr] "r" (&tmp_var) + : "memory"); + + if (!emulated) + return false; + + per_cpu(misaligned_access_speed, cpu) =3D + RISCV_HWPROBE_MISALIGNED_EMULATED; + + return true; +} + +void __init unaligned_emulation_finish(void) +{ + int cpu; + + /* + * We can only support PR_UNALIGN controls if all CPUs have misaligned + * accesses emulated since tasks requesting such control can run on any + * CPU. + */ + for_each_possible_cpu(cpu) { + if (per_cpu(misaligned_access_speed, cpu) !=3D + RISCV_HWPROBE_MISALIGNED_EMULATED) { + goto out; + } + } + unaligned_ctl =3D true; + +out: + unaligned_enabled =3D 1; +} + +bool unaligned_ctl_available(void) +{ + return unaligned_ctl; +} --=20 2.40.1 From nobody Fri Feb 13 09:49:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93272E7E644 for ; Tue, 26 Sep 2023 15:04:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235082AbjIZPEV (ORCPT ); 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([2a01:e0a:999:a3a0:2b3d:6c70:9dbf:5ede]) by smtp.gmail.com with ESMTPSA id x11-20020a5d650b000000b00318147fd2d3sm14926060wru.41.2023.09.26.08.03.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 08:03:58 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Atish Patra , Andrew Jones , Evan Green , =?UTF-8?q?Bj=C3=B6rn=20Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski Subject: [PATCH 7/7] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Date: Tue, 26 Sep 2023 17:03:16 +0200 Message-Id: <20230926150316.1129648-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com> References: <20230926150316.1129648-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that trap support is ready to handle misalignment errors in S-mode, allow the user to control the behavior of misaligned accesses using prctl(PR_SET_UNALIGN). Add an align_ctl flag in thread_struct which will be used to determine if we should SIGBUS the process or not on such fault. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/processor.h | 9 +++++++++ arch/riscv/kernel/process.c | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 3e23e1786d05..adbe520d07c5 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -8,6 +8,7 @@ =20 #include #include +#include =20 #include =20 @@ -82,6 +83,7 @@ struct thread_struct { unsigned long bad_cause; unsigned long vstate_ctrl; struct __riscv_v_ext_state vstate; + unsigned long align_ctl; }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ @@ -94,6 +96,7 @@ static inline void arch_thread_struct_whitelist(unsigned = long *offset, =20 #define INIT_THREAD { \ .sp =3D sizeof(init_stack) + (long)&init_stack, \ + .align_ctl =3D PR_UNALIGN_NOPRINT, \ } =20 #define task_pt_regs(tsk) \ @@ -134,6 +137,12 @@ extern long riscv_v_vstate_ctrl_set_current(unsigned l= ong arg); extern long riscv_v_vstate_ctrl_get_current(void); #endif /* CONFIG_RISCV_ISA_V */ =20 +extern int get_unalign_ctl(struct task_struct *tsk, unsigned long addr); +extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); + +#define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) +#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e32d737e039f..4f21d970a129 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -25,6 +25,7 @@ #include #include #include +#include =20 register unsigned long gp_in_global __asm__("gp"); =20 @@ -41,6 +42,23 @@ void arch_cpu_idle(void) cpu_do_idle(); } =20 +int set_unalign_ctl(struct task_struct *tsk, unsigned int val) +{ + if (!unaligned_ctl_available()) + return -EINVAL; + + tsk->thread.align_ctl =3D val; + return 0; +} + +int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) +{ + if (!unaligned_ctl_available()) + return -EINVAL; + + return put_user(tsk->thread.align_ctl, (unsigned long __user *)adr); +} + void __show_regs(struct pt_regs *regs) { show_regs_print_info(KERN_DEFAULT); --=20 2.40.1