From nobody Fri Feb 13 12:42:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68BB7CE7A9A for ; Mon, 25 Sep 2023 16:22:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231352AbjIYQWc (ORCPT ); Mon, 25 Sep 2023 12:22:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231213AbjIYQWa (ORCPT ); Mon, 25 Sep 2023 12:22:30 -0400 Received: from mx0a-00069f02.pphosted.com (mx0a-00069f02.pphosted.com [205.220.165.32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 302F0BE for ; Mon, 25 Sep 2023 09:22:24 -0700 (PDT) Received: from pps.filterd (m0246617.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38PECECD002029; Mon, 25 Sep 2023 16:22:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=corp-2023-03-30; bh=tvy6Z6szTq1bAkmZQeSWwGo173Ev+55Y3onQnABhxWE=; b=0b4AwQ0qGeBCDjIUBsIw+iJIfPLliB4+j5+kmZOHZwCnFvA6N/7pL5VeFc9GG05/q52E BzVqVF04dftXPZqhSH49fTHLP2lSZ1w1EFa0C9f5X4zP4KnmEuO2+q8VDZOS6s+Gs90w RpKwWMiFTGubE0NTwI9gC0s/i2cKDrG0kKxZg9Zoyv6MnN11T0X0oFQvXx1FtH0taG7S PvZkigoT359Z9oVmOiDKh47xZb7R5oKWV+BVE3vKVVo7z33ZYHb7D0HsiZYW1FzYw5eZ xnY8TwFDMzKS2aO23d7KgU9DwikrKYwbajY0oMhP2B42iJ/5r1VSDGF/puwH4NIHT0Aq rg== Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.appoci.oracle.com [138.1.37.129]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3t9rjuc48f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 25 Sep 2023 16:22:06 +0000 Received: from pps.filterd (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (8.17.1.19/8.17.1.19) with ESMTP id 38PFZV6T034921; Mon, 25 Sep 2023 16:22:05 GMT Received: from pps.reinject (localhost [127.0.0.1]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTPS id 3t9pf4ydsx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 25 Sep 2023 16:22:05 +0000 Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 38PGLi20024071; Mon, 25 Sep 2023 16:22:04 GMT Received: from mlluis-mac.uk.oracle.com (dhcp-10-175-170-37.vpn.oracle.com [10.175.170.37]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 3t9pf4ycur-2; Mon, 25 Sep 2023 16:22:04 +0000 From: Miguel Luis To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev Cc: miguel.luis@oracle.com Subject: [PATCH v2 1/2] arm64: Add missing _EL12 encodings Date: Mon, 25 Sep 2023 16:20:56 +0000 Message-Id: <20230925162057.27548-2-miguel.luis@oracle.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230925162057.27548-1-miguel.luis@oracle.com> References: <20230925162057.27548-1-miguel.luis@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-25_13,2023-09-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 bulkscore=0 mlxscore=0 mlxlogscore=984 suspectscore=0 phishscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2309250126 X-Proofpoint-ORIG-GUID: mPV9hicQh9mSiFp7cSPhziEQ-GfnxV-A X-Proofpoint-GUID: mPV9hicQh9mSiFp7cSPhziEQ-GfnxV-A Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some _EL12 encodings are missing. Add them. Signed-off-by: Miguel Luis Reviewed-by: Eric Auger --- arch/arm64/include/asm/sysreg.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 38296579a4fd..6e167bbf44ff 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -568,18 +568,29 @@ =20 /* VHE encodings for architectural EL0/1 system registers */ #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) +#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) +#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3) +#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) +#define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1) +#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6) #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) +#define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3) #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) +#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) +#define SYS_BRBCR_EL12 sys_reg(3, 5, 9, 0, 0) +#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0) #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) +#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) +#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7) #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) --=20 2.39.2 From nobody Fri Feb 13 12:42:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBF44CE7A9A for ; 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Mon, 25 Sep 2023 16:22:20 +0000 Received: from phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 38PGLi22024071; Mon, 25 Sep 2023 16:22:20 GMT Received: from mlluis-mac.uk.oracle.com (dhcp-10-175-170-37.vpn.oracle.com [10.175.170.37]) by phxpaimrmta03.imrmtpd1.prodappphxaev1.oraclevcn.com (PPS) with ESMTP id 3t9pf4ycur-3; Mon, 25 Sep 2023 16:22:20 +0000 From: Miguel Luis To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev Cc: miguel.luis@oracle.com Subject: [PATCH v2 2/2] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization Date: Mon, 25 Sep 2023 16:20:57 +0000 Message-Id: <20230925162057.27548-3-miguel.luis@oracle.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230925162057.27548-1-miguel.luis@oracle.com> References: <20230925162057.27548-1-miguel.luis@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-25_13,2023-09-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 bulkscore=0 mlxscore=0 mlxlogscore=999 suspectscore=0 phishscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2309250126 X-Proofpoint-ORIG-GUID: 0at01WG6PMWVVC80OzCSmus-Wdc347wc X-Proofpoint-GUID: 0at01WG6PMWVVC80OzCSmus-Wdc347wc Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some _EL1 registers got included in the _EL2 ranges, which are not affected by NV. Remove them, fine grain the ranges to exclusively include the _EL2 ones and fold SPSR/ELR _EL2 registers into the existing range. Signed-off-by: Miguel Luis --- arch/arm64/kvm/emulate-nested.c | 44 ++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 9ced1bf0c2b7..f6d0c87803f4 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -649,14 +649,46 @@ static const struct encoding_to_trap_config encoding_= to_cgt[] __initconst =3D { SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK), /* All _EL2 registers */ SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0), - sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV), + sys_reg(3, 4, 4, 0, 1), CGT_HCR_NV), /* Skip the SP_EL1 encoding... */ - SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV), - SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV), - SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1), - sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV), + SR_RANGE_TRAP(sys_reg(3, 4, 4, 3, 0), + sys_reg(3, 4, 10, 6, 7), CGT_HCR_NV), + /* + * Note that the spec. describes a group of MEC registers + * whose access should not trap, therefore skip the following: + * MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2, + * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, + * VMECID_P_EL2. + */ SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0), - sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV), + sys_reg(3, 4, 12, 1, 1), CGT_HCR_NV), + /* ICH_AP0R_EL2 */ + SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2, + SYS_ICH_AP0R3_EL2, CGT_HCR_NV), + /* ICH_AP1R_EL2 */ + SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2, + SYS_ICH_AP1R3_EL2, CGT_HCR_NV), + SR_RANGE_TRAP(sys_reg(3, 4, 12, 9, 5), + sys_reg(3, 4, 12, 11, 7), CGT_HCR_NV), + /* ICH_LR_EL2 */ + SR_RANGE_TRAP(SYS_ICH_LR0_EL2, + SYS_ICH_LR7_EL2, CGT_HCR_NV), + SR_RANGE_TRAP(SYS_ICH_LR8_EL2, + SYS_ICH_LR15_EL2, CGT_HCR_NV), + SR_RANGE_TRAP(sys_reg(3, 4, 13, 0, 1), + sys_reg(3, 4, 13, 0, 7), CGT_HCR_NV), + /* AMEVCNTVOFF0_EL2 */ + SR_RANGE_TRAP(sys_reg(3, 4, 13, 8, 0), + sys_reg(3, 4, 13, 8, 7), CGT_HCR_NV), + SR_RANGE_TRAP(sys_reg(3, 4, 13, 9, 0), + sys_reg(3, 4, 13, 9, 7), CGT_HCR_NV), + /* AMEVCNTVOFF1_EL2 */ + SR_RANGE_TRAP(sys_reg(3, 4, 13, 10, 0), + sys_reg(3, 4, 13, 10, 7), CGT_HCR_NV), + SR_RANGE_TRAP(sys_reg(3, 4, 13, 11, 0), + sys_reg(3, 4, 13, 11, 7), CGT_HCR_NV), + SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3), + sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV), /* All _EL02, _EL12 registers */ SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0), sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV), --=20 2.39.2