From nobody Fri Feb 13 14:07:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6078BCE7A94 for ; Mon, 25 Sep 2023 13:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232402AbjIYNkc (ORCPT ); Mon, 25 Sep 2023 09:40:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232289AbjIYNkT (ORCPT ); Mon, 25 Sep 2023 09:40:19 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 163791B8 for ; Mon, 25 Sep 2023 06:40:07 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1c364fb8a4cso58188685ad.1 for ; Mon, 25 Sep 2023 06:40:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695649206; x=1696254006; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uNHkjMM9HHYX8X83JcKOMwoHgKf/W4d95vsynq44CKo=; b=DcPfR/9E9VIPS1KbhspDAtONK1QO7eCSq9YKJW/V31SnY0ALc1hafseuwAifZZ3zlc ILC5PMi6e8eBlnnHfR3H7hNH3iaS2krL5aKqxy8E+bPbXHk1+neCoqn3nFUp6eGOwLsu bGq63E8omdmTzQKn+q+k9iyLCGUHCxsepV81iLrDBMJtl0tgKVXyIJwpcFAY/Cq48Iai iozTYONBEmDY+0NVUN/wTo3TjL3DW99sqEa7twTAfTl0L35IDQHn0m7H+Mt+1mCG/k2f 5S87FVsMKy9EQ1BzuqCtB2CojIMGkLZk08EmQKNoNfV9NK+8jdV7Pm93GLauRB0rKFC7 B8GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695649206; x=1696254006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uNHkjMM9HHYX8X83JcKOMwoHgKf/W4d95vsynq44CKo=; b=QS3b9ivcP+oBIGPhMQ0zUua1bwqu+oIV4HMarGFzCVS3RquJgQOrl8m2J9pA4L1TtQ rPeWxZSuplCflmBtwFnZHaGpbCN07eOtWia/gRspLWuRJtVls0i352iUqqPCT01ZAOcS Ux30YQEuu33WDsYtTToU3g+/m0D2fPNWM8YUjrUF/ZbQ5jH/vl029MvkG4kpE4f/uIWI Rr9XVPHZ3R2gGN5yz620Q0sPO8kEOspgL0uK79uSoUeE4qawQ+oS+mSHmasi/eHM0btN m/63cuYZrWxa28LBUadYEUXexPyUQiZlnhJdb9NsadTR1suEqo0L3KIRWSkJHCzcTZ7w /95A== X-Gm-Message-State: AOJu0YyaOLBXywi4LMroT+JAWRINgTmwYiZoMqW7+LAih1wgUP2vhOcs 5dRuLLlVUQ1/8bk07xLO5TmaIA== X-Google-Smtp-Source: AGHT+IGU21ACNUey6DzMiWsfg977IabscEjcD4GfNCnNUexJxmWmu1U36ws4l5wFoYxptLxUg/E8xA== X-Received: by 2002:a17:902:d50e:b0:1c5:74db:dc8b with SMTP id b14-20020a170902d50e00b001c574dbdc8bmr8353875plg.58.1695649206310; Mon, 25 Sep 2023 06:40:06 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id p11-20020a170902eacb00b001c625d6ffccsm969433pld.129.2023.09.25.06.40.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 06:40:05 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 8/9] KVM: riscv: selftests: Add smstateen registers to get-reg-list test Date: Mon, 25 Sep 2023 19:08:58 +0530 Message-Id: <20230925133859.1735879-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We have a new smstateen registers as separate sub-type of CSR ONE_REG interface so let us add these registers to get-reg-list test. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- .../selftests/kvm/riscv/get-reg-list.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 6cec0ef75cc7..625118d53b74 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -36,6 +36,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL: @@ -186,6 +187,8 @@ static const char *core_id_to_str(const char *prefix, _= _u64 id) "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")" #define RISCV_CSR_AIA(csr) \ "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")" +#define RISCV_CSR_SMSTATEEN(csr) \ + "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")" =20 static const char *general_csr_id_to_str(__u64 reg_off) { @@ -243,6 +246,18 @@ static const char *aia_csr_id_to_str(__u64 reg_off) return NULL; } =20 +static const char *smstateen_csr_id_to_str(__u64 reg_off) +{ + /* reg_off is the offset into struct kvm_riscv_smstateen_csr */ + switch (reg_off) { + case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0): + return RISCV_CSR_SMSTATEEN(sstateen0); + } + + TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off); + return NULL; +} + static const char *csr_id_to_str(const char *prefix, __u64 id) { __u64 reg_off =3D id & ~(REG_MASK | KVM_REG_RISCV_CSR); @@ -255,6 +270,8 @@ static const char *csr_id_to_str(const char *prefix, __= u64 id) return general_csr_id_to_str(reg_off); case KVM_REG_RISCV_CSR_AIA: return aia_csr_id_to_str(reg_off); + case KVM_REG_RISCV_CSR_SMSTATEEN: + return smstateen_csr_id_to_str(reg_off); } =20 TEST_FAIL("%s: Unknown csr subtype: 0x%llx", prefix, reg_subtype); @@ -332,6 +349,7 @@ static const char *isa_ext_id_to_str(__u64 id) KVM_ISA_EXT_ARR(I), KVM_ISA_EXT_ARR(M), KVM_ISA_EXT_ARR(V), + KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), @@ -637,6 +655,11 @@ static __u64 aia_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_IS= A_EXT_SSAIA, }; =20 +static __u64 smstateen_regs[] =3D { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CS= R_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_IS= A_EXT_SMSTATEEN, +}; + static __u64 fp_f_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_= F_REG(f[0]), KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_= F_REG(f[1]), @@ -744,6 +767,8 @@ static __u64 fp_d_regs[] =3D { {"zihpm", .feature =3D KVM_RISCV_ISA_EXT_ZIHPM, .regs =3D zihpm_regs, .re= gs_n =3D ARRAY_SIZE(zihpm_regs),} #define AIA_REGS_SUBLIST \ {"aia", .feature =3D KVM_RISCV_ISA_EXT_SSAIA, .regs =3D aia_regs, .regs_n= =3D ARRAY_SIZE(aia_regs),} +#define SMSTATEEN_REGS_SUBLIST \ + {"smstateen", .feature =3D KVM_RISCV_ISA_EXT_SMSTATEEN, .regs =3D smstate= en_regs, .regs_n =3D ARRAY_SIZE(smstateen_regs),} #define FP_F_REGS_SUBLIST \ {"fp_f", .feature =3D KVM_RISCV_ISA_EXT_F, .regs =3D fp_f_regs, \ .regs_n =3D ARRAY_SIZE(fp_f_regs),} @@ -871,6 +896,14 @@ static struct vcpu_reg_list aia_config =3D { }, }; =20 +static struct vcpu_reg_list smstateen_config =3D { + .sublists =3D { + BASE_SUBLIST, + SMSTATEEN_REGS_SUBLIST, + {0}, + }, +}; + static struct vcpu_reg_list fp_f_config =3D { .sublists =3D { BASE_SUBLIST, @@ -903,6 +936,7 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &zifencei_config, &zihpm_config, &aia_config, + &smstateen_config, &fp_f_config, &fp_d_config, }; --=20 2.34.1