From nobody Fri Feb 13 14:07:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0FDFCE7A81 for ; Mon, 25 Sep 2023 13:50:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232023AbjIYNjj (ORCPT ); Mon, 25 Sep 2023 09:39:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232004AbjIYNjg (ORCPT ); Mon, 25 Sep 2023 09:39:36 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73FC1116 for ; Mon, 25 Sep 2023 06:39:28 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1c09673b006so42614505ad.1 for ; Mon, 25 Sep 2023 06:39:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695649168; x=1696253968; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gV6mGP1XJq3xnVTxbQIHP/QVhp+GQJw7IZPtitWR2ag=; b=A6WdT3Ms5qTGJi16CIzV3LYdlwDMjnbBLsEPGCDcOKQcyZA921afkObt2VLhpHKZLC 6MfulKaJCE7NanK54WJ2oJjaohRAYzI2ByVbfFc2HKj9UOB4rc/whHNUmS5eHdtgJyXi AINXkgngAKvugN8i1lKGeAyf/9UmFacUHb1lbXIXHMJGhqg0yopKuLT7FKKoE77efTk+ /BNs8WWIfyN50EM9vgT4Rr7YiMJueTGOWSGC65XyiO49OowomkkyCxMFYN4FFmgiC78s +G9bBk6uiDNkruPtvj6vjcrseTHAOWydCDGUhJ4H/JTP8P4n57RSxXQZpidOBOA78eoy E3YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695649168; x=1696253968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gV6mGP1XJq3xnVTxbQIHP/QVhp+GQJw7IZPtitWR2ag=; b=PCdWWJ2K7fK0DagB2tMt/FWG7g8xGB0DdFLYzqshZoZqqpighsTZKjYNknitUlE8nT fvbxHUW1JQnEVf54l8GH91X+XN+jwBF89GMDIsxPvvgs3QfQByGTP1PrCfywePUmAuem pDvTHJQMfQMiQGKlQ6aChZRN8VRmv+AqdOXgpJn9N6Ct4X7qm+uPtJgxp6Ct0DbuNgIi EOpJwHN6vjU2yeTEnXZyw6NmGKUuY7FkRdNxQFvJHl+qqSmiNLakIZUnAu7Bfk3BBT7k 2zi0VxT8FMR6lQJoFSdU70pPBvIKgU/jFIbShT2icOchfoJSJyCsLR3y7vSHoehdUUf3 O+ig== X-Gm-Message-State: AOJu0Yzuqlh0KWshb5zSm2LK5z50yepPPSGGQw7bcoN2DfNMlccmWMvs C9Wuv9BLZwkP7pZOV96CZydE9A== X-Google-Smtp-Source: AGHT+IEDXrhyEx6eaSZ6frtjTYSejpa1s2eAnJYzebqP5g4HzZCjNkN/tfngtcIrEJra3Z7D04o6Dg== X-Received: by 2002:a17:902:c10c:b0:1c5:741d:f388 with SMTP id 12-20020a170902c10c00b001c5741df388mr4868718pli.9.1695649167770; Mon, 25 Sep 2023 06:39:27 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id p11-20020a170902eacb00b001c625d6ffccsm969433pld.129.2023.09.25.06.39.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 06:39:27 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 2/9] RISC-V: Detect XVentanaCondOps from ISA string Date: Mon, 25 Sep 2023 19:08:52 +0530 Message-Id: <20230925133859.1735879-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Veyron-V1 CPU supports custom conditional arithmetic and conditional-select/move operations referred to as XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating XVentanaCondOps extension. Let us detect XVentanaCondOps extension from ISA string available through DT or ACPI. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 0f520f7d058a..b7efe9e2fa89 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -59,6 +59,7 @@ #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_SMSTATEEN 43 +#define RISCV_ISA_EXT_XVENTANACONDOPS 44 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3755a8c2a9de..3a31d34fe709 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS), }; =20 const size_t riscv_isa_ext_count =3D ARRAY_SIZE(riscv_isa_ext); --=20 2.34.1