From nobody Fri Feb 13 12:28:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94B3ACE7A96 for ; Mon, 25 Sep 2023 13:39:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231916AbjIYNjb (ORCPT ); Mon, 25 Sep 2023 09:39:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231908AbjIYNj3 (ORCPT ); Mon, 25 Sep 2023 09:39:29 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8141FF for ; Mon, 25 Sep 2023 06:39:21 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1c1e3a4a06fso42172135ad.3 for ; Mon, 25 Sep 2023 06:39:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695649161; x=1696253961; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CsJSyEFV+awfjzqWEQrKDCJAKL6BoM6HZkqImf1ste0=; b=m9RKglTm9ThCLxCO6QpyfZX+xezakDScSzhxxCsFI2lcoF1CdQ2n2+6QirVUvUM6cz 8ufWJLRbXuynmoYSnlJWMyah5Tk+hmQQTWhajOdEIwobybVnPXOvrDXZVxcSMyknMJNY DrcAdTeaa5F+XOQc+N/2DT9aO70g9tkGfXqY4Y7dL3V71b722/nkrxyQll8PZ5hrS/RZ q4izsoLjRn+QectI65Ncw1/r9i6fciqPf7eQoB4Dt1PGE5aCmlMNu6GMcr+8Zl31A9hI 1Zj/FPCi4MTY4XU5OpQDu5Dyv4/JYb++1ryf6qbIW5x3YWEyc7u2sKr3Empqil/3qkmF xe3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695649161; x=1696253961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CsJSyEFV+awfjzqWEQrKDCJAKL6BoM6HZkqImf1ste0=; b=Rbt80+hb+v262F0fNvDwjZ0eMSnerqTKGKOoIiKnew0utOsaK/vIdxbitbOo9z6jCm NFmhOtX7+y+hMjL3QG/sCsx1kP29ObnXt8bLKcpPh1Bp6QtzQt3VN1wUQ40tosdPLatu kRgqWx15kBuF6NHshk9HzYYc94EHHvoCuC54Y8fGNKiWPCqq2D82E/Y3n31jU9z5/Gv9 eJ9slvrNkK9oevkK4ljoLhFNrDZfxIfckUo2XlUzUkAr4hNAnFyEAaehzL0N4s3XBmAx JLVI/0iuz1eh4r5RP39OLCWMncn8qNfgTIOdQ9LxPdVQ4HtJOqeKZO2bMnmHjJwqNB6c Sq/g== X-Gm-Message-State: AOJu0Yy3m8pbRhyDRc/C5TaCpQ5BevydJEmKKHzQvsZsOJ+lAu8bTpox O9pFSIPlhtKqMWp0WS4avnI9Qg== X-Google-Smtp-Source: AGHT+IGqj9n3VQj53FXQlpdMHVR+4bQF5JgIjkaYGnLOH0hemDoUwEedX5Qz4D6VU5amsUQF9Mm5Cg== X-Received: by 2002:a17:903:32cf:b0:1c6:1ac5:144c with SMTP id i15-20020a17090332cf00b001c61ac5144cmr2569000plr.40.1695649161179; Mon, 25 Sep 2023 06:39:21 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id p11-20020a170902eacb00b001c625d6ffccsm969433pld.129.2023.09.25.06.39.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 06:39:20 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 1/9] dt-bindings: riscv: Add XVentanaCondOps extension entry Date: Mon, 25 Sep 2023 19:08:51 +0530 Message-Id: <20230925133859.1735879-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add an entry for the XVentanaCondOps extension to the riscv,isa-extensions property. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 36ff6749fbba..cad8ef68eca7 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -171,6 +171,13 @@ properties: memory types as ratified in the 20191213 version of the privil= eged ISA specification. =20 + - const: xventanacondops + description: | + The Ventana specific XVentanaCondOps extension for conditional + arithmetic and conditional-select/move operations defined by t= he + Ventana custom extensions specification v1.0.1 (or higher) at + https://github.com/ventanamicro/ventana-custom-extensions/rele= ases. + - const: zba description: | The standard Zba bit-manipulation extension for address genera= tion --=20 2.34.1 From nobody Fri Feb 13 12:28:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0FDFCE7A81 for ; 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Mon, 25 Sep 2023 06:39:27 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id p11-20020a170902eacb00b001c625d6ffccsm969433pld.129.2023.09.25.06.39.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 06:39:27 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 2/9] RISC-V: Detect XVentanaCondOps from ISA string Date: Mon, 25 Sep 2023 19:08:52 +0530 Message-Id: <20230925133859.1735879-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Veyron-V1 CPU supports custom conditional arithmetic and conditional-select/move operations referred to as XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating XVentanaCondOps extension. Let us detect XVentanaCondOps extension from ISA string available through DT or ACPI. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 0f520f7d058a..b7efe9e2fa89 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -59,6 +59,7 @@ #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_SMSTATEEN 43 +#define RISCV_ISA_EXT_XVENTANACONDOPS 44 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3755a8c2a9de..3a31d34fe709 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS), }; 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Mon, 25 Sep 2023 06:39:33 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 3/9] dt-bindings: riscv: Add Zicond extension entry Date: Mon, 25 Sep 2023 19:08:53 +0530 Message-Id: <20230925133859.1735879-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add an entry for the Zicond extension to the riscv,isa-extensions property. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index cad8ef68eca7..3f0b47686080 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -225,6 +225,12 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification. =20 + - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 95cf1= f9 + ("Add changes requested by Ved during signoff") of riscv-zicon= d. + - const: zicsr description: | The standard Zicsr extension for control and status register --=20 2.34.1 From nobody Fri Feb 13 12:28:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58C91CE7A98 for ; Mon, 25 Sep 2023 13:39:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232106AbjIYNju (ORCPT ); Mon, 25 Sep 2023 09:39:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232063AbjIYNjr (ORCPT ); Mon, 25 Sep 2023 09:39:47 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 351C6FF for ; Mon, 25 Sep 2023 06:39:41 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1c60f1a2652so16003375ad.0 for ; Mon, 25 Sep 2023 06:39:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695649180; x=1696253980; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G0o9lQ4GgOP7dFq6KPsGtVotlHRRQlDwzXlKCC3Ypps=; b=ZQB63PmMZx3tf9Lzotp/7jqmTkeArhlhJmFx+R3ZmyCQn4gZmKC26wi/MDaPbvTh9a E8lQBohJCh0vz7DvNrvnrpK6ZcEEb/jgCwbW6W08kmSTncPnNZZ8asG5xXIdAXztzd7/ N5YZLMKNbxos2nZGH2pvhkpeNXayTZhHGPqgEt2uE7Ar9gxUQnzjHVgFOoucUz2FgcUY abagfCMYCRaZpnyaN60z4jrJFwH6YiLm4yT/FloMD04N0braiD8mH+QKiuabrjbBYD6X PtenvReLIF4OenYQtCQLZe+4fipxN3V5mS5VfjXCPFvL/MUlC/J03PfQWauKBpciU8jd Zjrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695649180; x=1696253980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G0o9lQ4GgOP7dFq6KPsGtVotlHRRQlDwzXlKCC3Ypps=; b=icrpTN+/Q8Jj1pwOHAJf2F19aqlK/kRd5PXOmiOELHwk2wZXTrIN9iskFX89creGST KZj5Q/rl1C6i2CCqe7mUKK/6dxy2iDmytPBdA/LGoyeNRSVyw9bqAgHqD+tqR7ZCd3jc HOdWV21pMcwFAKjJeyr6gbf/QIHRiox+HoaMxa2zEQfjnCkSpoaPRsEGiBT0l5LEK5Jg RDFHww3ZLve2n+bL5Kp4VJKwXi3m+F58fnI5awq9NmvtInmSXONLZggI49CX0mMMmmFG PkbpFUOCgMTJKdcGP+mb25SeyxyXbCXy4MQO9pZgCu/XLnhffnJ5/jLqR3ZN5LeDt+dC 7rNg== X-Gm-Message-State: AOJu0Yy11qf9+jvOjjDIlLsxugQpPKfw7y25uUsBpqNkZ19sqqU4A6xg nR91AX1udEmj+ImRa4TqOE/qVg== X-Google-Smtp-Source: AGHT+IHWCYspI/fUj+Ig0k3L9hYf5Uzb2FzPkjigw9xzhpmfqfpqTqSt/ibnnqx7qGmYx7Sty1gsrA== X-Received: by 2002:a17:902:e5d1:b0:1c3:868f:5958 with SMTP id u17-20020a170902e5d100b001c3868f5958mr14239969plf.20.1695649180488; Mon, 25 Sep 2023 06:39:40 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id p11-20020a170902eacb00b001c625d6ffccsm969433pld.129.2023.09.25.06.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 06:39:40 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 4/9] RISC-V: Detect Zicond from ISA string Date: Mon, 25 Sep 2023 19:08:54 +0530 Message-Id: <20230925133859.1735879-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V integer conditional (Zicond) operation extension defines standard conditional arithmetic and conditional-select/move operations which are inspired from the XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating Zicond extension. Let us detect Zicond extension from ISA string available through DT or ACPI. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b7efe9e2fa89..15bafc02ffd4 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -60,6 +60,7 @@ #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_SMSTATEEN 43 #define RISCV_ISA_EXT_XVENTANACONDOPS 44 +#define RISCV_ISA_EXT_ZICOND 45 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3a31d34fe709..7f683916f2c2 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -167,6 +167,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), --=20 2.34.1 From nobody Fri Feb 13 12:28:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68EC0CE7A94 for ; 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Mon, 25 Sep 2023 06:39:46 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id p11-20020a170902eacb00b001c625d6ffccsm969433pld.129.2023.09.25.06.39.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 06:39:46 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 5/9] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Date: Mon, 25 Sep 2023 19:08:55 +0530 Message-Id: <20230925133859.1735879-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable XVentanaCondOps extension for Guest/VM. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index b1baf6f096a3..e030c12c7dfc 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -138,6 +138,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZIFENCEI, KVM_RISCV_ISA_EXT_ZIHPM, KVM_RISCV_ISA_EXT_SMSTATEEN, + KVM_RISCV_ISA_EXT_XVENTANACONDOPS, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 388599fcf684..17a847a1114b 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -40,6 +40,7 @@ static const unsigned long kvm_isa_ext_arr[] =3D { KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), + KVM_ISA_EXT_ARR(XVENTANACONDOPS), KVM_ISA_EXT_ARR(ZBA), KVM_ISA_EXT_ARR(ZBB), KVM_ISA_EXT_ARR(ZBS), @@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned l= ong ext) case KVM_RISCV_ISA_EXT_SSTC: case KVM_RISCV_ISA_EXT_SVINVAL: case KVM_RISCV_ISA_EXT_SVNAPOT: + case KVM_RISCV_ISA_EXT_XVENTANACONDOPS: case KVM_RISCV_ISA_EXT_ZBA: case KVM_RISCV_ISA_EXT_ZBB: case KVM_RISCV_ISA_EXT_ZBS: --=20 2.34.1 From nobody Fri Feb 13 12:28:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36B78CE7A94 for ; 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Mon, 25 Sep 2023 06:39:53 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id p11-20020a170902eacb00b001c625d6ffccsm969433pld.129.2023.09.25.06.39.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 06:39:52 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 6/9] RISC-V: KVM: Allow Zicond extension for Guest/VM Date: Mon, 25 Sep 2023 19:08:56 +0530 Message-Id: <20230925133859.1735879-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zicond extension for Guest/VM. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index e030c12c7dfc..35ceb38a4eff 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -139,6 +139,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZIHPM, KVM_RISCV_ISA_EXT_SMSTATEEN, KVM_RISCV_ISA_EXT_XVENTANACONDOPS, + KVM_RISCV_ISA_EXT_ZICOND, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 17a847a1114b..d3ca4969c985 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -47,6 +47,7 @@ static const unsigned long kvm_isa_ext_arr[] =3D { KVM_ISA_EXT_ARR(ZICBOM), KVM_ISA_EXT_ARR(ZICBOZ), KVM_ISA_EXT_ARR(ZICNTR), + KVM_ISA_EXT_ARR(ZICOND), KVM_ISA_EXT_ARR(ZICSR), KVM_ISA_EXT_ARR(ZIFENCEI), KVM_ISA_EXT_ARR(ZIHINTPAUSE), @@ -95,6 +96,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned l= ong ext) case KVM_RISCV_ISA_EXT_ZBB: case KVM_RISCV_ISA_EXT_ZBS: case KVM_RISCV_ISA_EXT_ZICNTR: + case KVM_RISCV_ISA_EXT_ZICOND: case KVM_RISCV_ISA_EXT_ZICSR: case KVM_RISCV_ISA_EXT_ZIFENCEI: case KVM_RISCV_ISA_EXT_ZIHINTPAUSE: --=20 2.34.1 From nobody Fri Feb 13 12:28:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C01ECE7A95 for ; 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Mon, 25 Sep 2023 06:39:59 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id p11-20020a170902eacb00b001c625d6ffccsm969433pld.129.2023.09.25.06.39.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 06:39:59 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 7/9] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Date: Mon, 25 Sep 2023 19:08:57 +0530 Message-Id: <20230925133859.1735879-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We have a new senvcfg register in the general CSR ONE_REG interface so let us add it to get-reg-list test. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index a61b706a8778..6cec0ef75cc7 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -211,6 +211,8 @@ static const char *general_csr_id_to_str(__u64 reg_off) return RISCV_CSR_GENERAL(satp); case KVM_REG_RISCV_CSR_REG(scounteren): return RISCV_CSR_GENERAL(scounteren); + case KVM_REG_RISCV_CSR_REG(senvcfg): + return RISCV_CSR_GENERAL(senvcfg); } =20 TEST_FAIL("Unknown general csr reg: 0x%llx", reg_off); @@ -540,6 +542,7 @@ static __u64 base_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CS= R_GENERAL | KVM_REG_RISCV_CSR_REG(sip), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CS= R_GENERAL | KVM_REG_RISCV_CSR_REG(satp), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CS= R_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CS= R_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TI= MER_REG(frequency), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TI= MER_REG(time), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TI= MER_REG(compare), --=20 2.34.1 From nobody Fri Feb 13 12:28:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6078BCE7A94 for ; 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Mon, 25 Sep 2023 06:40:06 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id p11-20020a170902eacb00b001c625d6ffccsm969433pld.129.2023.09.25.06.40.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 06:40:05 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 8/9] KVM: riscv: selftests: Add smstateen registers to get-reg-list test Date: Mon, 25 Sep 2023 19:08:58 +0530 Message-Id: <20230925133859.1735879-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We have a new smstateen registers as separate sub-type of CSR ONE_REG interface so let us add these registers to get-reg-list test. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- .../selftests/kvm/riscv/get-reg-list.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 6cec0ef75cc7..625118d53b74 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -36,6 +36,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL: @@ -186,6 +187,8 @@ static const char *core_id_to_str(const char *prefix, _= _u64 id) "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")" #define RISCV_CSR_AIA(csr) \ "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")" +#define RISCV_CSR_SMSTATEEN(csr) \ + "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")" =20 static const char *general_csr_id_to_str(__u64 reg_off) { @@ -243,6 +246,18 @@ static const char *aia_csr_id_to_str(__u64 reg_off) return NULL; } =20 +static const char *smstateen_csr_id_to_str(__u64 reg_off) +{ + /* reg_off is the offset into struct kvm_riscv_smstateen_csr */ + switch (reg_off) { + case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0): + return RISCV_CSR_SMSTATEEN(sstateen0); + } + + TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off); + return NULL; +} + static const char *csr_id_to_str(const char *prefix, __u64 id) { __u64 reg_off =3D id & ~(REG_MASK | KVM_REG_RISCV_CSR); @@ -255,6 +270,8 @@ static const char *csr_id_to_str(const char *prefix, __= u64 id) return general_csr_id_to_str(reg_off); case KVM_REG_RISCV_CSR_AIA: return aia_csr_id_to_str(reg_off); + case KVM_REG_RISCV_CSR_SMSTATEEN: + return smstateen_csr_id_to_str(reg_off); } =20 TEST_FAIL("%s: Unknown csr subtype: 0x%llx", prefix, reg_subtype); @@ -332,6 +349,7 @@ static const char *isa_ext_id_to_str(__u64 id) KVM_ISA_EXT_ARR(I), KVM_ISA_EXT_ARR(M), KVM_ISA_EXT_ARR(V), + KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), @@ -637,6 +655,11 @@ static __u64 aia_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_IS= A_EXT_SSAIA, }; =20 +static __u64 smstateen_regs[] =3D { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CS= R_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_IS= A_EXT_SMSTATEEN, +}; + static __u64 fp_f_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_= F_REG(f[0]), KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_= F_REG(f[1]), @@ -744,6 +767,8 @@ static __u64 fp_d_regs[] =3D { {"zihpm", .feature =3D KVM_RISCV_ISA_EXT_ZIHPM, .regs =3D zihpm_regs, .re= gs_n =3D ARRAY_SIZE(zihpm_regs),} #define AIA_REGS_SUBLIST \ {"aia", .feature =3D KVM_RISCV_ISA_EXT_SSAIA, .regs =3D aia_regs, .regs_n= =3D ARRAY_SIZE(aia_regs),} +#define SMSTATEEN_REGS_SUBLIST \ + {"smstateen", .feature =3D KVM_RISCV_ISA_EXT_SMSTATEEN, .regs =3D smstate= en_regs, .regs_n =3D ARRAY_SIZE(smstateen_regs),} #define FP_F_REGS_SUBLIST \ {"fp_f", .feature =3D KVM_RISCV_ISA_EXT_F, .regs =3D fp_f_regs, \ .regs_n =3D ARRAY_SIZE(fp_f_regs),} @@ -871,6 +896,14 @@ static struct vcpu_reg_list aia_config =3D { }, }; =20 +static struct vcpu_reg_list smstateen_config =3D { + .sublists =3D { + BASE_SUBLIST, + SMSTATEEN_REGS_SUBLIST, + {0}, + }, +}; + static struct vcpu_reg_list fp_f_config =3D { .sublists =3D { BASE_SUBLIST, @@ -903,6 +936,7 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &zifencei_config, &zihpm_config, &aia_config, + &smstateen_config, &fp_f_config, &fp_d_config, }; --=20 2.34.1 From nobody Fri Feb 13 12:28:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E15DCCE7A81 for ; Mon, 25 Sep 2023 13:40:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232118AbjIYNko (ORCPT ); Mon, 25 Sep 2023 09:40:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232354AbjIYNkW (ORCPT ); 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Mon, 25 Sep 2023 06:40:12 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v2 9/9] KVM: riscv: selftests: Add condops extensions to get-reg-list test Date: Mon, 25 Sep 2023 19:08:59 +0530 Message-Id: <20230925133859.1735879-10-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We have a new conditional operations related ISA extensions so let us add these extensions to get-reg-list test. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- .../selftests/kvm/riscv/get-reg-list.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 625118d53b74..cb1bb95b5df2 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -42,12 +42,14 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVNAPOT: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_XVENTANACONDOPS: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: @@ -355,12 +357,14 @@ static const char *isa_ext_id_to_str(__u64 id) KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), + KVM_ISA_EXT_ARR(XVENTANACONDOPS), KVM_ISA_EXT_ARR(ZBA), KVM_ISA_EXT_ARR(ZBB), KVM_ISA_EXT_ARR(ZBS), KVM_ISA_EXT_ARR(ZICBOM), KVM_ISA_EXT_ARR(ZICBOZ), KVM_ISA_EXT_ARR(ZICNTR), + KVM_ISA_EXT_ARR(ZICOND), KVM_ISA_EXT_ARR(ZICSR), KVM_ISA_EXT_ARR(ZIFENCEI), KVM_ISA_EXT_ARR(ZIHINTPAUSE), @@ -632,6 +636,10 @@ static __u64 zicntr_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_IS= A_EXT_ZICNTR, }; =20 +static __u64 zicond_regs[] =3D { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_IS= A_EXT_ZICOND, +}; + static __u64 zicsr_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_IS= A_EXT_ZICSR, }; @@ -644,6 +652,10 @@ static __u64 zihpm_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_IS= A_EXT_ZIHPM, }; =20 +static __u64 xventanacondops_regs[] =3D { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_IS= A_EXT_XVENTANACONDOPS, +}; + static __u64 aia_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CS= R_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CS= R_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1), @@ -759,12 +771,16 @@ static __u64 fp_d_regs[] =3D { {"zbs", .feature =3D KVM_RISCV_ISA_EXT_ZBS, .regs =3D zbs_regs, .regs_n = =3D ARRAY_SIZE(zbs_regs),} #define ZICNTR_REGS_SUBLIST \ {"zicntr", .feature =3D KVM_RISCV_ISA_EXT_ZICNTR, .regs =3D zicntr_regs, = .regs_n =3D ARRAY_SIZE(zicntr_regs),} +#define ZICOND_REGS_SUBLIST \ + {"zicond", .feature =3D KVM_RISCV_ISA_EXT_ZICOND, .regs =3D zicond_regs, = .regs_n =3D ARRAY_SIZE(zicond_regs),} #define ZICSR_REGS_SUBLIST \ {"zicsr", .feature =3D KVM_RISCV_ISA_EXT_ZICSR, .regs =3D zicsr_regs, .re= gs_n =3D ARRAY_SIZE(zicsr_regs),} #define ZIFENCEI_REGS_SUBLIST \ {"zifencei", .feature =3D KVM_RISCV_ISA_EXT_ZIFENCEI, .regs =3D zifencei_= regs, .regs_n =3D ARRAY_SIZE(zifencei_regs),} #define ZIHPM_REGS_SUBLIST \ {"zihpm", .feature =3D KVM_RISCV_ISA_EXT_ZIHPM, .regs =3D zihpm_regs, .re= gs_n =3D ARRAY_SIZE(zihpm_regs),} +#define XVENTANACONDOPS_REGS_SUBLIST \ + {"xventanacondops", .feature =3D KVM_RISCV_ISA_EXT_XVENTANACONDOPS, .regs= =3D xventanacondops_regs, .regs_n =3D ARRAY_SIZE(xventanacondops_regs),} #define AIA_REGS_SUBLIST \ {"aia", .feature =3D KVM_RISCV_ISA_EXT_SSAIA, .regs =3D aia_regs, .regs_n= =3D ARRAY_SIZE(aia_regs),} #define SMSTATEEN_REGS_SUBLIST \ @@ -864,6 +880,14 @@ static struct vcpu_reg_list zicntr_config =3D { }, }; =20 +static struct vcpu_reg_list zicond_config =3D { + .sublists =3D { + BASE_SUBLIST, + ZICOND_REGS_SUBLIST, + {0}, + }, +}; + static struct vcpu_reg_list zicsr_config =3D { .sublists =3D { BASE_SUBLIST, @@ -888,6 +912,14 @@ static struct vcpu_reg_list zihpm_config =3D { }, }; =20 +static struct vcpu_reg_list xventanacondops_config =3D { + .sublists =3D { + BASE_SUBLIST, + XVENTANACONDOPS_REGS_SUBLIST, + {0}, + }, +}; + static struct vcpu_reg_list aia_config =3D { .sublists =3D { BASE_SUBLIST, @@ -932,9 +964,11 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &zbb_config, &zbs_config, &zicntr_config, + &zicond_config, &zicsr_config, &zifencei_config, &zihpm_config, + &xventanacondops_config, &aia_config, &smstateen_config, &fp_f_config, --=20 2.34.1