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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id y5-20020a62b505000000b0068ffb8da107sm7349833pfe.212.2023.09.25.00.03.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 00:03:03 -0700 (PDT) From: Jacky Huang To: a.zummo@towertech.it, alexandre.belloni@bootlin.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mjchen@nuvoton.com, schung@nuvoton.com, Jacky Huang , Krzysztof Kozlowski Subject: [PATCH v4 1/3] dt-bindings: rtc: Add Nuvoton ma35d1 rtc Date: Mon, 25 Sep 2023 07:02:49 +0000 Message-Id: <20230925070251.28-2-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230925070251.28-1-ychuang570808@gmail.com> References: <20230925070251.28-1-ychuang570808@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jacky Huang Add documentation describing the Nuvoton ma35d1 rtc controller. Signed-off-by: Jacky Huang Reviewed-by: Krzysztof Kozlowski --- .../bindings/rtc/nuvoton,ma35d1-rtc.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/nuvoton,ma35d1-rt= c.yaml diff --git a/Documentation/devicetree/bindings/rtc/nuvoton,ma35d1-rtc.yaml = b/Documentation/devicetree/bindings/rtc/nuvoton,ma35d1-rtc.yaml new file mode 100644 index 000000000000..5e4ade803eed --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nuvoton,ma35d1-rtc.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nuvoton,ma35d1-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Real Time Clock + +maintainers: + - Min-Jen Chen + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + enum: + - nuvoton,ma35d1-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + rtc@40410000 { + compatible =3D "nuvoton,ma35d1-rtc"; + reg =3D <0x40410000 0x200>; + interrupts =3D ; + clocks =3D <&clk RTC_GATE>; + }; + +... --=20 2.34.1 From nobody Wed Dec 17 08:53:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 575DECE7A81 for ; Mon, 25 Sep 2023 07:03:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232424AbjIYHDY (ORCPT ); Mon, 25 Sep 2023 03:03:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232348AbjIYHDN (ORCPT ); Mon, 25 Sep 2023 03:03:13 -0400 Received: from mail-oi1-x233.google.com (mail-oi1-x233.google.com [IPv6:2607:f8b0:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0CACC6; Mon, 25 Sep 2023 00:03:06 -0700 (PDT) Received: by mail-oi1-x233.google.com with SMTP id 5614622812f47-3ae0b0e9a68so3795146b6e.0; Mon, 25 Sep 2023 00:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695625386; x=1696230186; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WDGT67Q+ic1nejZuLGS46+I/MVwpubEr1pR0ugjy0IU=; b=G1QMWT8JVjav9cfYKo6W4V9tEiTFM677khgXsdb+3DmD9KyzoETpoYU4mhMWez8FZd /WGYQ1HHFvTgToS5UsraZC9zPlgbaOmcxjpa8897j9itIJ46lW7aCHtnhv/URg2Q8hw1 vB29FBYcjM7yo1iPnwPqiaB0bnxF08LrHlWDExY3XVpuJeGiD65Vzau5qbMrKtVyt+uP sWgbQuiYQauNlyCaoNlRvt1ugu5WFPI4Cpw8acbgrOhj0NipzfLlnz14rMHR5CV5nM19 fYn949jdChMJMaREPz4brtWw/rXl/v5VselSoU5szDahuj6t/ITVi8wRXqI43wJ3/cgw yqyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695625386; x=1696230186; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WDGT67Q+ic1nejZuLGS46+I/MVwpubEr1pR0ugjy0IU=; b=Q/3QGCC7SDPQHUho7wdvRroFugD97l9t/kyh/FpEPM7WNW2TTfBeoHpu+gevTASJCL 19aKev9BpUSnWQAaaYCxplfYYM/ik4h5qhCPpcnceloz19HCEUhrYO30BmceQn3nMo5s a+gR90JPh4kPkJS++pONSObpiHf2wCuiLw5+Fh9YNfUDMSZmE3dhGyP0p9t627wX0p4V ryR6oo9eWahKR6p+k68kmmhrAgkYodzDyAi/RSjzGQly0sJdqQ+gS6hc1tuZ/u60deBD xwWfwDwt1Unexa8YBKGCxrIMR9L1w4GRHrBILkmTpb01Y5ou+CwpOn+YSLQMHqPEb+4K hJ8A== X-Gm-Message-State: AOJu0Yxeek0diHasJm3rKK/5pJlt9dCgu8Q/n7F726XAqd4bwoveHgm7 8HbQnqQY7b/ryZCFnVywYBI= X-Google-Smtp-Source: AGHT+IGuIf5mBPt88+M6/YIuuNJKLE8C/47l0VkV0khzucuV5WQH4sTDrzNExeLrUZwNC2wFVnVfUg== X-Received: by 2002:a05:6808:23cc:b0:3ad:fcd5:3dd6 with SMTP id bq12-20020a05680823cc00b003adfcd53dd6mr9828065oib.13.1695625385867; Mon, 25 Sep 2023 00:03:05 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id y5-20020a62b505000000b0068ffb8da107sm7349833pfe.212.2023.09.25.00.03.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 00:03:05 -0700 (PDT) From: Jacky Huang To: a.zummo@towertech.it, alexandre.belloni@bootlin.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mjchen@nuvoton.com, schung@nuvoton.com, Jacky Huang Subject: [PATCH v4 2/3] arm64: dts: nuvoton: Add rtc for ma35d1 Date: Mon, 25 Sep 2023 07:02:50 +0000 Message-Id: <20230925070251.28-3-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230925070251.28-1-ychuang570808@gmail.com> References: <20230925070251.28-1-ychuang570808@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jacky Huang Add rtc controller support to the dtsi of ma35d1 SoC and enable rtc on SOM and IoT boards. Signed-off-by: Jacky Huang --- arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts | 4 ++++ arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts | 4 ++++ arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 8 ++++++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts b/arch/arm64/b= oot/dts/nuvoton/ma35d1-iot-512m.dts index b89e2be6abae..b3be4331abcf 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts @@ -54,3 +54,7 @@ &clk { "integer", "integer"; }; + +&rtc { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/b= oot/dts/nuvoton/ma35d1-som-256m.dts index a1ebddecb7f8..9858788a589c 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -54,3 +54,7 @@ &clk { "integer", "integer"; }; + +&rtc { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/= nuvoton/ma35d1.dtsi index 781cdae566a0..394395bfd3ae 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -95,6 +95,14 @@ clk: clock-controller@40460200 { clocks =3D <&clk_hxt>; }; =20 + rtc: rtc@40410000 { + compatible =3D "nuvoton,ma35d1-rtc"; + reg =3D <0x0 0x40410000 0x0 0x200>; + interrupts =3D ; + clocks =3D <&clk RTC_GATE>; + status =3D "disabled"; + }; + uart0: serial@40700000 { compatible =3D "nuvoton,ma35d1-uart"; reg =3D <0x0 0x40700000 0x0 0x100>; --=20 2.34.1 From nobody Wed Dec 17 08:53:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CC18CE7A89 for ; Mon, 25 Sep 2023 07:03:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232401AbjIYHDW (ORCPT ); Mon, 25 Sep 2023 03:03:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232355AbjIYHDQ (ORCPT ); Mon, 25 Sep 2023 03:03:16 -0400 Received: from mail-ot1-x331.google.com (mail-ot1-x331.google.com [IPv6:2607:f8b0:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10425B8; Mon, 25 Sep 2023 00:03:09 -0700 (PDT) Received: by mail-ot1-x331.google.com with SMTP id 46e09a7af769-6bdcbde9676so3922633a34.3; Mon, 25 Sep 2023 00:03:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695625388; x=1696230188; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vHhaL5m4pKA7+OJ/gcfrIM4dCYgUutLL3dqd1BkNZ1c=; b=E4FXoB1R+IHhwwpxavAHXSayQF6vse2H/xMMrlGnhtC7W/ePsz0qTr8SqLzHifagsF FRBzJQrAWUWuB7RlOwhbMbHr2bOShTxq7rEfUh9ZhOm3IHkuVAs+R+gB6mTOTj1ePUuf u9MhSt285Adjai2nJRDr9Xcn60Bqjiu3uHXOpaP+X6SC1OLw5wBQdZCKD1W6Osg/nbit gHgZ3sqMOdZEyzzdsz9ZRUi5OsK23tPvXHu1+on69s7F/VMbOQWAMtuw7Sz263/Mt4FG QcDYvSD8Uywr6WoO19UARJw7kMcBgET5/d+B96Hm2UU/x2d3uaCq/kmHbdIJykOYoHwy ZfBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695625388; x=1696230188; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vHhaL5m4pKA7+OJ/gcfrIM4dCYgUutLL3dqd1BkNZ1c=; b=txhy3PXE11t/4hjBzYVGfDlTAVNY8/MVxHiqI9bxvGP52WUbECOxo7Z+SOhlCg1DOt iA1q2aoujo1zIrIBw3b2Ou+H2qofq57YhXSY3XuXpnAiQiRlnI+FB6+kQSurV/xEqMW8 7VXTWXS0lPN4SWyZ6Ib1DYpDrtwEiNjgPjH9agCw9C2+E9XQmaix6Dm/D1V2EcdrIdZS 0wEbMCZPEor1kXpK6yrIAu3C2J6b0Rv8S/G4/EI6Q4oBT1hP1zSoAmGBwd6qrBUvZJ2f F0aRM1BHBFKDiB2SmlFnfxFZjMJ61UCW/1/nj3BdjWpu1hoRE9Jg+2JatKdpDjMHvIc0 OBdw== X-Gm-Message-State: AOJu0Yww9ohB7aHrexvhZKUaOHTf4smd6aL77uwY/V8gsgATGkoROEKC pgzviU4yDSG0ZOMc4IbckSImiMlgbKo= X-Google-Smtp-Source: AGHT+IH7ntprxS8kSVOpW37L1aIJAyRfN6R5YNyj8ToGfmfTjwHFm9YiSb7yZ3cor7GMm7fMF2lOFw== X-Received: by 2002:a05:6358:9989:b0:142:fb84:92e6 with SMTP id j9-20020a056358998900b00142fb8492e6mr9007560rwb.9.1695625388117; Mon, 25 Sep 2023 00:03:08 -0700 (PDT) Received: from a28aa0606c51.. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id y5-20020a62b505000000b0068ffb8da107sm7349833pfe.212.2023.09.25.00.03.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 00:03:07 -0700 (PDT) From: Jacky Huang To: a.zummo@towertech.it, alexandre.belloni@bootlin.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mjchen@nuvoton.com, schung@nuvoton.com, Jacky Huang Subject: [PATCH v4 3/3] rtc: Add driver for Nuvoton ma35d1 rtc controller Date: Mon, 25 Sep 2023 07:02:51 +0000 Message-Id: <20230925070251.28-4-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230925070251.28-1-ychuang570808@gmail.com> References: <20230925070251.28-1-ychuang570808@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jacky Huang The ma35d1 rtc controller provides real-time and calendar messaging capabilities. It supports programmable time tick and alarm match interrupts. The time and calendar messages are expressed in BCD format. This driver supports the built-in rtc controller of the ma35d1. It enables setting and reading the rtc time and configuring and reading the rtc alarm. Signed-off-by: Jacky Huang --- drivers/rtc/Kconfig | 11 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-ma35d1.c | 324 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 336 insertions(+) create mode 100644 drivers/rtc/rtc-ma35d1.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index d7502433c78a..0615b2831273 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1930,6 +1930,17 @@ config RTC_DRV_TI_K3 This driver can also be built as a module, if so, the module will be called "rtc-ti-k3". =20 +config RTC_DRV_MA35D1 + tristate "Nuvoton MA35D1 RTC" + depends on ARCH_MA35 || COMPILE_TEST + select REGMAP_MMIO + help + If you say yes here you get support for the Nuvoton MA35D1 + On-Chip Real Time Clock. + + This driver can also be built as a module, if so, the module + will be called "rtc-ma35d1". + comment "HID Sensor RTC drivers" =20 config RTC_DRV_HID_SENSOR_TIME diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index fd209883ee2e..763c9cb5dde1 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -88,6 +88,7 @@ obj-$(CONFIG_RTC_DRV_M41T94) +=3D rtc-m41t94.o obj-$(CONFIG_RTC_DRV_M48T35) +=3D rtc-m48t35.o obj-$(CONFIG_RTC_DRV_M48T59) +=3D rtc-m48t59.o obj-$(CONFIG_RTC_DRV_M48T86) +=3D rtc-m48t86.o +obj-$(CONFIG_RTC_DRV_MA35D1) +=3D rtc-ma35d1.o obj-$(CONFIG_RTC_DRV_MAX6900) +=3D rtc-max6900.o obj-$(CONFIG_RTC_DRV_MAX6902) +=3D rtc-max6902.o obj-$(CONFIG_RTC_DRV_MAX6916) +=3D rtc-max6916.o diff --git a/drivers/rtc/rtc-ma35d1.c b/drivers/rtc/rtc-ma35d1.c new file mode 100644 index 000000000000..07c9a083a9d5 --- /dev/null +++ b/drivers/rtc/rtc-ma35d1.c @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RTC driver for Nuvoton MA35D1 + * + * Copyright (C) 2023 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* MA35D1 RTC Control Registers */ +#define MA35_REG_RTC_INIT 0x00 +#define MA35_REG_RTC_SINFASTS 0x04 +#define MA35_REG_RTC_FREQADJ 0x08 +#define MA35_REG_RTC_TIME 0x0c +#define MA35_REG_RTC_CAL 0x10 +#define MA35_REG_RTC_CLKFMT 0x14 +#define MA35_REG_RTC_WEEKDAY 0x18 +#define MA35_REG_RTC_TALM 0x1c +#define MA35_REG_RTC_CALM 0x20 +#define MA35_REG_RTC_LEAPYEAR 0x24 +#define MA35_REG_RTC_INTEN 0x28 +#define MA35_REG_RTC_INTSTS 0x2c + +/* register MA35_REG_RTC_INIT */ +#define RTC_INIT_ACTIVE BIT(0) +#define RTC_INIT_MAGIC_CODE 0xa5eb1357 + +/* register MA35_REG_RTC_CLKFMT */ +#define RTC_CLKFMT_24HEN BIT(0) +#define RTC_CLKFMT_DCOMPEN BIT(16) + +/* register MA35_REG_RTC_INTEN */ +#define RTC_INTEN_ALMIEN BIT(0) +#define RTC_INTEN_UIEN BIT(1) +#define RTC_INTEN_CLKFIEN BIT(24) +#define RTC_INTEN_CLKSTIEN BIT(25) + +/* register MA35_REG_RTC_INTSTS */ +#define RTC_INTSTS_ALMIF BIT(0) +#define RTC_INTSTS_UIF BIT(1) +#define RTC_INTSTS_CLKFIF BIT(24) +#define RTC_INTSTS_CLKSTIF BIT(25) + +#define RTC_INIT_TIMEOUT 250 + +struct ma35_rtc { + int irq_num; + void __iomem *rtc_reg; + struct rtc_device *rtcdev; +}; + +static u32 rtc_reg_read(struct ma35_rtc *p, u32 offset) +{ + return __raw_readl(p->rtc_reg + offset); +} + +static inline void rtc_reg_write(struct ma35_rtc *p, u32 offset, u32 value) +{ + __raw_writel(value, p->rtc_reg + offset); +} + +static irqreturn_t ma35d1_rtc_interrupt(int irq, void *data) +{ + struct ma35_rtc *rtc =3D (struct ma35_rtc *)data; + unsigned long events =3D 0, rtc_irq; + + rtc_irq =3D rtc_reg_read(rtc, MA35_REG_RTC_INTSTS); + + if (rtc_irq & RTC_INTSTS_ALMIF) { + rtc_reg_write(rtc, MA35_REG_RTC_INTSTS, RTC_INTSTS_ALMIF); + events |=3D RTC_AF | RTC_IRQF; + } + + if (rtc_irq & RTC_INTSTS_UIF) { + rtc_reg_write(rtc, MA35_REG_RTC_INTSTS, RTC_INTSTS_UIF); + events |=3D RTC_UF | RTC_IRQF; + } + + rtc_update_irq(rtc->rtcdev, 1, events); + + return IRQ_HANDLED; +} + +static int ma35d1_rtc_init(struct ma35_rtc *rtc, u32 ms_timeout) +{ + const unsigned long timeout =3D jiffies + msecs_to_jiffies(ms_timeout); + + do { + if (rtc_reg_read(rtc, MA35_REG_RTC_INIT) & RTC_INIT_ACTIVE) + return 0; + + rtc_reg_write(rtc, MA35_REG_RTC_INIT, RTC_INIT_MAGIC_CODE); + + mdelay(1); + + } while (time_before(jiffies, timeout)); + + return -ETIMEDOUT; +} + +static int ma35d1_alarm_irq_enable(struct device *dev, u32 enabled) +{ + struct ma35_rtc *rtc =3D dev_get_drvdata(dev); + u32 reg_ien; + + reg_ien =3D rtc_reg_read(rtc, MA35_REG_RTC_INTEN); + + if (enabled) + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, reg_ien | RTC_INTEN_ALMIEN); + else + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, reg_ien & ~RTC_INTEN_ALMIEN); + + return 0; +} + +static int ma35d1_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct ma35_rtc *rtc =3D dev_get_drvdata(dev); + u32 time, cal, wday; + + do { + time =3D rtc_reg_read(rtc, MA35_REG_RTC_TIME); + cal =3D rtc_reg_read(rtc, MA35_REG_RTC_CAL); + wday =3D rtc_reg_read(rtc, MA35_REG_RTC_WEEKDAY); + } while (time !=3D rtc_reg_read(rtc, MA35_REG_RTC_TIME) || + cal !=3D rtc_reg_read(rtc, MA35_REG_RTC_CAL)); + + tm->tm_mday =3D bcd2bin(cal >> 0); + tm->tm_wday =3D wday; + tm->tm_mon =3D bcd2bin(cal >> 8); + tm->tm_mon =3D tm->tm_mon - 1; + tm->tm_year =3D bcd2bin(cal >> 16) + 100; + + tm->tm_sec =3D bcd2bin(time >> 0); + tm->tm_min =3D bcd2bin(time >> 8); + tm->tm_hour =3D bcd2bin(time >> 16); + + return rtc_valid_tm(tm); +} + +static int ma35d1_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct ma35_rtc *rtc =3D dev_get_drvdata(dev); + u32 val; + + val =3D bin2bcd(tm->tm_mday) << 0 | bin2bcd(tm->tm_mon + 1) << 8 | + bin2bcd(tm->tm_year - 100) << 16; + rtc_reg_write(rtc, MA35_REG_RTC_CAL, val); + + val =3D bin2bcd(tm->tm_sec) << 0 | bin2bcd(tm->tm_min) << 8 | + bin2bcd(tm->tm_hour) << 16; + rtc_reg_write(rtc, MA35_REG_RTC_TIME, val); + + val =3D tm->tm_wday; + rtc_reg_write(rtc, MA35_REG_RTC_WEEKDAY, val); + + return 0; +} + +static int ma35d1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *al= rm) +{ + struct ma35_rtc *rtc =3D dev_get_drvdata(dev); + u32 talm, calm; + + talm =3D rtc_reg_read(rtc, MA35_REG_RTC_TALM); + calm =3D rtc_reg_read(rtc, MA35_REG_RTC_CALM); + + alrm->time.tm_mday =3D bcd2bin(calm >> 0); + alrm->time.tm_mon =3D bcd2bin(calm >> 8); + alrm->time.tm_mon =3D alrm->time.tm_mon - 1; + + alrm->time.tm_year =3D bcd2bin(calm >> 16) + 100; + + alrm->time.tm_sec =3D bcd2bin(talm >> 0); + alrm->time.tm_min =3D bcd2bin(talm >> 8); + alrm->time.tm_hour =3D bcd2bin(talm >> 16); + + return rtc_valid_tm(&alrm->time); +} + +static int ma35d1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alr= m) +{ + struct ma35_rtc *rtc =3D dev_get_drvdata(dev); + unsigned long val; + + val =3D bin2bcd(alrm->time.tm_mday) << 0 | bin2bcd(alrm->time.tm_mon + 1)= << 8 | + bin2bcd(alrm->time.tm_year - 100) << 16; + rtc_reg_write(rtc, MA35_REG_RTC_CALM, val); + + val =3D bin2bcd(alrm->time.tm_sec) << 0 | bin2bcd(alrm->time.tm_min) << 8= | + bin2bcd(alrm->time.tm_hour) << 16; + rtc_reg_write(rtc, MA35_REG_RTC_TALM, val); + + ma35d1_alarm_irq_enable(dev, alrm->enabled); + + return 0; +} + +static const struct rtc_class_ops ma35d1_rtc_ops =3D { + .read_time =3D ma35d1_rtc_read_time, + .set_time =3D ma35d1_rtc_set_time, + .read_alarm =3D ma35d1_rtc_read_alarm, + .set_alarm =3D ma35d1_rtc_set_alarm, + .alarm_irq_enable =3D ma35d1_alarm_irq_enable, +}; + +static int ma35d1_rtc_probe(struct platform_device *pdev) +{ + struct ma35_rtc *rtc; + struct clk *clk; + u32 regval; + int ret; + + rtc =3D devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + if (!rtc) + return -ENOMEM; + + rtc->rtc_reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rtc->rtc_reg)) + return PTR_ERR(rtc->rtc_reg); + + clk =3D of_clk_get(pdev->dev.of_node, 0); + if (IS_ERR(clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk), "failed to find rtc clock= \n"); + + ret =3D clk_prepare_enable(clk); + if (ret) + return ret; + + if (!(rtc_reg_read(rtc, MA35_REG_RTC_INIT) & RTC_INIT_ACTIVE)) { + ret =3D ma35d1_rtc_init(rtc, RTC_INIT_TIMEOUT); + if (ret) + return dev_err_probe(&pdev->dev, ret, "rtc init failed\n"); + } + + rtc->irq_num =3D platform_get_irq(pdev, 0); + + ret =3D devm_request_irq(&pdev->dev, rtc->irq_num, ma35d1_rtc_interrupt, + IRQF_NO_SUSPEND, "ma35d1rtc", rtc); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to request rtc irq\n"); + + platform_set_drvdata(pdev, rtc); + + device_init_wakeup(&pdev->dev, true); + + rtc->rtcdev =3D devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rtc->rtcdev)) + return PTR_ERR(rtc->rtcdev); + + rtc->rtcdev->ops =3D &ma35d1_rtc_ops; + rtc->rtcdev->range_min =3D RTC_TIMESTAMP_BEGIN_2000; + rtc->rtcdev->range_max =3D RTC_TIMESTAMP_END_2099; + + ret =3D devm_rtc_register_device(rtc->rtcdev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to register rtc device\n"); + + regval =3D rtc_reg_read(rtc, MA35_REG_RTC_INTEN); + regval |=3D RTC_INTEN_UIEN; + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, regval); + + return 0; +} + +static int ma35d1_rtc_suspend(struct platform_device *pdev, pm_message_t s= tate) +{ + struct ma35_rtc *rtc =3D platform_get_drvdata(pdev); + u32 regval; + + if (device_may_wakeup(&pdev->dev)) + enable_irq_wake(rtc->irq_num); + + regval =3D rtc_reg_read(rtc, MA35_REG_RTC_INTEN); + regval &=3D ~RTC_INTEN_UIEN; + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, regval); + + return 0; +} + +static int ma35d1_rtc_resume(struct platform_device *pdev) +{ + struct ma35_rtc *rtc =3D platform_get_drvdata(pdev); + u32 regval; + + if (device_may_wakeup(&pdev->dev)) + disable_irq_wake(rtc->irq_num); + + regval =3D rtc_reg_read(rtc, MA35_REG_RTC_INTEN); + regval |=3D RTC_INTEN_UIEN; + rtc_reg_write(rtc, MA35_REG_RTC_INTEN, regval); + + return 0; +} + +static const struct of_device_id ma35d1_rtc_of_match[] =3D { + { .compatible =3D "nuvoton,ma35d1-rtc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ma35d1_rtc_of_match); + +static struct platform_driver ma35d1_rtc_driver =3D { + .suspend =3D ma35d1_rtc_suspend, + .resume =3D ma35d1_rtc_resume, + .probe =3D ma35d1_rtc_probe, + .driver =3D { + .name =3D "rtc-ma35d1", + .of_match_table =3D ma35d1_rtc_of_match, + }, +}; + +module_platform_driver(ma35d1_rtc_driver); + +MODULE_AUTHOR("Ming-Jen Chen "); +MODULE_DESCRIPTION("MA35D1 RTC driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1