From nobody Fri Feb 13 12:42:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC8BECE7A8B for ; Mon, 25 Sep 2023 02:11:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231703AbjIYCLd (ORCPT ); Sun, 24 Sep 2023 22:11:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230360AbjIYCLb (ORCPT ); Sun, 24 Sep 2023 22:11:31 -0400 Received: from out-198.mta1.migadu.com (out-198.mta1.migadu.com [95.215.58.198]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64E0EEE for ; Sun, 24 Sep 2023 19:11:24 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1695607882; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x5tMUp6nQxBrhWd3iRz7QzLsI7eW1vyNH67Y+6fzlTo=; b=GoJ0RtsSIsmcJFbakh3Qeo5ead6HnP2cV/+60l0w8vj2EJCxW4NTa2HYmuz3ZTlySkj7Uj tUW6cDDlxMItLUshxsTFvSt3M+diGg/ZWahCJsQQctPycDzHVmqaFNAt//DMau2U/Fk4J8 8RqVE4TuqQPuioRJIFFoxf2ne6lDL0/gylBDU77cwe7zn8TWY83igqBrLiXB0mub+wUeIg zE2IgXUVTTIPX7s+2qC0PEsr4HrMB1FF1ahDZlPESEuAO2Dxcw0fAZDcy40fJ9pRs+qwKb RRR8qiyLeKPL6mC8mP08rULz5Cxw53POKz1i2AECR09uU1GVdQnMcGCrEVSEQQ== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Heiko Stuebner , Chris Morgan , Jagan Teki , John Watts , Paul Cercueil , Christophe Branchereau , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v3 1/7] drm/panel: nv3052c: Document known register names Date: Mon, 25 Sep 2023 12:10:52 +1000 Message-ID: <20230925021059.451019-2-contact@jookia.org> In-Reply-To: <20230925021059.451019-1-contact@jookia.org> References: <20230925021059.451019-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Many of these registers have a known name in the public datasheet. Document them as comments for reference. Signed-off-by: John Watts Reviewed-by: Jessica Zhang --- .../gpu/drm/panel/panel-newvision-nv3052c.c | 261 +++++++++--------- 1 file changed, 132 insertions(+), 129 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 71e57de6d8b2..589431523ce7 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -42,9 +42,9 @@ struct nv3052c_reg { }; =20 static const struct nv3052c_reg nv3052c_panel_regs[] =3D { - { 0xff, 0x30 }, - { 0xff, 0x52 }, - { 0xff, 0x01 }, + // EXTC Command set enable, select page 1 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, + // Mostly unknown registers { 0xe3, 0x00 }, { 0x40, 0x00 }, { 0x03, 0x40 }, @@ -62,15 +62,15 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = =3D { { 0x25, 0x06 }, { 0x26, 0x14 }, { 0x27, 0x14 }, - { 0x38, 0xcc }, - { 0x39, 0xd7 }, - { 0x3a, 0x4a }, + { 0x38, 0xcc }, // VCOM_ADJ1 + { 0x39, 0xd7 }, // VCOM_ADJ2 + { 0x3a, 0x4a }, // VCOM_ADJ3 { 0x28, 0x40 }, { 0x29, 0x01 }, { 0x2a, 0xdf }, { 0x49, 0x3c }, - { 0x91, 0x77 }, - { 0x92, 0x77 }, + { 0x91, 0x77 }, // EXTPW_CTRL2 + { 0x92, 0x77 }, // EXTPW_CTRL3 { 0xa0, 0x55 }, { 0xa1, 0x50 }, { 0xa4, 0x9c }, @@ -94,123 +94,126 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = =3D { { 0xb8, 0x26 }, { 0xf0, 0x00 }, { 0xf6, 0xc0 }, - { 0xff, 0x30 }, - { 0xff, 0x52 }, - { 0xff, 0x02 }, - { 0xb0, 0x0b }, - { 0xb1, 0x16 }, - { 0xb2, 0x17 }, - { 0xb3, 0x2c }, - { 0xb4, 0x32 }, - { 0xb5, 0x3b }, - { 0xb6, 0x29 }, - { 0xb7, 0x40 }, - { 0xb8, 0x0d }, - { 0xb9, 0x05 }, - { 0xba, 0x12 }, - { 0xbb, 0x10 }, - { 0xbc, 0x12 }, - { 0xbd, 0x15 }, - { 0xbe, 0x19 }, - { 0xbf, 0x0e }, - { 0xc0, 0x16 }, - { 0xc1, 0x0a }, - { 0xd0, 0x0c }, - { 0xd1, 0x17 }, - { 0xd2, 0x14 }, - { 0xd3, 0x2e }, - { 0xd4, 0x32 }, - { 0xd5, 0x3c }, - { 0xd6, 0x22 }, - { 0xd7, 0x3d }, - { 0xd8, 0x0d }, - { 0xd9, 0x07 }, - { 0xda, 0x13 }, - { 0xdb, 0x13 }, - { 0xdc, 0x11 }, - { 0xdd, 0x15 }, - { 0xde, 0x19 }, - { 0xdf, 0x10 }, - { 0xe0, 0x17 }, - { 0xe1, 0x0a }, - { 0xff, 0x30 }, - { 0xff, 0x52 }, - { 0xff, 0x03 }, - { 0x00, 0x2a }, - { 0x01, 0x2a }, - { 0x02, 0x2a }, - { 0x03, 0x2a }, - { 0x04, 0x61 }, - { 0x05, 0x80 }, - { 0x06, 0xc7 }, - { 0x07, 0x01 }, - { 0x08, 0x03 }, - { 0x09, 0x04 }, - { 0x70, 0x22 }, - { 0x71, 0x80 }, - { 0x30, 0x2a }, - { 0x31, 0x2a }, - { 0x32, 0x2a }, - { 0x33, 0x2a }, - { 0x34, 0x61 }, - { 0x35, 0xc5 }, - { 0x36, 0x80 }, - { 0x37, 0x23 }, - { 0x40, 0x03 }, - { 0x41, 0x04 }, - { 0x42, 0x05 }, - { 0x43, 0x06 }, - { 0x44, 0x11 }, - { 0x45, 0xe8 }, - { 0x46, 0xe9 }, - { 0x47, 0x11 }, - { 0x48, 0xea }, - { 0x49, 0xeb }, - { 0x50, 0x07 }, - { 0x51, 0x08 }, - { 0x52, 0x09 }, - { 0x53, 0x0a }, - { 0x54, 0x11 }, - { 0x55, 0xec }, - { 0x56, 0xed }, - { 0x57, 0x11 }, - { 0x58, 0xef }, - { 0x59, 0xf0 }, - { 0xb1, 0x01 }, - { 0xb4, 0x15 }, - { 0xb5, 0x16 }, - { 0xb6, 0x09 }, - { 0xb7, 0x0f }, - { 0xb8, 0x0d }, - { 0xb9, 0x0b }, - { 0xba, 0x00 }, - { 0xc7, 0x02 }, - { 0xca, 0x17 }, - { 0xcb, 0x18 }, - { 0xcc, 0x0a }, - { 0xcd, 0x10 }, - { 0xce, 0x0e }, - { 0xcf, 0x0c }, - { 0xd0, 0x00 }, - { 0x81, 0x00 }, - { 0x84, 0x15 }, - { 0x85, 0x16 }, - { 0x86, 0x10 }, - { 0x87, 0x0a }, - { 0x88, 0x0c }, - { 0x89, 0x0e }, - { 0x8a, 0x02 }, - { 0x97, 0x00 }, - { 0x9a, 0x17 }, - { 0x9b, 0x18 }, - { 0x9c, 0x0f }, - { 0x9d, 0x09 }, - { 0x9e, 0x0b }, - { 0x9f, 0x0d }, - { 0xa0, 0x01 }, - { 0xff, 0x30 }, - { 0xff, 0x52 }, - { 0xff, 0x02 }, + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Set gray scale voltage to adjust gamma + { 0xb0, 0x0b }, // PGAMVR0 + { 0xb1, 0x16 }, // PGAMVR1 + { 0xb2, 0x17 }, // PGAMVR2 + { 0xb3, 0x2c }, // PGAMVR3 + { 0xb4, 0x32 }, // PGAMVR4 + { 0xb5, 0x3b }, // PGAMVR5 + { 0xb6, 0x29 }, // PGAMPR0 + { 0xb7, 0x40 }, // PGAMPR1 + { 0xb8, 0x0d }, // PGAMPK0 + { 0xb9, 0x05 }, // PGAMPK1 + { 0xba, 0x12 }, // PGAMPK2 + { 0xbb, 0x10 }, // PGAMPK3 + { 0xbc, 0x12 }, // PGAMPK4 + { 0xbd, 0x15 }, // PGAMPK5 + { 0xbe, 0x19 }, // PGAMPK6 + { 0xbf, 0x0e }, // PGAMPK7 + { 0xc0, 0x16 }, // PGAMPK8 + { 0xc1, 0x0a }, // PGAMPK9 + // Set gray scale voltage to adjust gamma + { 0xd0, 0x0c }, // NGAMVR0 + { 0xd1, 0x17 }, // NGAMVR0 + { 0xd2, 0x14 }, // NGAMVR1 + { 0xd3, 0x2e }, // NGAMVR2 + { 0xd4, 0x32 }, // NGAMVR3 + { 0xd5, 0x3c }, // NGAMVR4 + { 0xd6, 0x22 }, // NGAMPR0 + { 0xd7, 0x3d }, // NGAMPR1 + { 0xd8, 0x0d }, // NGAMPK0 + { 0xd9, 0x07 }, // NGAMPK1 + { 0xda, 0x13 }, // NGAMPK2 + { 0xdb, 0x13 }, // NGAMPK3 + { 0xdc, 0x11 }, // NGAMPK4 + { 0xdd, 0x15 }, // NGAMPK5 + { 0xde, 0x19 }, // NGAMPK6 + { 0xdf, 0x10 }, // NGAMPK7 + { 0xe0, 0x17 }, // NGAMPK8 + { 0xe1, 0x0a }, // NGAMPK9 + // EXTC Command set enable, select page 3 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, + // Set various timing settings + { 0x00, 0x2a }, // GIP_VST_1 + { 0x01, 0x2a }, // GIP_VST_2 + { 0x02, 0x2a }, // GIP_VST_3 + { 0x03, 0x2a }, // GIP_VST_4 + { 0x04, 0x61 }, // GIP_VST_5 + { 0x05, 0x80 }, // GIP_VST_6 + { 0x06, 0xc7 }, // GIP_VST_7 + { 0x07, 0x01 }, // GIP_VST_8 + { 0x08, 0x03 }, // GIP_VST_9 + { 0x09, 0x04 }, // GIP_VST_10 + { 0x70, 0x22 }, // GIP_ECLK1 + { 0x71, 0x80 }, // GIP_ECLK2 + { 0x30, 0x2a }, // GIP_CLK_1 + { 0x31, 0x2a }, // GIP_CLK_2 + { 0x32, 0x2a }, // GIP_CLK_3 + { 0x33, 0x2a }, // GIP_CLK_4 + { 0x34, 0x61 }, // GIP_CLK_5 + { 0x35, 0xc5 }, // GIP_CLK_6 + { 0x36, 0x80 }, // GIP_CLK_7 + { 0x37, 0x23 }, // GIP_CLK_8 + { 0x40, 0x03 }, // GIP_CLKA_1 + { 0x41, 0x04 }, // GIP_CLKA_2 + { 0x42, 0x05 }, // GIP_CLKA_3 + { 0x43, 0x06 }, // GIP_CLKA_4 + { 0x44, 0x11 }, // GIP_CLKA_5 + { 0x45, 0xe8 }, // GIP_CLKA_6 + { 0x46, 0xe9 }, // GIP_CLKA_7 + { 0x47, 0x11 }, // GIP_CLKA_8 + { 0x48, 0xea }, // GIP_CLKA_9 + { 0x49, 0xeb }, // GIP_CLKA_10 + { 0x50, 0x07 }, // GIP_CLKB_1 + { 0x51, 0x08 }, // GIP_CLKB_2 + { 0x52, 0x09 }, // GIP_CLKB_3 + { 0x53, 0x0a }, // GIP_CLKB_4 + { 0x54, 0x11 }, // GIP_CLKB_5 + { 0x55, 0xec }, // GIP_CLKB_6 + { 0x56, 0xed }, // GIP_CLKB_7 + { 0x57, 0x11 }, // GIP_CLKB_8 + { 0x58, 0xef }, // GIP_CLKB_9 + { 0x59, 0xf0 }, // GIP_CLKB_10 + // Map internal GOA signals to GOA output pad + { 0xb1, 0x01 }, // PANELD2U2 + { 0xb4, 0x15 }, // PANELD2U5 + { 0xb5, 0x16 }, // PANELD2U6 + { 0xb6, 0x09 }, // PANELD2U7 + { 0xb7, 0x0f }, // PANELD2U8 + { 0xb8, 0x0d }, // PANELD2U9 + { 0xb9, 0x0b }, // PANELD2U10 + { 0xba, 0x00 }, // PANELD2U11 + { 0xc7, 0x02 }, // PANELD2U24 + { 0xca, 0x17 }, // PANELD2U27 + { 0xcb, 0x18 }, // PANELD2U28 + { 0xcc, 0x0a }, // PANELD2U29 + { 0xcd, 0x10 }, // PANELD2U30 + { 0xce, 0x0e }, // PANELD2U31 + { 0xcf, 0x0c }, // PANELD2U32 + { 0xd0, 0x00 }, // PANELD2U33 + // Map internal GOA signals to GOA output pad + { 0x81, 0x00 }, // PANELU2D2 + { 0x84, 0x15 }, // PANELU2D5 + { 0x85, 0x16 }, // PANELU2D6 + { 0x86, 0x10 }, // PANELU2D7 + { 0x87, 0x0a }, // PANELU2D8 + { 0x88, 0x0c }, // PANELU2D9 + { 0x89, 0x0e }, // PANELU2D10 + { 0x8a, 0x02 }, // PANELU2D11 + { 0x97, 0x00 }, // PANELU2D24 + { 0x9a, 0x17 }, // PANELU2D27 + { 0x9b, 0x18 }, // PANELU2D28 + { 0x9c, 0x0f }, // PANELU2D29 + { 0x9d, 0x09 }, // PANELU2D30 + { 0x9e, 0x0b }, // PANELU2D31 + { 0x9f, 0x0d }, // PANELU2D32 + { 0xa0, 0x01 }, // PANELU2D33 + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Unknown registers { 0x01, 0x01 }, { 0x02, 0xda }, { 0x03, 0xba }, @@ -227,10 +230,10 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = =3D { { 0x0e, 0x48 }, { 0x0f, 0x38 }, { 0x10, 0x2b }, - { 0xff, 0x30 }, - { 0xff, 0x52 }, - { 0xff, 0x00 }, - { 0x36, 0x0a }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, + // Display Access Control + { 0x36, 0x0a }, // bgr =3D 1, ss =3D 1, gs =3D 0 }; =20 static inline struct nv3052c *to_nv3052c(struct drm_panel *panel) --=20 2.42.0 From nobody Fri Feb 13 12:42:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46035CE7A8B for ; Mon, 25 Sep 2023 02:11:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231755AbjIYCLl (ORCPT ); Sun, 24 Sep 2023 22:11:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231744AbjIYCLh (ORCPT ); Sun, 24 Sep 2023 22:11:37 -0400 Received: from out-199.mta0.migadu.com (out-199.mta0.migadu.com [IPv6:2001:41d0:1004:224b::c7]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CA2A10C for ; Sun, 24 Sep 2023 19:11:30 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1695607888; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=N/ff6X+NOYVbrocTBpgld9JVVmEwtIn+hGTJSAUql5A=; b=pyJBUWtEPpDCgLUqa9T9Oq1k1KMROSr1qK+/oGDfyLpm7FKlDMkeYcBsjaeuwhqlpzJjO2 81KGKbBqBBEpVfEIb6xk0dg2yjGd58hrLWOtMUogFkT70gVIpPoDIdtymSNYr6lq6mtfB4 IyVdU/6caI9ngzI2b7G0a730EMgk25dTO8+vApYFXgcH41cAl7HfoIBptHVpXW39UVVCi0 HNIdiE96+J5m3GBthxaaZjULKbaQha3VRzubbqOIFZsg1iLr2Lbq/9Ir8iqi42TDCJSt54 AwbRgnWdOHUGi4ZkwcveyH//vprzEu9KzGbCUKWhPD+jjExg5qO1JLZNeOgK5A== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Heiko Stuebner , Chris Morgan , Jagan Teki , John Watts , Paul Cercueil , Christophe Branchereau , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v3 2/7] drm/panel: nv3052c: Add SPI device IDs Date: Mon, 25 Sep 2023 12:10:53 +1000 Message-ID: <20230925021059.451019-3-contact@jookia.org> In-Reply-To: <20230925021059.451019-1-contact@jookia.org> References: <20230925021059.451019-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SPI drivers needs their own list of compatible device IDs in order for automatic module loading to work. Add those for this driver. Signed-off-by: John Watts Reviewed-by: Jessica Zhang --- drivers/gpu/drm/panel/panel-newvision-nv3052c.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 589431523ce7..90dea21f9856 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -465,6 +465,12 @@ static const struct nv3052c_panel_info ltk035c5444t_pa= nel_info =3D { .bus_flags =3D DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, }; =20 +static const struct spi_device_id nv3052c_ids[] =3D { + { "ltk035c5444t", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(spi, nv3052c_ids); + static const struct of_device_id nv3052c_of_match[] =3D { { .compatible =3D "leadtek,ltk035c5444t", .data =3D <k035c5444t_panel_i= nfo }, { /* sentinel */ } @@ -476,6 +482,7 @@ static struct spi_driver nv3052c_driver =3D { .name =3D "nv3052c", .of_match_table =3D nv3052c_of_match, }, + .id_table =3D nv3052c_ids, .probe =3D nv3052c_probe, .remove =3D nv3052c_remove, }; --=20 2.42.0 From nobody Fri Feb 13 12:42:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B285CE7A91 for ; Mon, 25 Sep 2023 02:11:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231818AbjIYCLu (ORCPT ); Sun, 24 Sep 2023 22:11:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231777AbjIYCLp (ORCPT ); Sun, 24 Sep 2023 22:11:45 -0400 Received: from out-190.mta0.migadu.com (out-190.mta0.migadu.com [IPv6:2001:41d0:1004:224b::be]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9C6ACF for ; Sun, 24 Sep 2023 19:11:36 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1695607894; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KjYW+FPYn4FtPs/h0Kb7cdF5d1ojhB/ZqlHnYv4SWzY=; b=ADn0fQ3cpdEzqFpU0SrFyxBMlnwPycknXFywWCUBuZub8eXFzYI37a7nYbHGEBfg0aL+AG dllzsq8miBQKzbA+NcAg8elpwh6otvxEPlG/bpw8e9DXseIQlLxwHKqg0jsW8a9eDWoXiV 1kwPcvFDcgR6CVeGpCXnGGAtm7RchLvsBIBr8AvIU9YQnA6DGjK5XrWSmsrG2mPyJdyD0/ 4WSKkHvfVnKz4ysncUjp5mx54ZP7CE0/rih8I8tySHwGmVt4SdGiK3Jurv7aVtVejKaEZU hNOdDm7PQqDNwR9OCBR8r2boGOmpGaOXrRAcLamPBCPzNzJ2MXNPta9ilqsnnQ== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Heiko Stuebner , Chris Morgan , Jagan Teki , John Watts , Paul Cercueil , Christophe Branchereau , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v3 3/7] drm/panel: nv3052c: Allow specifying registers per panel Date: Mon, 25 Sep 2023 12:10:54 +1000 Message-ID: <20230925021059.451019-4-contact@jookia.org> In-Reply-To: <20230925021059.451019-1-contact@jookia.org> References: <20230925021059.451019-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Panel initialization registers are per-display and not tied to the controller itself. Different panels will specify their own registers. Attach the sequences to the panel info struct so future panels can specify their own sequences. Signed-off-by: John Watts Reviewed-by: Jessica Zhang --- .../gpu/drm/panel/panel-newvision-nv3052c.c | 24 ++++++++++++------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 90dea21f9856..382062a79ba8 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -20,11 +20,18 @@ #include #include =20 +struct nv3052c_reg { + u8 cmd; + u8 val; +}; + struct nv3052c_panel_info { const struct drm_display_mode *display_modes; unsigned int num_modes; u16 width_mm, height_mm; u32 bus_format, bus_flags; + const struct nv3052c_reg *panel_regs; + int panel_regs_len; }; =20 struct nv3052c { @@ -36,12 +43,7 @@ struct nv3052c { struct gpio_desc *reset_gpio; }; =20 -struct nv3052c_reg { - u8 cmd; - u8 val; -}; - -static const struct nv3052c_reg nv3052c_panel_regs[] =3D { +static const struct nv3052c_reg ltk035c5444t_panel_regs[] =3D { // EXTC Command set enable, select page 1 { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, // Mostly unknown registers @@ -244,6 +246,8 @@ static inline struct nv3052c *to_nv3052c(struct drm_pan= el *panel) static int nv3052c_prepare(struct drm_panel *panel) { struct nv3052c *priv =3D to_nv3052c(panel); + const struct nv3052c_reg *panel_regs =3D priv->panel_info->panel_regs; + int panel_regs_len =3D priv->panel_info->panel_regs_len; struct mipi_dbi *dbi =3D &priv->dbi; unsigned int i; int err; @@ -260,9 +264,9 @@ static int nv3052c_prepare(struct drm_panel *panel) gpiod_set_value_cansleep(priv->reset_gpio, 0); usleep_range(5000, 20000); =20 - for (i =3D 0; i < ARRAY_SIZE(nv3052c_panel_regs); i++) { - err =3D mipi_dbi_command(dbi, nv3052c_panel_regs[i].cmd, - nv3052c_panel_regs[i].val); + for (i =3D 0; i < panel_regs_len; i++) { + err =3D mipi_dbi_command(dbi, panel_regs[i].cmd, + panel_regs[i].val); =20 if (err) { dev_err(priv->dev, "Unable to set register: %d\n", err); @@ -463,6 +467,8 @@ static const struct nv3052c_panel_info ltk035c5444t_pan= el_info =3D { .height_mm =3D 64, .bus_format =3D MEDIA_BUS_FMT_RGB888_1X24, .bus_flags =3D DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, + .panel_regs =3D ltk035c5444t_panel_regs, + .panel_regs_len =3D ARRAY_SIZE(ltk035c5444t_panel_regs), }; =20 static const struct spi_device_id nv3052c_ids[] =3D { --=20 2.42.0 From nobody Fri Feb 13 12:42:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24E8FCE7A8B for ; Mon, 25 Sep 2023 02:11:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231670AbjIYCL7 (ORCPT ); Sun, 24 Sep 2023 22:11:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231784AbjIYCLu (ORCPT ); Sun, 24 Sep 2023 22:11:50 -0400 Received: from out-194.mta1.migadu.com (out-194.mta1.migadu.com [95.215.58.194]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D244710B for ; Sun, 24 Sep 2023 19:11:42 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1695607900; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mDBen6ub9Ykb7jl/HjRNQUgyV0YEuYq8cczfFJs5XnQ=; b=Kh+KWdi7AK1HWDNx07BNRmmJSU00sK6Dlzs2+gHulIP9FZxdeyNOT2uKVYu5lA6ElOIx+F /HnVUl7VCu/uVlALc/6yGPwnoInn0RNLtm3i3NADBUL/0kyMLBPfxJ74JvAMoYC2KB6XQu R9Pq4FabDS66vA3bQAYBJFTvqdgCIPhYdSOn4uG+eqf3u3NpmsPwa+UR3lfvX3e8+KEyZj jjuw5jt9YLC38rgP2C/1TPrbZr240Q3+O03PeXWNpjzsQ2WZQ+6Q+1KwmM9RDniRFaluVU dgvvX25+L9CzO9wMNNfeAHoJkA4ne+HAJhDiUp1u9T990gSp/GHZfHzcogjZxg== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Heiko Stuebner , Chris Morgan , Jagan Teki , John Watts , Paul Cercueil , Christophe Branchereau , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v3 4/7] drm/panel: nv3052c: Add Fascontek FS035VG158 LCD display Date: Mon, 25 Sep 2023 12:10:55 +1000 Message-ID: <20230925021059.451019-5-contact@jookia.org> In-Reply-To: <20230925021059.451019-1-contact@jookia.org> References: <20230925021059.451019-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This display is extremely similar to the LTK035C5444T, but still has some minor variations in panel initialization. Signed-off-by: John Watts Reviewed-by: Jessica Zhang --- .../gpu/drm/panel/panel-newvision-nv3052c.c | 223 ++++++++++++++++++ 1 file changed, 223 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 382062a79ba8..79f1f67df13c 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -238,6 +238,201 @@ static const struct nv3052c_reg ltk035c5444t_panel_re= gs[] =3D { { 0x36, 0x0a }, // bgr =3D 1, ss =3D 1, gs =3D 0 }; =20 +static const struct nv3052c_reg fs035vg158_panel_regs[] =3D { + // EXTC Command set enable, select page 1 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, + // Mostly unknown registers + { 0xe3, 0x00 }, + { 0x40, 0x00 }, + { 0x03, 0x40 }, + { 0x04, 0x00 }, + { 0x05, 0x03 }, + { 0x08, 0x00 }, + { 0x09, 0x07 }, + { 0x0a, 0x01 }, + { 0x0b, 0x32 }, + { 0x0c, 0x32 }, + { 0x0d, 0x0b }, + { 0x0e, 0x00 }, + { 0x23, 0x20 }, // RGB interface control: DE MODE PCLK-N + { 0x24, 0x0c }, + { 0x25, 0x06 }, + { 0x26, 0x14 }, + { 0x27, 0x14 }, + { 0x38, 0x9c }, //VCOM_ADJ1, different to ltk035c5444t + { 0x39, 0xa7 }, //VCOM_ADJ2, different to ltk035c5444t + { 0x3a, 0x50 }, //VCOM_ADJ3, different to ltk035c5444t + { 0x28, 0x40 }, + { 0x29, 0x01 }, + { 0x2a, 0xdf }, + { 0x49, 0x3c }, + { 0x91, 0x57 }, //EXTPW_CTRL2, different to ltk035c5444t + { 0x92, 0x57 }, //EXTPW_CTRL3, different to ltk035c5444t + { 0xa0, 0x55 }, + { 0xa1, 0x50 }, + { 0xa4, 0x9c }, + { 0xa7, 0x02 }, + { 0xa8, 0x01 }, + { 0xa9, 0x01 }, + { 0xaa, 0xfc }, + { 0xab, 0x28 }, + { 0xac, 0x06 }, + { 0xad, 0x06 }, + { 0xae, 0x06 }, + { 0xaf, 0x03 }, + { 0xb0, 0x08 }, + { 0xb1, 0x26 }, + { 0xb2, 0x28 }, + { 0xb3, 0x28 }, + { 0xb4, 0x03 }, // Unknown, different to ltk035c5444 + { 0xb5, 0x08 }, + { 0xb6, 0x26 }, + { 0xb7, 0x08 }, + { 0xb8, 0x26 }, + { 0xf0, 0x00 }, + { 0xf6, 0xc0 }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Set gray scale voltage to adjust gamma + { 0xb0, 0x0b }, // PGAMVR0 + { 0xb1, 0x16 }, // PGAMVR1 + { 0xb2, 0x17 }, // PGAMVR2 + { 0xb3, 0x2c }, // PGAMVR3 + { 0xb4, 0x32 }, // PGAMVR4 + { 0xb5, 0x3b }, // PGAMVR5 + { 0xb6, 0x29 }, // PGAMPR0 + { 0xb7, 0x40 }, // PGAMPR1 + { 0xb8, 0x0d }, // PGAMPK0 + { 0xb9, 0x05 }, // PGAMPK1 + { 0xba, 0x12 }, // PGAMPK2 + { 0xbb, 0x10 }, // PGAMPK3 + { 0xbc, 0x12 }, // PGAMPK4 + { 0xbd, 0x15 }, // PGAMPK5 + { 0xbe, 0x19 }, // PGAMPK6 + { 0xbf, 0x0e }, // PGAMPK7 + { 0xc0, 0x16 }, // PGAMPK8 + { 0xc1, 0x0a }, // PGAMPK9 + // Set gray scale voltage to adjust gamma + { 0xd0, 0x0c }, // NGAMVR0 + { 0xd1, 0x17 }, // NGAMVR0 + { 0xd2, 0x14 }, // NGAMVR1 + { 0xd3, 0x2e }, // NGAMVR2 + { 0xd4, 0x32 }, // NGAMVR3 + { 0xd5, 0x3c }, // NGAMVR4 + { 0xd6, 0x22 }, // NGAMPR0 + { 0xd7, 0x3d }, // NGAMPR1 + { 0xd8, 0x0d }, // NGAMPK0 + { 0xd9, 0x07 }, // NGAMPK1 + { 0xda, 0x13 }, // NGAMPK2 + { 0xdb, 0x13 }, // NGAMPK3 + { 0xdc, 0x11 }, // NGAMPK4 + { 0xdd, 0x15 }, // NGAMPK5 + { 0xde, 0x19 }, // NGAMPK6 + { 0xdf, 0x10 }, // NGAMPK7 + { 0xe0, 0x17 }, // NGAMPK8 + { 0xe1, 0x0a }, // NGAMPK9 + // EXTC Command set enable, select page 3 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, + // Set various timing settings + { 0x00, 0x2a }, // GIP_VST_1 + { 0x01, 0x2a }, // GIP_VST_2 + { 0x02, 0x2a }, // GIP_VST_3 + { 0x03, 0x2a }, // GIP_VST_4 + { 0x04, 0x61 }, // GIP_VST_5 + { 0x05, 0x80 }, // GIP_VST_6 + { 0x06, 0xc7 }, // GIP_VST_7 + { 0x07, 0x01 }, // GIP_VST_8 + { 0x08, 0x03 }, // GIP_VST_9 + { 0x09, 0x04 }, // GIP_VST_10 + { 0x70, 0x22 }, // GIP_ECLK1 + { 0x71, 0x80 }, // GIP_ECLK2 + { 0x30, 0x2a }, // GIP_CLK_1 + { 0x31, 0x2a }, // GIP_CLK_2 + { 0x32, 0x2a }, // GIP_CLK_3 + { 0x33, 0x2a }, // GIP_CLK_4 + { 0x34, 0x61 }, // GIP_CLK_5 + { 0x35, 0xc5 }, // GIP_CLK_6 + { 0x36, 0x80 }, // GIP_CLK_7 + { 0x37, 0x23 }, // GIP_CLK_8 + { 0x40, 0x03 }, // GIP_CLKA_1 + { 0x41, 0x04 }, // GIP_CLKA_2 + { 0x42, 0x05 }, // GIP_CLKA_3 + { 0x43, 0x06 }, // GIP_CLKA_4 + { 0x44, 0x11 }, // GIP_CLKA_5 + { 0x45, 0xe8 }, // GIP_CLKA_6 + { 0x46, 0xe9 }, // GIP_CLKA_7 + { 0x47, 0x11 }, // GIP_CLKA_8 + { 0x48, 0xea }, // GIP_CLKA_9 + { 0x49, 0xeb }, // GIP_CLKA_10 + { 0x50, 0x07 }, // GIP_CLKB_1 + { 0x51, 0x08 }, // GIP_CLKB_2 + { 0x52, 0x09 }, // GIP_CLKB_3 + { 0x53, 0x0a }, // GIP_CLKB_4 + { 0x54, 0x11 }, // GIP_CLKB_5 + { 0x55, 0xec }, // GIP_CLKB_6 + { 0x56, 0xed }, // GIP_CLKB_7 + { 0x57, 0x11 }, // GIP_CLKB_8 + { 0x58, 0xef }, // GIP_CLKB_9 + { 0x59, 0xf0 }, // GIP_CLKB_10 + // Map internal GOA signals to GOA output pad + { 0xb1, 0x01 }, // PANELD2U2 + { 0xb4, 0x15 }, // PANELD2U5 + { 0xb5, 0x16 }, // PANELD2U6 + { 0xb6, 0x09 }, // PANELD2U7 + { 0xb7, 0x0f }, // PANELD2U8 + { 0xb8, 0x0d }, // PANELD2U9 + { 0xb9, 0x0b }, // PANELD2U10 + { 0xba, 0x00 }, // PANELD2U11 + { 0xc7, 0x02 }, // PANELD2U24 + { 0xca, 0x17 }, // PANELD2U27 + { 0xcb, 0x18 }, // PANELD2U28 + { 0xcc, 0x0a }, // PANELD2U29 + { 0xcd, 0x10 }, // PANELD2U30 + { 0xce, 0x0e }, // PANELD2U31 + { 0xcf, 0x0c }, // PANELD2U32 + { 0xd0, 0x00 }, // PANELD2U33 + // Map internal GOA signals to GOA output pad + { 0x81, 0x00 }, // PANELU2D2 + { 0x84, 0x15 }, // PANELU2D5 + { 0x85, 0x16 }, // PANELU2D6 + { 0x86, 0x10 }, // PANELU2D7 + { 0x87, 0x0a }, // PANELU2D8 + { 0x88, 0x0c }, // PANELU2D9 + { 0x89, 0x0e }, // PANELU2D10 + { 0x8a, 0x02 }, // PANELU2D11 + { 0x97, 0x00 }, // PANELU2D24 + { 0x9a, 0x17 }, // PANELU2D27 + { 0x9b, 0x18 }, // PANELU2D28 + { 0x9c, 0x0f }, // PANELU2D29 + { 0x9d, 0x09 }, // PANELU2D30 + { 0x9e, 0x0b }, // PANELU2D31 + { 0x9f, 0x0d }, // PANELU2D32 + { 0xa0, 0x01 }, // PANELU2D33 + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Unknown registers + { 0x01, 0x01 }, + { 0x02, 0xda }, + { 0x03, 0xba }, + { 0x04, 0xa8 }, + { 0x05, 0x9a }, + { 0x06, 0x70 }, + { 0x07, 0xff }, + { 0x08, 0x91 }, + { 0x09, 0x90 }, + { 0x0a, 0xff }, + { 0x0b, 0x8f }, + { 0x0c, 0x60 }, + { 0x0d, 0x58 }, + { 0x0e, 0x48 }, + { 0x0f, 0x38 }, + { 0x10, 0x2b }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, + // Display Access Control + { 0x36, 0x0a }, // bgr =3D 1, ss =3D 1, gs =3D 0 +}; + static inline struct nv3052c *to_nv3052c(struct drm_panel *panel) { return container_of(panel, struct nv3052c, panel); @@ -460,6 +655,21 @@ static const struct drm_display_mode ltk035c5444t_mode= s[] =3D { }, }; =20 +static const struct drm_display_mode fs035vg158_modes[] =3D { + { /* 60 Hz */ + .clock =3D 21000, + .hdisplay =3D 640, + .hsync_start =3D 640 + 34, + .hsync_end =3D 640 + 34 + 4, + .htotal =3D 640 + 34 + 4 + 20, + .vdisplay =3D 480, + .vsync_start =3D 480 + 12, + .vsync_end =3D 480 + 12 + 4, + .vtotal =3D 480 + 12 + 4 + 6, + .flags =3D DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + }, +}; + static const struct nv3052c_panel_info ltk035c5444t_panel_info =3D { .display_modes =3D ltk035c5444t_modes, .num_modes =3D ARRAY_SIZE(ltk035c5444t_modes), @@ -471,14 +681,27 @@ static const struct nv3052c_panel_info ltk035c5444t_p= anel_info =3D { .panel_regs_len =3D ARRAY_SIZE(ltk035c5444t_panel_regs), }; =20 +static const struct nv3052c_panel_info fs035vg158_panel_info =3D { + .display_modes =3D fs035vg158_modes, + .num_modes =3D ARRAY_SIZE(fs035vg158_modes), + .width_mm =3D 70, + .height_mm =3D 53, + .bus_format =3D MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags =3D DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, + .panel_regs =3D fs035vg158_panel_regs, + .panel_regs_len =3D ARRAY_SIZE(fs035vg158_panel_regs), +}; + static const struct spi_device_id nv3052c_ids[] =3D { { "ltk035c5444t", }, + { "fs035vg158", }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(spi, nv3052c_ids); =20 static const struct of_device_id nv3052c_of_match[] =3D { { .compatible =3D "leadtek,ltk035c5444t", .data =3D <k035c5444t_panel_i= nfo }, + { .compatible =3D "fascontek,fs035vg158", .data =3D &fs035vg158_panel_inf= o }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, nv3052c_of_match); --=20 2.42.0 From nobody Fri Feb 13 12:42:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F1A6CE7A91 for ; Mon, 25 Sep 2023 02:12:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231858AbjIYCMI (ORCPT ); Sun, 24 Sep 2023 22:12:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231843AbjIYCL4 (ORCPT ); Sun, 24 Sep 2023 22:11:56 -0400 Received: from out-190.mta0.migadu.com (out-190.mta0.migadu.com [IPv6:2001:41d0:1004:224b::be]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B64411B0 for ; Sun, 24 Sep 2023 19:11:48 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1695607907; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=y2D4ndlv6XBBNSayv9WpZm/nwIasLD85Z8EivmdKgzU=; b=RdHDtsbNWCx1JNGGXeTjSeIrNZQoqQW+PvoAHMK/bTVzCRQz9N2Ko7b2JjzGNCgHuVykRT jjz+hYVGJseB65cDSUekskVuddOUOmrTgbmlPsujCCaaRchDeTnZPPLzHQPfKjnp3blQj5 Qfgfy+coT6QiFYy/LPmyC87ykXYRwPY3yyqJG/+m/7rk3JPPWYzER3sZEvEKWpPQb7uwZi VMT2lGSsGYgiWsb0sYEmVqPjclgB09g3/76/Wl9wsbYLWkwn304xpkO2qbXlL+WyxO4tOX dCO33TvpNWfxNn4+fTv03UDQE1OXXg9+x3Nx1KhqIm9SfRXAkF6ozbh09kzsJA== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Heiko Stuebner , Chris Morgan , Jagan Teki , John Watts , Paul Cercueil , Christophe Branchereau , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [RFC PATCH v3 5/7] dt-bindings: display: panel: Clean up leadtek,ltk035c5444t properties Date: Mon, 25 Sep 2023 12:10:56 +1000 Message-ID: <20230925021059.451019-6-contact@jookia.org> In-Reply-To: <20230925021059.451019-1-contact@jookia.org> References: <20230925021059.451019-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove common properties listed in common yaml files. Add required properties needed to describe the panel. Signed-off-by: John Watts Reviewed-by: Rob Herring --- .../bindings/display/panel/leadtek,ltk035c5444t.yaml | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/leadtek,ltk035= c5444t.yaml b/Documentation/devicetree/bindings/display/panel/leadtek,ltk03= 5c5444t.yaml index ebdca5f5a001..7a55961e1a3d 100644 --- a/Documentation/devicetree/bindings/display/panel/leadtek,ltk035c5444t.= yaml +++ b/Documentation/devicetree/bindings/display/panel/leadtek,ltk035c5444t.= yaml @@ -18,16 +18,12 @@ properties: compatible: const: leadtek,ltk035c5444t =20 - backlight: true - port: true - power-supply: true - reg: true - reset-gpios: true - spi-3wire: true =20 required: - compatible + - reg + - port - power-supply - reset-gpios =20 --=20 2.42.0 From nobody Fri Feb 13 12:42:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D290CE7A91 for ; Mon, 25 Sep 2023 02:12:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231784AbjIYCMN (ORCPT ); Sun, 24 Sep 2023 22:12:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231769AbjIYCMB (ORCPT ); Sun, 24 Sep 2023 22:12:01 -0400 Received: from out-202.mta0.migadu.com (out-202.mta0.migadu.com [91.218.175.202]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 571C4193 for ; Sun, 24 Sep 2023 19:11:55 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1695607913; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Gv+uafqaxdaZgt/RSDYyi9C7m8D3DymG7MRuMChltow=; b=YWs5pGYMd+dRD8Qyiiih1AuF22KRu13DKM6DqbOM/k+3M8Sc8qCYwFYNjYxs08l3KUzxGK FOx/Nrh51hSfPbukJYr7xS9hE0iErhScAWcUawXkT/4YZoHOLpVHJtSffcn6GblyApb0y6 JsHNCtsE1YDhOaDBaRzt1V1eRufeTaQBkD1+eqkYUtht8hp3CuQJzU6KrD3J+yx4hB/kDe iV0aoRe1ijsv69Hs8YZNWnVu+2W/EVnxuAQ9V4dJgg269KaY1tz0Zi8GItF/XIzSg60Pol z95GCuDMRzygBOD4ODNM8TeiX2v6j4NZv5plr0+Cr4WhZt9vyncRYZvuOCzlfg== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Heiko Stuebner , Chris Morgan , Jagan Teki , John Watts , Paul Cercueil , Christophe Branchereau , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [RFC PATCH v3 6/7] dt-bindings: vendor-prefixes: Add fascontek Date: Mon, 25 Sep 2023 12:10:57 +1000 Message-ID: <20230925021059.451019-7-contact@jookia.org> In-Reply-To: <20230925021059.451019-1-contact@jookia.org> References: <20230925021059.451019-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fascontek manufactures LCD panels such as the FS035VG158. Signed-off-by: John Watts Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 565b13fb429d..744317e2a7cb 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -468,6 +468,8 @@ patternProperties: description: Fairphone B.V. "^faraday,.*": description: Faraday Technology Corporation + "^fascontek,.*": + description: Fascontek "^fastrax,.*": description: Fastrax Oy "^fcs,.*": --=20 2.42.0 From nobody Fri Feb 13 12:42:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B607DCE7A91 for ; Mon, 25 Sep 2023 02:12:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231853AbjIYCMU (ORCPT ); Sun, 24 Sep 2023 22:12:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231855AbjIYCMI (ORCPT ); Sun, 24 Sep 2023 22:12:08 -0400 Received: from out-201.mta1.migadu.com (out-201.mta1.migadu.com [IPv6:2001:41d0:203:375::c9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 764CD1AB for ; Sun, 24 Sep 2023 19:12:01 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1695607919; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JhEQ1dqgKvz3w9QUVhZNxp0xbOiz8esdacL61UcOl+o=; b=reLviE8eY03Zixne93aJYjmlNnoeKH3LZ7mp6VsZHKBJPOc9sKjWVPwEFW3s/4NENAjZW8 deain8KjDdxO8t7euO5BpC0nX+tduW1A7cUFDILo6X9gQ80H8zliAQH+Ztk1O4ROyg73UJ 54pJspsixPhbOEElPzb4l94W8GodS+ejKgyLe57267wK011zlpqD/yI08N+DNLt8KiaP6Q pG5ePA7/BwT/nsX6BhG01wc8F76Q5GsUt7uUWqupdyStwXj9LM5F3AjerqhzJbDBI6kSZl qTPbUemZr6Oe6HeGCfvo6saHRrIpN3X+MjWFf2u/h3IbDQab1bpH8kzypWy8EQ== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Jessica Zhang , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Heiko Stuebner , Chris Morgan , Jagan Teki , John Watts , Paul Cercueil , Christophe Branchereau , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [RFC PATCH v3 7/7] dt-bindings: display: panel: add Fascontek FS035VG158 panel Date: Mon, 25 Sep 2023 12:10:58 +1000 Message-ID: <20230925021059.451019-8-contact@jookia.org> In-Reply-To: <20230925021059.451019-1-contact@jookia.org> References: <20230925021059.451019-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a small 3.5" 640x480 IPS LCD panel. Signed-off-by: John Watts Reviewed-by: Rob Herring --- .../display/panel/fascontek,fs035vg158.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/fascont= ek,fs035vg158.yaml diff --git a/Documentation/devicetree/bindings/display/panel/fascontek,fs03= 5vg158.yaml b/Documentation/devicetree/bindings/display/panel/fascontek,fs0= 35vg158.yaml new file mode 100644 index 000000000000..d13c4bd26de4 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/fascontek,fs035vg158.= yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/fascontek,fs035vg158.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Fascontek FS035VG158 3.5" (640x480 pixels) 24-bit IPS LCD panel + +maintainers: + - John Watts + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: fascontek,fs035vg158 + + spi-3wire: true + +required: + - compatible + - reg + - port + - power-supply + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + panel@0 { + compatible =3D "fascontek,fs035vg158"; + reg =3D <0>; + + spi-3wire; + spi-max-frequency =3D <3125000>; + + reset-gpios =3D <&gpe 2 GPIO_ACTIVE_LOW>; + + backlight =3D <&backlight>; + power-supply =3D <&vcc>; + + port { + panel_input: endpoint { + remote-endpoint =3D <&panel_output>; + }; + }; + }; + }; --=20 2.42.0