From nobody Wed Dec 17 04:35:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 784E1CE7A8B for ; Fri, 22 Sep 2023 21:30:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230035AbjIVVas (ORCPT ); Fri, 22 Sep 2023 17:30:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229944AbjIVVak (ORCPT ); Fri, 22 Sep 2023 17:30:40 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFC43C1; Fri, 22 Sep 2023 14:30:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695418234; x=1726954234; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ShdByvzHZrIatOiiLohtDB7ahuIepttl4FPmXc1tWd0=; b=L2kIgiJAHiWoqzcB+ojIgpaqg5V9hZNZcNXdEm4qW+js73H3Px64mLir xZSiKNvWQs0yJfHUN+bgefWZRU2hoCCFSjVz5bvDGjDoYnZQGujr8mArF sbJhTgMCY72FdyaOMQuj2V/vdTpUMeqvvj7Iwtsrd9ttDLJKOfcBzBKfh RAOt53x1PQoMQR77fAS7jbncgbvfU6PxNKC7RJf9eY0uEgxjkJNoB8K3k RIsT1PcMr3tzMttwrJKT0sqMYftaZ39EwjH7YYO9nePeCYBcJ99RqG26m ud7xhFt6peY5wYfj7SBAOp4WM30dOUD3cK1NRHC3N8YOBQTZ6KLwYUf2o g==; X-IronPort-AV: E=McAfee;i="6600,9927,10841"; a="379828421" X-IronPort-AV: E=Sophos;i="6.03,169,1694761200"; d="scan'208";a="379828421" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2023 14:30:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10841"; a="813237856" X-IronPort-AV: E=Sophos;i="6.03,169,1694761200"; d="scan'208";a="813237856" Received: from linux.intel.com ([10.54.29.200]) by fmsmga008.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2023 14:30:34 -0700 Received: from debox1-desk4.intel.com (unknown [10.212.188.234]) by linux.intel.com (Postfix) with ESMTP id E98B8580DB2; Fri, 22 Sep 2023 14:30:33 -0700 (PDT) From: "David E. Box" To: linux-kernel@vger.kernel.org, david.e.box@linux.intel.com, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH 10/11] platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P Date: Fri, 22 Sep 2023 14:30:31 -0700 Message-Id: <20230922213032.1770590-11-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922213032.1770590-1-david.e.box@linux.intel.com> References: <20230922213032.1770590-1-david.e.box@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Xi Pardee Add support to read the low power mode requirements for Meteor Lake M and Meteor Lake P. Signed-off-by: Xi Pardee Signed-off-by: David E. Box --- drivers/platform/x86/intel/pmc/mtl.c | 39 +++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/in= tel/pmc/mtl.c index 780874142a90..c2ac50cfdd51 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -11,6 +11,13 @@ #include #include "core.h" =20 +/* PMC SSRAM PMT Telemetry GUIDS */ +#define SOCP_LPM_REQ_GUID 0x2625030 +#define IOEM_LPM_REQ_GUID 0x4357464 +#define IOEP_LPM_REQ_GUID 0x5077612 + +static const u8 MTL_LPM_REG_INDEX[] =3D {0, 4, 5, 6, 8, 9, 10, 11, 12, 13,= 14, 15, 16, 20}; + /* * Die Mapping to Product. * Product SOCDie IOEDie PCHDie @@ -465,6 +472,7 @@ const struct pmc_reg_map mtl_socm_reg_map =3D { .lpm_sts =3D mtl_socm_lpm_maps, .lpm_status_offset =3D MTL_LPM_STATUS_OFFSET, .lpm_live_status_offset =3D MTL_LPM_LIVE_STATUS_OFFSET, + .lpm_reg_index =3D MTL_LPM_REG_INDEX, }; =20 const struct pmc_bit_map mtl_ioep_pfear_map[] =3D { @@ -782,6 +790,13 @@ const struct pmc_reg_map mtl_ioep_reg_map =3D { .ltr_show_sts =3D mtl_ioep_ltr_show_map, .ltr_ignore_offset =3D CNP_PMC_LTR_IGNORE_OFFSET, .ltr_ignore_max =3D ADL_NUM_IP_IGN_ALLOWED, + .lpm_num_maps =3D ADL_LPM_NUM_MAPS, + .lpm_res_counter_step_x2 =3D TGL_PMC_LPM_RES_COUNTER_STEP_X2, + .lpm_residency_offset =3D MTL_LPM_RESIDENCY_OFFSET, + .lpm_priority_offset =3D MTL_LPM_PRI_OFFSET, + .lpm_en_offset =3D MTL_LPM_EN_OFFSET, + .lpm_sts_latch_en_offset =3D MTL_LPM_STATUS_LATCH_EN_OFFSET, + .lpm_reg_index =3D MTL_LPM_REG_INDEX, }; =20 const struct pmc_bit_map mtl_ioem_pfear_map[] =3D { @@ -922,6 +937,13 @@ const struct pmc_reg_map mtl_ioem_reg_map =3D { .ltr_show_sts =3D mtl_ioep_ltr_show_map, .ltr_ignore_offset =3D CNP_PMC_LTR_IGNORE_OFFSET, .ltr_ignore_max =3D ADL_NUM_IP_IGN_ALLOWED, + .lpm_sts_latch_en_offset =3D MTL_LPM_STATUS_LATCH_EN_OFFSET, + .lpm_num_maps =3D ADL_LPM_NUM_MAPS, + .lpm_priority_offset =3D MTL_LPM_PRI_OFFSET, + .lpm_en_offset =3D MTL_LPM_EN_OFFSET, + .lpm_res_counter_step_x2 =3D TGL_PMC_LPM_RES_COUNTER_STEP_X2, + .lpm_residency_offset =3D MTL_LPM_RESIDENCY_OFFSET, + .lpm_reg_index =3D MTL_LPM_REG_INDEX, }; =20 #define PMC_DEVID_SOCM 0x7e7f @@ -929,16 +951,19 @@ const struct pmc_reg_map mtl_ioem_reg_map =3D { #define PMC_DEVID_IOEM 0x7ebf static struct pmc_info mtl_pmc_info_list[] =3D { { - .devid =3D PMC_DEVID_SOCM, - .map =3D &mtl_socm_reg_map, + .guid =3D SOCP_LPM_REQ_GUID, + .devid =3D PMC_DEVID_SOCM, + .map =3D &mtl_socm_reg_map, }, { - .devid =3D PMC_DEVID_IOEP, - .map =3D &mtl_ioep_reg_map, + .guid =3D IOEP_LPM_REQ_GUID, + .devid =3D PMC_DEVID_IOEP, + .map =3D &mtl_ioep_reg_map, }, { - .devid =3D PMC_DEVID_IOEM, - .map =3D &mtl_ioem_reg_map + .guid =3D IOEM_LPM_REQ_GUID, + .devid =3D PMC_DEVID_IOEM, + .map =3D &mtl_ioem_reg_map }, {} }; @@ -1012,5 +1037,7 @@ int mtl_core_init(struct pmc_dev *pmcdev) dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n"); pmc_core_send_ltr_ignore(pmcdev, 3); =20 + ret =3D pmc_core_ssram_get_lpm_reqs(pmcdev); + return 0; } --=20 2.34.1