From nobody Fri Feb 13 15:40:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 033E5E6FE52 for ; Fri, 22 Sep 2023 15:21:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232673AbjIVPVg (ORCPT ); Fri, 22 Sep 2023 11:21:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229986AbjIVPVd (ORCPT ); Fri, 22 Sep 2023 11:21:33 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10408A3; Fri, 22 Sep 2023 08:21:27 -0700 (PDT) Date: Fri, 22 Sep 2023 17:21:22 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1695396085; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type; bh=giv5GthGmSzPfmD5eP8G9h2KnjXUevF2nuFoLaUAjYI=; b=uMXLCNQ2f9gu8fKDtazlwo2vAYY2Biog0f2symzkEqSXg54Uo8X/OQivLgzaDtwzSx6x1T GDwjIJeDieeXeq6NwQFe0nzPHqLvnHitlaIbvcI95/Vv8G2A9yuzycF8qGmChoYDOvzv3V FplkTSXiTYqNJULYOS9a3Xc+6kiIIJU4j8ysFO2dqYdHjHI9vRov9Jq86+B/PUJK5K+Rkv gI6G3LEKJIa+fbafGVTTEnHSoHXg1s2eTyEa1aFbf+w8iu/TryT0CBU/ukcU69Izb2OOKa bIzXMLOpigZNr3Az1XxlIjIbN0RpAWej1x18yCxtuvfEFCi067NYGX8vbptwow== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1695396085; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type; bh=giv5GthGmSzPfmD5eP8G9h2KnjXUevF2nuFoLaUAjYI=; b=a3lI0ZB1goRal4awrdOjFRe5fRjvfZ1EJvJrWIlAN9aj/RN4O3+9/yopxHBxLG5RfI4wMi KFZq6fDUXgYCDwCw== From: Sebastian Andrzej Siewior To: Thomas Gleixner Cc: LKML , linux-rt-users@vger.kernel.org, Steven Rostedt Subject: [ANNOUNCE] v6.6-rc2-rt4 Message-ID: <20230922152122.WTxQdDyw@linutronix.de> MIME-Version: 1.0 Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dear RT folks! I'm pleased to announce the v6.6-rc2-rt4 patch set.=20 Changes since v6.6-rc2-rt3: - "sander44" reported a warning originating from amdgpu driver. Known issues None The delta patch against v6.6-rc2-rt3 is appended below and can be found her= e: =20 https://cdn.kernel.org/pub/linux/kernel/projects/rt/6.6/incr/patch-6.6= -rc2-rt3-rt4.patch.xz You can get this release via the git tree at: https://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git v= 6.6-rc2-rt4 The RT patch against v6.6-rc2 can be found here: https://cdn.kernel.org/pub/linux/kernel/projects/rt/6.6/older/patch-6.6= -rc2-rt4.patch.xz The split quilt queue is available at: https://cdn.kernel.org/pub/linux/kernel/projects/rt/6.6/older/patches-6= .6-rc2-rt4.tar.xz Sebastian diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/d= rm/amd/display/amdgpu_dm/dc_fpu.c index 172aa10a8800f..4ae4720535a56 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -60,11 +60,9 @@ static DEFINE_PER_CPU(int, fpu_recursion_depth); */ inline void dc_assert_fp_enabled(void) { - int *pcpu, depth =3D 0; + int depth; =20 - pcpu =3D get_cpu_ptr(&fpu_recursion_depth); - depth =3D *pcpu; - put_cpu_ptr(&fpu_recursion_depth); + depth =3D __this_cpu_read(fpu_recursion_depth); =20 ASSERT(depth >=3D 1); } @@ -84,33 +82,28 @@ inline void dc_assert_fp_enabled(void) */ void dc_fpu_begin(const char *function_name, const int line) { - int *pcpu; + int depth; =20 - pcpu =3D get_cpu_ptr(&fpu_recursion_depth); - *pcpu +=3D 1; + WARN_ON_ONCE(!in_task()); + preempt_disable(); + depth =3D __this_cpu_inc_return(fpu_recursion_depth); =20 - if (*pcpu =3D=3D 1) { + if (depth =3D=3D 1) { #if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) - migrate_disable(); kernel_fpu_begin(); #elif defined(CONFIG_PPC64) - if (cpu_has_feature(CPU_FTR_VSX_COMP)) { - preempt_disable(); + if (cpu_has_feature(CPU_FTR_VSX_COMP)) enable_kernel_vsx(); - } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) { - preempt_disable(); + else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) enable_kernel_altivec(); - } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) { - preempt_disable(); + else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) enable_kernel_fp(); - } #elif defined(CONFIG_ARM64) kernel_neon_begin(); #endif } =20 - TRACE_DCN_FPU(true, function_name, line, *pcpu); - put_cpu_ptr(&fpu_recursion_depth); + TRACE_DCN_FPU(true, function_name, line, depth); } =20 /** @@ -125,30 +118,26 @@ void dc_fpu_begin(const char *function_name, const in= t line) */ void dc_fpu_end(const char *function_name, const int line) { - int *pcpu; + int depth; =20 - pcpu =3D get_cpu_ptr(&fpu_recursion_depth); - *pcpu -=3D 1; - if (*pcpu <=3D 0) { + depth =3D __this_cpu_dec_return(fpu_recursion_depth); + if (depth =3D=3D 0) { #if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) kernel_fpu_end(); - migrate_enable(); #elif defined(CONFIG_PPC64) - if (cpu_has_feature(CPU_FTR_VSX_COMP)) { + if (cpu_has_feature(CPU_FTR_VSX_COMP)) disable_kernel_vsx(); - preempt_enable(); - } else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) { + else if (cpu_has_feature(CPU_FTR_ALTIVEC_COMP)) disable_kernel_altivec(); - preempt_enable(); - } else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) { + else if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) disable_kernel_fp(); - preempt_enable(); - } #elif defined(CONFIG_ARM64) kernel_neon_end(); #endif + } else { + WARN_ON_ONCE(depth < 0); } =20 - TRACE_DCN_FPU(false, function_name, line, *pcpu); - put_cpu_ptr(&fpu_recursion_depth); + TRACE_DCN_FPU(false, function_name, line, depth); + preempt_enable(); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/driver= s/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index d587f807dfd7c..5036a3e608324 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2141,9 +2141,17 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct = dc_state *context, bool fast_validate) { bool voltage_supported; + display_e2e_pipe_params_st *pipes; + + pipes =3D kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_param= s_st), GFP_KERNEL); + if (!pipes) + return false; + DC_FP_START(); - voltage_supported =3D dcn20_validate_bandwidth_fp(dc, context, fast_valid= ate); + voltage_supported =3D dcn20_validate_bandwidth_fp(dc, context, fast_valid= ate, pipes); DC_FP_END(); + + kfree(pipes); return voltage_supported; } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/driver= s/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index d1a25fe6c44fa..5674c3450fc36 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -953,9 +953,17 @@ static bool dcn21_validate_bandwidth(struct dc *dc, st= ruct dc_state *context, bool fast_validate) { bool voltage_supported; + display_e2e_pipe_params_st *pipes; + + pipes =3D kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_param= s_st), GFP_KERNEL); + if (!pipes) + return false; + DC_FP_START(); - voltage_supported =3D dcn21_validate_bandwidth_fp(dc, context, fast_valid= ate); + voltage_supported =3D dcn21_validate_bandwidth_fp(dc, context, fast_valid= ate, pipes); DC_FP_END(); + + kfree(pipes); return voltage_supported; } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers= /gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 5805fb02af14e..2ad92497b9bf2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -1923,7 +1923,7 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _= vcs_dpi_soc_bounding_box_st } =20 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_sta= te *context, - bool fast_validate) + bool fast_validate, display_e2e_pipe_params_st *pipes) { bool out =3D false; =20 @@ -1932,7 +1932,6 @@ static bool dcn20_validate_bandwidth_internal(struct = dc *dc, struct dc_state *co int vlevel =3D 0; int pipe_split_from[MAX_PIPES]; int pipe_cnt =3D 0; - display_e2e_pipe_params_st *pipes =3D kzalloc(dc->res_pool->pipe_count * = sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); DC_LOGGER_INIT(dc->ctx->logger); =20 BW_VAL_TRACE_COUNT(); @@ -1967,16 +1966,14 @@ static bool dcn20_validate_bandwidth_internal(struc= t dc *dc, struct dc_state *co out =3D false; =20 validate_out: - kfree(pipes); =20 BW_VAL_TRACE_FINISH(); =20 return out; } =20 -bool dcn20_validate_bandwidth_fp(struct dc *dc, - struct dc_state *context, - bool fast_validate) +bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, + bool fast_validate, display_e2e_pipe_params_st *pipes) { bool voltage_supported =3D false; bool full_pstate_supported =3D false; @@ -1995,11 +1992,11 @@ bool dcn20_validate_bandwidth_fp(struct dc *dc, ASSERT(context !=3D dc->current_state); =20 if (fast_validate) { - return dcn20_validate_bandwidth_internal(dc, context, true); + return dcn20_validate_bandwidth_internal(dc, context, true, pipes); } =20 // Best case, we support full UCLK switch latency - voltage_supported =3D dcn20_validate_bandwidth_internal(dc, context, fals= e); + voltage_supported =3D dcn20_validate_bandwidth_internal(dc, context, fals= e, pipes); full_pstate_supported =3D context->bw_ctx.bw.dcn.clk.p_state_change_suppo= rt; =20 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us =3D=3D 0 || @@ -2011,7 +2008,8 @@ bool dcn20_validate_bandwidth_fp(struct dc *dc, // Fallback: Try to only support G6 temperature read latency context->bw_ctx.dml.soc.dram_clock_change_latency_us =3D context->bw_ctx.= dml.soc.dummy_pstate_latency_us; =20 - voltage_supported =3D dcn20_validate_bandwidth_internal(dc, context, fals= e); + memset(pipes, 0, dc->res_pool->pipe_count * sizeof(display_e2e_pipe_param= s_st)); + voltage_supported =3D dcn20_validate_bandwidth_internal(dc, context, fals= e, pipes); dummy_pstate_supported =3D context->bw_ctx.bw.dcn.clk.p_state_change_supp= ort; =20 if (voltage_supported && (dummy_pstate_supported || !(context->stream_cou= nt))) { @@ -2216,9 +2214,8 @@ static void dcn21_calculate_wm(struct dc *dc, struct = dc_state *context, &context->bw_ctx.dml, pipes, pipe_cnt); } =20 -bool dcn21_validate_bandwidth_fp(struct dc *dc, - struct dc_state *context, - bool fast_validate) +bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, + bool fast_validate, display_e2e_pipe_params_st *pipes) { bool out =3D false; =20 @@ -2227,7 +2224,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, int vlevel =3D 0; int pipe_split_from[MAX_PIPES]; int pipe_cnt =3D 0; - display_e2e_pipe_params_st *pipes =3D kzalloc(dc->res_pool->pipe_count * = sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); DC_LOGGER_INIT(dc->ctx->logger); =20 BW_VAL_TRACE_COUNT(); @@ -2267,7 +2263,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, out =3D false; =20 validate_out: - kfree(pipes); =20 BW_VAL_TRACE_FINISH(); =20 diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h b/drivers= /gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h index c51badf7b68a9..b6c34198ddc86 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h @@ -61,9 +61,8 @@ void dcn20_update_bounding_box(struct dc *dc, unsigned int num_states); void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb); -bool dcn20_validate_bandwidth_fp(struct dc *dc, - struct dc_state *context, - bool fast_validate); +bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, + bool fast_validate, display_e2e_pipe_params_st *pipes); void dcn20_fpu_set_wm_ranges(int i, struct pp_smu_wm_range_sets *ranges, struct _vcs_dpi_soc_bounding_box_st *loaded_bb); @@ -77,9 +76,8 @@ int dcn21_populate_dml_pipes_from_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate); -bool dcn21_validate_bandwidth_fp(struct dc *dc, - struct dc_state *context, - bool fast_validate); +bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, = bool + fast_validate, display_e2e_pipe_params_st *pipes); void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_= params); =20 void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params); diff --git a/localversion-rt b/localversion-rt index 1445cd65885cd..ad3da1bcab7e8 100644 --- a/localversion-rt +++ b/localversion-rt @@ -1 +1 @@ --rt3 +-rt4