From nobody Fri Feb 13 15:39:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1910BCD4F3B for ; Fri, 22 Sep 2023 09:29:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232941AbjIVJ3I convert rfc822-to-8bit (ORCPT ); Fri, 22 Sep 2023 05:29:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232939AbjIVJ3C (ORCPT ); Fri, 22 Sep 2023 05:29:02 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58C3419E; Fri, 22 Sep 2023 02:28:53 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 12E2A17EDF; Fri, 22 Sep 2023 17:28:51 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:51 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:49 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v5 1/4] dt-bindings: pwm: Add StarFive PWM module Date: Fri, 22 Sep 2023 17:28:45 +0800 Message-ID: <20230922092848.72664-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922092848.72664-1-william.qiu@starfivetech.com> References: <20230922092848.72664-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add documentation to describe StarFive Pulse Width Modulation controller driver. Signed-off-by: William Qiu Reviewed-by: Krzysztof Kozlowski Reviewed-by: Hal Feng --- .../bindings/pwm/starfive,jh7100-pwm.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7100-p= wm.yaml diff --git a/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml= b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml new file mode 100644 index 000000000000..6f1937beb962 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/starfive,jh7100-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 and JH7110 PWM controller + +maintainers: + - William Qiu + +description: + StarFive SoCs contain PWM and when operating in PWM mode, the PTC core g= enerates + binary signal with user-programmable low and high periods. Clock source = for the + PWM can be either system clock or external clock. Each PWM timer block p= rovides 8 + PWM channels. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - starfive,jh7100-pwm + - starfive,jh7110-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + pwm@12490000 { + compatible =3D "starfive,jh7100-pwm"; + reg =3D <0x12490000 0x10000>; + clocks =3D <&clkgen 181>; + resets =3D <&rstgen 109>; + #pwm-cells =3D <3>; + }; --=20 2.34.1 From nobody Fri Feb 13 15:39:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6136ECD4F3B for ; Fri, 22 Sep 2023 09:29:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232985AbjIVJ3N convert rfc822-to-8bit (ORCPT ); Fri, 22 Sep 2023 05:29:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233001AbjIVJ3H (ORCPT ); Fri, 22 Sep 2023 05:29:07 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9BF31BC; Fri, 22 Sep 2023 02:28:59 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id E518624E2A1; Fri, 22 Sep 2023 17:28:51 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:52 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:50 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v5 2/4] pwm: starfive: Add PWM driver support Date: Fri, 22 Sep 2023 17:28:46 +0800 Message-ID: <20230922092848.72664-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922092848.72664-1-william.qiu@starfivetech.com> References: <20230922092848.72664-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Pulse Width Modulation driver support for StarFive JH7100 and JH7110 SoC. Co-developed-by: Hal Feng Signed-off-by: Hal Feng Signed-off-by: William Qiu --- MAINTAINERS | 7 ++ drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-starfive.c | 190 +++++++++++++++++++++++++++++++++++++ 4 files changed, 207 insertions(+) create mode 100644 drivers/pwm/pwm-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS index bf0f54c24f81..bc2155bd2712 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20495,6 +20495,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71* F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h =20 +STARFIVE JH71X0 PWM DRIVERS +M: William Qiu +M: Hal Feng +S: Supported +F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml +F: drivers/pwm/pwm-starfive-ptc.c + STARFIVE JH71X0 RESET CONTROLLER DRIVERS M: Emil Renner Berthing M: Hal Feng diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8ebcddf91f7b..e2ee0169f6e4 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -569,6 +569,15 @@ config PWM_SPRD To compile this driver as a module, choose M here: the module will be called pwm-sprd. =20 +config PWM_STARFIVE + tristate "StarFive PWM support" + depends on ARCH_STARFIVE || COMPILE_TEST + help + Generic PWM framework driver for StarFive SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-starfive. + config PWM_STI tristate "STiH4xx PWM support" depends on ARCH_STI || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c822389c2a24..93b954376873 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_SIFIVE) +=3D pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) +=3D pwm-sl28cpld.o obj-$(CONFIG_PWM_SPEAR) +=3D pwm-spear.o obj-$(CONFIG_PWM_SPRD) +=3D pwm-sprd.o +obj-$(CONFIG_PWM_STARFIVE) +=3D pwm-starfive.o obj-$(CONFIG_PWM_STI) +=3D pwm-sti.o obj-$(CONFIG_PWM_STM32) +=3D pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) +=3D pwm-stm32-lp.o diff --git a/drivers/pwm/pwm-starfive.c b/drivers/pwm/pwm-starfive.c new file mode 100644 index 000000000000..d390349fc95d --- /dev/null +++ b/drivers/pwm/pwm-starfive.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PWM driver for the StarFive JH71x0 SoC + * + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Access PTC register (CNTR, HRC, LRC and CTRL) */ +#define REG_PTC_BASE_ADDR_SUB(base, N) ((base) + (((N) > 3) ? \ + (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10))) +#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N)) +#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4) +#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8) +#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC) + +/* PTC_RPTC_CTRL register bits*/ +#define PTC_EN BIT(0) +#define PTC_ECLK BIT(1) +#define PTC_NEC BIT(2) +#define PTC_OE BIT(3) +#define PTC_SIGNLE BIT(4) +#define PTC_INTE BIT(5) +#define PTC_INT BIT(6) +#define PTC_CNTRRST BIT(7) +#define PTC_CAPTE BIT(8) + +struct starfive_pwm_ptc_device { + struct pwm_chip chip; + struct clk *clk; + struct reset_control *rst; + void __iomem *regs; + u32 clk_rate; /* PWM APB clock frequency */ +}; + +static inline struct starfive_pwm_ptc_device * +chip_to_starfive_ptc(struct pwm_chip *chip) + +{ + return container_of(chip, struct starfive_pwm_ptc_device, chip); +} + +static int starfive_pwm_ptc_get_state(struct pwm_chip *chip, + struct pwm_device *dev, + struct pwm_state *state) +{ + struct starfive_pwm_ptc_device *pwm =3D chip_to_starfive_ptc(chip); + u32 period_data, duty_data, ctrl_data; + + period_data =3D readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm)); + duty_data =3D readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm)); + ctrl_data =3D readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); + + state->period =3D DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, = pwm->clk_rate); + state->duty_cycle =3D DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC= , pwm->clk_rate); + state->polarity =3D PWM_POLARITY_INVERSED; + state->enabled =3D (ctrl_data & PTC_EN) ? true : false; + + return 0; +} + +static int starfive_pwm_ptc_apply(struct pwm_chip *chip, + struct pwm_device *dev, + const struct pwm_state *state) +{ + struct starfive_pwm_ptc_device *pwm =3D chip_to_starfive_ptc(chip); + u32 period_data, duty_data, ctrl_data =3D 0; + + if (state->polarity !=3D PWM_POLARITY_INVERSED) + return -EINVAL; + + period_data =3D DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate, + NSEC_PER_SEC); + duty_data =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate, + NSEC_PER_SEC); + + writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm)); + writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm)); + writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm)); + + ctrl_data =3D readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); + if (state->enabled) + writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hw= pwm)); + else + writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev-= >hwpwm)); + + return 0; +} + +static const struct pwm_ops starfive_pwm_ptc_ops =3D { + .get_state =3D starfive_pwm_ptc_get_state, + .apply =3D starfive_pwm_ptc_apply, + .owner =3D THIS_MODULE, +}; + +static int starfive_pwm_ptc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct starfive_pwm_ptc_device *pwm; + struct pwm_chip *chip; + int ret; + + pwm =3D devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + chip =3D &pwm->chip; + chip->dev =3D dev; + chip->ops =3D &starfive_pwm_ptc_ops; + chip->npwm =3D 8; + chip->of_pwm_n_cells =3D 3; + + pwm->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->regs)) + return dev_err_probe(dev, PTR_ERR(pwm->regs), + "Unable to map IO resources\n"); + + pwm->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), + "Unable to get pwm's clock\n"); + + pwm->rst =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(pwm->rst)) + return dev_err_probe(dev, PTR_ERR(pwm->rst), + "Unable to get pwm's reset\n"); + + ret =3D reset_control_deassert(pwm->rst); + if (ret) { + dev_err(dev, "Failed to enable clock for pwm: %d\n", ret); + return ret; + } + + pwm->clk_rate =3D clk_get_rate(pwm->clk); + if (pwm->clk_rate <=3D 0) { + dev_warn(dev, "Failed to get APB clock rate\n"); + return -EINVAL; + } + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) { + dev_err(dev, "Cannot register PTC: %d\n", ret); + clk_disable_unprepare(pwm->clk); + reset_control_assert(pwm->rst); + return ret; + } + + platform_set_drvdata(pdev, pwm); + + return 0; +} + +static int starfive_pwm_ptc_remove(struct platform_device *dev) +{ + struct starfive_pwm_ptc_device *pwm =3D platform_get_drvdata(dev); + + reset_control_assert(pwm->rst); + clk_disable_unprepare(pwm->clk); + + return 0; +} + +static const struct of_device_id starfive_pwm_ptc_of_match[] =3D { + { .compatible =3D "starfive,jh7100-pwm" }, + { .compatible =3D "starfive,jh7110-pwm" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match); + +static struct platform_driver starfive_pwm_ptc_driver =3D { + .probe =3D starfive_pwm_ptc_probe, + .remove =3D starfive_pwm_ptc_remove, + .driver =3D { + .name =3D "pwm-starfive-ptc", + .of_match_table =3D starfive_pwm_ptc_of_match, + }, +}; +module_platform_driver(starfive_pwm_ptc_driver); + +MODULE_AUTHOR("Jieqin Chen"); +MODULE_AUTHOR("Hal Feng "); +MODULE_DESCRIPTION("StarFive PWM PTC driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Feb 13 15:39:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FA39CD4F42 for ; Fri, 22 Sep 2023 09:29:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233005AbjIVJ3Q convert rfc822-to-8bit (ORCPT ); Fri, 22 Sep 2023 05:29:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232989AbjIVJ3G (ORCPT ); Fri, 22 Sep 2023 05:29:06 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9C661BD; Fri, 22 Sep 2023 02:28:59 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id C617924E2A5; Fri, 22 Sep 2023 17:28:52 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:53 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:51 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v5 3/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration Date: Fri, 22 Sep 2023 17:28:47 +0800 Message-ID: <20230922092848.72664-4-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922092848.72664-1-william.qiu@starfivetech.com> References: <20230922092848.72664-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add StarFive JH7110 PWM controller node and add PWM pins configuration on VisionFive 2 board. Signed-off-by: William Qiu Reviewed-by: Hal Feng --- .../jh7110-starfive-visionfive-2.dtsi | 22 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi= b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index d79f94432b27..4bfb8f0f810f 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -268,6 +268,12 @@ reserved-data@600000 { }; }; =20 +&pwm { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm_pins>; + status =3D "okay"; +}; + &spi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&spi0_pins>; @@ -402,6 +408,22 @@ GPOEN_SYS_SDIO1_DATA3, }; }; =20 + pwm_pins: pwm-0 { + pwm-pins { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <12>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + spi0_pins: spi0-0 { mosi-pins { pinmux =3D ; + clocks =3D <&syscrg JH7110_SYSCLK_PWM_APB>; + resets =3D <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sfctemp: temperature-sensor@120e0000 { compatible =3D "starfive,jh7110-temp"; reg =3D <0x0 0x120e0000 0x0 0x10000>; --=20 2.34.1 From nobody Fri Feb 13 15:39:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23105CD4F42 for ; Fri, 22 Sep 2023 09:29:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232968AbjIVJ3G convert rfc822-to-8bit (ORCPT ); Fri, 22 Sep 2023 05:29:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232941AbjIVJ3C (ORCPT ); Fri, 22 Sep 2023 05:29:02 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 105831B0; Fri, 22 Sep 2023 02:28:55 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 94D8017ED4; Fri, 22 Sep 2023 17:28:53 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:53 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:52 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v5 4/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration Date: Fri, 22 Sep 2023 17:28:48 +0800 Message-ID: <20230922092848.72664-5-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922092848.72664-1-william.qiu@starfivetech.com> References: <20230922092848.72664-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add StarFive JH7100 PWM controller node and add PWM pins configuration on VisionFive 1 board. Signed-off-by: William Qiu Reviewed-by: Hal Feng --- .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++ 2 files changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..11876906cc05 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN, }; }; =20 + pwm_pins: pwm-0 { + pwm-pins { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <35>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + uart3_pins: uart3-0 { rx-pins { pinmux =3D ; }; =20 +&pwm { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm_pins>; + status =3D "okay"; +}; + &uart3 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart3_pins>; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts= /starfive/jh7100.dtsi index 35ab54fb235f..9c8c557031e6 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -274,6 +274,15 @@ watchdog@12480000 { <&rstgen JH7100_RSTN_WDT>; }; =20 + pwm: pwm@12490000 { + compatible =3D "starfive,jh7100-pwm"; + reg =3D <0x0 0x12490000 0x0 0x10000>; + clocks =3D <&clkgen JH7100_CLK_PWM_APB>; + resets =3D <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + sfctemp: temperature-sensor@124a0000 { compatible =3D "starfive,jh7100-temp"; reg =3D <0x0 0x124a0000 0x0 0x10000>; --=20 2.34.1