From nobody Fri Sep 20 09:49:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12438E7D0D5 for ; Fri, 22 Sep 2023 06:50:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229877AbjIVGum (ORCPT ); Fri, 22 Sep 2023 02:50:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229476AbjIVGud (ORCPT ); Fri, 22 Sep 2023 02:50:33 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76BFF100; Thu, 21 Sep 2023 23:50:23 -0700 (PDT) X-UUID: 4b6c329a591411eea33bb35ae8d461a2-20230922 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Hd86NQfy2/lhvIbniSQO9dAVZPI8a5X3Ca7Vv9yeC14=; b=Wx2tt5cakkAFikU6kOoaMhh6xKyeJMN7L6nSP7vnGrk03F5bu4NVTzD0fdwb64T1uoERtZDu3WOkkCBPqrjjbn6rTDdm7rD6Gn1AAYuWLY476Vkx/zsjCoihXuQl1HOCxdjm9MvBHsq3BfBPxgxyh1jEILtpP0Eiy44K30Gmb10=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:aefa9ee5-4375-41b6-8d7c-55f2704f07b0,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:eea054c3-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4b6c329a591411eea33bb35ae8d461a2-20230922 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2106204616; Fri, 22 Sep 2023 14:50:19 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 22 Sep 2023 14:50:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 22 Sep 2023 14:50:18 +0800 From: Moudy Ho To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Moudy Ho Subject: [PATCH v6 1/2] arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes Date: Fri, 22 Sep 2023 14:50:16 +0800 Message-ID: <20230922065017.10357-2-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230922065017.10357-1-moudy.ho@mediatek.com> References: <20230922065017.10357-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to generalize the node names, the DMA-related nodes corresponding to MT8183 MDP3 need to be corrected. Fixes: 60a2fb8d202a ("arm64: dts: mt8183: add MediaTek MDP3 nodes") Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 5169779d01df..bab68c233792 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1781,7 +1781,7 @@ mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; }; =20 - mdp3-rdma0@14001000 { + dma-controller0@14001000 { compatible =3D "mediatek,mt8183-mdp3-rdma"; reg =3D <0 0x14001000 0 0x1000>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x1000 0x1000>; @@ -1793,6 +1793,7 @@ iommus =3D <&iommu M4U_PORT_MDP_RDMA0>; mboxes =3D <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; + #dma-cells =3D <1>; }; =20 mdp3-rsz0@14003000 { @@ -1813,7 +1814,7 @@ clocks =3D <&mmsys CLK_MM_MDP_RSZ1>; }; =20 - mdp3-wrot0@14005000 { + dma-controller@14005000 { compatible =3D "mediatek,mt8183-mdp3-wrot"; reg =3D <0 0x14005000 0 0x1000>; mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; @@ -1822,6 +1823,7 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; clocks =3D <&mmsys CLK_MM_MDP_WROT0>; iommus =3D <&iommu M4U_PORT_MDP_WROT0>; + #dma-cells =3D <1>; }; =20 mdp3-wdma@14006000 { --=20 2.18.0 From nobody Fri Sep 20 09:49:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 923D9E7D0D5 for ; Fri, 22 Sep 2023 06:50:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230043AbjIVGup (ORCPT ); Fri, 22 Sep 2023 02:50:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229648AbjIVGuf (ORCPT ); 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Fri, 22 Sep 2023 14:50:20 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 22 Sep 2023 14:50:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 22 Sep 2023 14:50:18 +0800 From: Moudy Ho To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Moudy Ho Subject: [PATCH v6 2/2] arm64: dts: mediatek: mt8195: add MDP3 nodes Date: Fri, 22 Sep 2023 14:50:17 +0800 Message-ID: <20230922065017.10357-3-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230922065017.10357-1-moudy.ho@mediatek.com> References: <20230922065017.10357-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--8.986800-8.000000 X-TMASE-MatchedRID: k8Cd32tj8sGuhCBFl/b63kfhraIl1XgxkUtSee+57IFAtKM3hDDAfGb6 PphVtfZgTPeZkapFnH8kAzbREWz9my2w9y+uUSpWCz1WR8KHe4B3Bf9JIqsoeKkp8F/qKdS/o8W MkQWv6iXBcIE78YqRWo6HM5rqDwqtjj4YbMVy5eTpc/bTWgP1PgI0JuAvZeXuFJT7e5MiFS67sH 9dSDhp1w== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--8.986800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 30AC287EC04FD40ACA1105414F4A6B61C208B07CAB8000E43BE3DD52D45AFA272000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device nodes for Media Data Path 3 (MDP3) modules. Signed-off-by: Moudy Ho --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 388 +++++++++++++++++++++++ 1 file changed, 388 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 4dbbf8fdab75..cf61ba7b8956 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1960,6 +1960,114 @@ #clock-cells =3D <1>; }; =20 + dma-controller@14001000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + iommus =3D <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_RDMA>; + mboxes =3D <&gce1 12 CMDQ_THR_PRIO_1>, + <&gce1 13 CMDQ_THR_PRIO_1>, + <&gce1 14 CMDQ_THR_PRIO_1>, + <&gce1 21 CMDQ_THR_PRIO_1>, + <&gce1 22 CMDQ_THR_PRIO_1>; + #dma-cells =3D <1>; + }; + + display@14002000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14002000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_FG>; + }; + + display@14003000 { + compatible =3D "mediatek,mt8195-mdp3-stitch"; + reg =3D <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_STITCH>; + }; + + display@14004000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_HDR>; + }; + + display@14005000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14005000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14006000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys0 CLK_VPP0_MDP_RSZ>; + }; + + display@14007000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14007000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_TDSHP>; + }; + + display@14008000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14008000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14009000 { + compatible =3D "mediatek,mt8195-mdp3-ovl"; + reg =3D <0 0x14009000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_OVL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + iommus =3D <&iommu_vpp M4U_PORT_L4_MDP_OVL>; + }; + + display@1400a000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x1400a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_PADDING>; + }; + + display@1400b000 { + compatible =3D "mediatek,mt8195-mdp3-tcc"; + reg =3D <0 0x1400b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks =3D <&vppsys0 CLK_VPP0_MDP_TCC>; + }; + + dma-controller@1400c000 { + compatible =3D "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x1400c000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys0 CLK_VPP0_MDP_WROT>; + iommus =3D <&iommu_vpp M4U_PORT_L4_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + #dma-cells =3D <1>; + }; + mutex@1400f000 { compatible =3D "mediatek,mt8195-vpp-mutex"; reg =3D <0 0x1400f000 0 0x1000>; @@ -2107,6 +2215,286 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; }; =20 + display@14f06000 { + compatible =3D "mediatek,mt8195-mdp3-split"; + reg =3D <0 0x14f06000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_VPP_SPLIT>, + <&vppsys1 CLK_VPP1_HDMI_META>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f07000 { + compatible =3D "mediatek,mt8195-mdp3-tcc"; + reg =3D <0 0x14f07000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; + }; + + dma-controller@14f08000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f08000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f09000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f09000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f0a000 { + compatible =3D "mediatek,mt8195-mdp3-rdma"; + reg =3D <0 0x14f0a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; + iommus =3D <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + display@14f0b000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; + }; + + display@14f0c000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0c000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; + }; + + display@14f0d000 { + compatible =3D "mediatek,mt8195-mdp3-fg"; + reg =3D <0 0x14f0d000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; + }; + + display@14f0e000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f0e000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; + }; + + display@14f0f000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f0f000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; + }; + + display@14f10000 { + compatible =3D "mediatek,mt8195-mdp3-hdr"; + reg =3D <0 0x14f10000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; + }; + + display@14f11000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f11000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f12000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f12000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f13000 { + compatible =3D "mediatek,mt8195-mdp3-aal"; + reg =3D <0 0x14f13000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f14000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f14000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; + }; + + display@14f15000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f15000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; + }; + + display@14f16000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14f16000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; + }; + + display@14f17000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f17000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; + }; + + display@14f18000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f18000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; + }; + + display@14f19000 { + compatible =3D "mediatek,mt8195-mdp3-tdshp"; + reg =3D <0 0x14f19000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; + }; + + display@14f1a000 { + compatible =3D "mediatek,mt8195-mdp3-merge"; + reg =3D <0 0x14f1a000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1b000 { + compatible =3D "mediatek,mt8195-mdp3-merge"; + reg =3D <0 0x14f1b000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1c000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1c000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1d000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1d000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; + interrupts =3D ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1e000 { + compatible =3D "mediatek,mt8195-mdp3-color"; + reg =3D <0 0x14f1e000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1f000 { + compatible =3D "mediatek,mt8195-mdp3-ovl"; + reg =3D <0 0x14f1f000 0 0x1000>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>; + }; + + display@14f20000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x14f20000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; + }; + + display@14f21000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x14f21000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; + }; + + display@14f22000 { + compatible =3D "mediatek,mt8195-mdp3-pad"; + reg =3D <0 0x14f22000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; + }; + + dma-controller@14f23000 { + compatible =3D "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14f23000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f24000 { + compatible =3D "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14f24000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; + iommus =3D <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + + dma-controller@14f25000 { + compatible =3D "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14f25000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; + mediatek,gce-events =3D , + ; + clocks =3D <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; + iommus =3D <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells =3D <1>; + }; + imgsys: clock-controller@15000000 { compatible =3D "mediatek,mt8195-imgsys"; reg =3D <0 0x15000000 0 0x1000>; --=20 2.18.0