From nobody Fri Sep 20 12:35:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10E2EE7D0A0 for ; Thu, 21 Sep 2023 17:12:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230331AbjIURMP (ORCPT ); Thu, 21 Sep 2023 13:12:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231609AbjIURKj (ORCPT ); Thu, 21 Sep 2023 13:10:39 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 518CFAD21; Thu, 21 Sep 2023 10:06:01 -0700 (PDT) X-UUID: 71a730b6583f11ee8051498923ad61e6-20230921 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=DRztt0dJ9A8RuVogfdKc7sUF5lM6Wl4xKNWsz2Kfiyg=; b=liyU2c1m1JGM9xyNitmraY90RxNHdU0KIxwpFnanHA9Pe6461QCBM61+oryzTLv8ZLlKBjAbTkyuUXgvQFpRtzOjV3GW3kTDdIjRcEPX9rFZoLIfazrOQ1NSIMEhUumXDt/+x1T0uAMKzy2IecnSaivf8zleASm9Ic/qfW3aFhk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:42c7a0d8-690a-4758-8b1f-0b3314700430,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:c8a8f3ef-9a6e-4c39-b73e-f2bc08ca3dc5,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 71a730b6583f11ee8051498923ad61e6-20230921 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1962528436; Thu, 21 Sep 2023 13:26:40 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 21 Sep 2023 13:26:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 21 Sep 2023 13:26:39 +0800 From: Mark Tseng To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Roger Lu , Kevin Hilman CC: , , , , , Subject: [PATCH v4 2/3] soc: mediatek: svs: Add support for MT8188 SoC Date: Thu, 21 Sep 2023 13:26:36 +0800 Message-ID: <20230921052637.30444-3-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230921052637.30444-1-chun-jen.tseng@mediatek.com> References: <20230921052637.30444-1-chun-jen.tseng@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--9.945800-8.000000 X-TMASE-MatchedRID: GwmKcylEtt8Z+je+8a5/a38c8oKMbgYY0pVrZbbfikgTF8tEGMn0ovlY oV6p/cSxdlrF5BK8CswKDee6oJ8ihU9dh3PRYVY14RtSDjG+z7ChQhstwJ9G4L/A+0D1to6PxVi gu5lFVb73Asd/8PeGdX/OPC6s46aMdC+kmKoukpze0loolklf9acJxWZ5/lR8FLXUWU5hGiFynC +RoYX/O+LzNWBegCW2xl8lw85EaVQLbigRnpKlKSPzRlrdFGDwlS+LS7CPc8Y4ovxnM3kXzUM56 5Vek2hG1zkMaxsirfaLl/7MeQ305w== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--9.945800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 25074B410BDE680DF9FA0796F53ACECC46C4AB80961A7723E3214BCA3E42981F2000:8 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8188 svs gpu uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Mark Tseng Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 127 +++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 3a2f97cd5272..d2ae0b0cf95a 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1808,6 +1808,66 @@ static bool svs_mt8192_efuse_parsing(struct svs_plat= form *svsp) return true; } =20 +static bool svs_mt8188_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + u32 idx, i, golden_temp; + int ret; + + for (i =3D 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[5]) { + dev_notice(svsp->dev, "svs_efuse[5] =3D 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + + if (svsb->type =3D=3D SVSB_LOW) { + svsb->mtdes =3D svsp->efuse[5] & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[5] >> 16) & GENMASK(7, 0); + svsb->mdes =3D (svsp->efuse[5] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[15] >> 16) & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[15] >> 24) & GENMASK(7, 0); + } else if (svsb->type =3D=3D SVSB_HIGH) { + svsb->mtdes =3D svsp->efuse[4] & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[4] >> 16) & GENMASK(7, 0); + svsb->mdes =3D (svsp->efuse[4] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D svsp->efuse[14] & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[14] >> 8) & GENMASK(7, 0); + } + + svsb->vmax +=3D svsb->dvt_fixed; + } + + ret =3D svs_get_efuse_data(svsp, "t-calibration-data", + &svsp->tefuse, &svsp->tefuse_max); + if (ret) + return false; + + for (i =3D 0; i < svsp->tefuse_max; i++) + if (svsp->tefuse[i] !=3D 0) + break; + + if (i =3D=3D svsp->tefuse_max) + golden_temp =3D 50; /* All thermal efuse data are 0 */ + else + golden_temp =3D (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + svsb->mts =3D 500; + svsb->bts =3D (((500 * golden_temp + 250460) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2173,6 +2233,61 @@ static struct svs_bank svs_mt8192_banks[] =3D { }, }; =20 +static struct svs_bank svs_mt8188_banks[] =3D { + { + .sw_id =3D SVSB_GPU, + .type =3D SVSB_LOW, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support =3D SVSB_MODE_INIT02, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 640000000, + .turn_freq_base =3D 640000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x38, + .vmin =3D 0x1c, + .age_config =3D 0x555555, + .dc_config =3D 0x555555, + .dvt_fixed =3D 0x1, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0000, + .int_st =3D BIT(0), + .ctl0 =3D 0x00100003, + }, + { + .sw_id =3D SVSB_GPU, + .type =3D SVSB_HIGH, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .tzone_name =3D "gpu1", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 880000000, + .turn_freq_base =3D 640000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x38, + .vmin =3D 0x1c, + .age_config =3D 0x555555, + .dc_config =3D 0x555555, + .dvt_fixed =3D 0x4, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0001, + .int_st =3D BIT(1), + .ctl0 =3D 0x00100003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 0, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 7, + }, +}; + static struct svs_bank svs_mt8183_banks[] =3D { { .sw_id =3D SVSB_CPU_LITTLE, @@ -2286,6 +2401,15 @@ static const struct svs_platform_data svs_mt8192_pla= tform_data =3D { .bank_max =3D ARRAY_SIZE(svs_mt8192_banks), }; =20 +static const struct svs_platform_data svs_mt8188_platform_data =3D { + .name =3D "mt8188-svs", + .banks =3D svs_mt8188_banks, + .efuse_parsing =3D svs_mt8188_efuse_parsing, + .probe =3D svs_mt8192_platform_probe, + .regs =3D svs_regs_v2, + .bank_max =3D ARRAY_SIZE(svs_mt8188_banks), +}; + static const struct svs_platform_data svs_mt8183_platform_data =3D { .name =3D "mt8183-svs", .banks =3D svs_mt8183_banks, @@ -2299,6 +2423,9 @@ static const struct of_device_id svs_of_match[] =3D { { .compatible =3D "mediatek,mt8192-svs", .data =3D &svs_mt8192_platform_data, + }, { + .compatible =3D "mediatek,mt8188-svs", + .data =3D &svs_mt8188_platform_data, }, { .compatible =3D "mediatek,mt8183-svs", .data =3D &svs_mt8183_platform_data, --=20 2.18.0