From nobody Fri Dec 19 06:32:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D1F7CE79AB for ; Wed, 20 Sep 2023 09:46:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234211AbjITJqZ (ORCPT ); Wed, 20 Sep 2023 05:46:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234186AbjITJqU (ORCPT ); Wed, 20 Sep 2023 05:46:20 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC069A3 for ; Wed, 20 Sep 2023 02:46:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695203174; x=1726739174; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fPbsFBLao1m6KO+ew1b44zTXvTcP/hWch9xcabu50YM=; b=k1HxQzPYyiAEOv5PIi3JCHrGXXc2JcQZkipCIYOVpK55QcrAYb+Xxn9a JT9s+NEKzJ6wWCCFnPgwss7qI1LeHrWl1fk9ZH6XWlES+WpAgW5VJtyrn vubsHRE15IXYKNKC8QodQoFl9GGGnjVVOfjldPpeEBkWMj526LqFT01/M 1MwS+QYFudsi1yV4Z+5D5QUSjJwdEIYdTjDVt7vTM9N1yIIylxGOMPJ3Y aWa3iwEvZ9SSXlr/L1w1PGpMFy4VVBg8/+3lPucMBaXgpHw8RsQzVnkOw kNm557DAo3jc4Llet2cJNTtygA5GsnYdTOZDRQZqp86K+35wvAOm569Rt A==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="370491720" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="370491720" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 02:46:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="861911774" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="861911774" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 02:46:12 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Lucas De Marchi , Daniele Ceraolo Spurio , Rodrigo Vivi Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/4] drm/xe/gsc: add HECI2 register offsets Date: Wed, 20 Sep 2023 12:41:48 +0300 Message-Id: <20230920094151.1593505-2-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230920094151.1593505-1-alexander.usyskin@intel.com> References: <20230920094151.1593505-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vitaly Lubart Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h Reviewed-by: Rodrigo Vivi Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/regs/xe_regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe= _regs.h index 39d7b0740bf0..4cbc3062cb9a 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -33,6 +33,10 @@ #define XEHPC_BCS6_RING_BASE 0x3ea000 #define XEHPC_BCS7_RING_BASE 0x3ec000 #define XEHPC_BCS8_RING_BASE 0x3ee000 + +#define DG1_GSC_HECI2_BASE 0x00259000 +#define DG2_GSC_HECI2_BASE 0x00374000 + #define GSCCS_RING_BASE 0x11a000 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) --=20 2.34.1