From nobody Thu Nov 14 16:52:58 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4714CD3424 for ; Mon, 18 Sep 2023 09:39:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241042AbjIRJjK (ORCPT ); Mon, 18 Sep 2023 05:39:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240975AbjIRJig (ORCPT ); Mon, 18 Sep 2023 05:38:36 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68265120 for ; Mon, 18 Sep 2023 02:38:26 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-99de884ad25so568607066b.3 for ; Mon, 18 Sep 2023 02:38:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1695029905; x=1695634705; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LLilmH6KNML3mqOxoMEotqYRiNUYNeaDDiuGijBala4=; b=RS08wUizzhyHQxvhTVbIzkui+ZUwpvU4uHrQFLLFsvcV6h0a0gr86I+gmL2UjrSRYb LqKd6SXZBk8gfY6Y7auX52fDUS/dj1iIEb6VnwfxDW665QHdgmOdTSb718mQ9k3DF/2R XmcKR5B9S8wYzLkxDme6HI/+Hb0tfk0bETjyjog4a6x+9ilaMMvDefj62CxWxT+zMRey V4W0LzjgVYi8/fCc/juc33NzTu/3YB/nnMryW117M2SCs7lar1WnHrBEJwKpfHIcPyis I/KI0xL9FLPv2zBgI/ddYoQG89ocDo3bBO/VeVUcaevAI2morn26Cw7qcWIoallWbHmb U/gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695029905; x=1695634705; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LLilmH6KNML3mqOxoMEotqYRiNUYNeaDDiuGijBala4=; b=CvcDvyqf/MXj8oUVZJ6nRAVzdcMEKQoU/9t9i3CaS67hSZj9aQx5jDVVIZoxpz3zud 04jfj9sKDh6S0W4S0j4CWDDj/CMsVNlaEaMaedmOvXp/aMWuu3wUDEJgJnlSiC+bcpDv Ubeg67vIpLYeYrLAIPK13CL9TAHPgmjC0aAWwec1nHLfNfrWJEHPqprUybKVKlSMqqB8 nzVsSyxHu/UId5qR6gbe25Ur13xBxe3InrQt8Fkw/IRYXIk0hE5TTMYg4S3fE0gHMdqy 7irINlpQqE9Mppmfj1DfRb0lKBmz54jRq/txf3EXP7LyM4vRp4JaNofjBTLYr8gNjxKp 7yng== X-Gm-Message-State: AOJu0YxluZ+DojepUZAG72Vc111QVKIuvYUzAq95BQV2G6DvZLtA6iHJ gJ3eyEfMjXUzyHkw7qGCR1KX2A== X-Google-Smtp-Source: AGHT+IHo7uRZxnUYKgzvfn7oJLB+FQSSEMySz37yIq63ZWajaSCSobNXrakxfVE1UnmFwrktsIyVrA== X-Received: by 2002:a17:907:789a:b0:9ad:e66a:413c with SMTP id ku26-20020a170907789a00b009ade66a413cmr5729797ejc.48.1695029904885; Mon, 18 Sep 2023 02:38:24 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4091:a246:8222:872:4a5b:b69c:1318]) by smtp.gmail.com with ESMTPSA id o10-20020a1709061d4a00b0099293cdbc98sm6251164ejh.145.2023.09.18.02.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Sep 2023 02:38:24 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: Ulf Hansson , Alexandre Mergnat , Chun-Jie Chen , AngeloGioacchino Del Regno , Tinghan Shen , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon , Fabien Parent , Markus Schneider-Pargmann Subject: [PATCH v8 6/8] soc: mediatek: Add support for WAY_EN operations Date: Mon, 18 Sep 2023 11:37:50 +0200 Message-Id: <20230918093751.1188668-7-msp@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230918093751.1188668-1-msp@baylibre.com> References: <20230918093751.1188668-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexandre Bailon This updates the power domain to support WAY_EN operations. WAY_EN operations on mt8365 are using a different component to check for the acknowledgment, namely the infracfg-nao component. Also to enable a way it the bit needs to be cleared while disabling a way needs a bit to be set. To support these two operations two flags are added, BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally another regmap is created if the INFRA_NAO capability is set. This operation is required by the mt8365 for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++--- drivers/pmdomain/mediatek/mtk-pm-domains.h | 3 ++ 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/= mediatek/mtk-pm-domains.c index c1154de98830..4bf3a375b749 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -44,6 +44,7 @@ struct scpsys_domain { struct clk_bulk_data *clks; int num_subsys_clks; struct clk_bulk_data *subsys_clks; + struct regmap *infracfg_nao; struct regmap *infracfg; struct regmap *smi; struct regulator *supply; @@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(s= truct scpsys_domain *pd, return pd->infracfg; } =20 +static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_doma= in *pd, + const struct scpsys_bus_prot_data *bpd) +{ + if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO) + return pd->infracfg_nao; + else + return scpsys_bus_protect_get_regmap(pd, bpd); +} + static int scpsys_bus_protect_clear(struct scpsys_domain *pd, const struct scpsys_bus_prot_data *bpd) { + struct regmap *sta_regmap =3D scpsys_bus_protect_get_sta_regmap(pd, bpd); struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); u32 sta_mask =3D bpd->bus_prot_sta_mask; + u32 expected_ack; u32 val; =20 + expected_ack =3D (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mas= k : 0); + if (bpd->flags & BUS_PROT_REG_UPDATE) regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); else @@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_dom= ain *pd, if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK) return 0; =20 - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, - val, !(val & sta_mask), + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, + val, (val & sta_mask) =3D=3D expected_ack, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 static int scpsys_bus_protect_set(struct scpsys_domain *pd, const struct scpsys_bus_prot_data *bpd) { + struct regmap *sta_regmap =3D scpsys_bus_protect_get_sta_regmap(pd, bpd); struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); u32 sta_mask =3D bpd->bus_prot_sta_mask; u32 val; @@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain = *pd, else regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); =20 - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, val, (val & sta_mask) =3D=3D sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } @@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_dom= ain *pd) if (!bpd->bus_prot_set_clr_mask) break; =20 - ret =3D scpsys_bus_protect_set(pd, bpd); + if (bpd->flags & BUS_PROT_INVERTED) + ret =3D scpsys_bus_protect_clear(pd, bpd); + else + ret =3D scpsys_bus_protect_set(pd, bpd); if (ret) return ret; } @@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_do= main *pd) if (!bpd->bus_prot_set_clr_mask) continue; =20 - ret =3D scpsys_bus_protect_clear(pd, bpd); + if (bpd->flags & BUS_PROT_INVERTED) + ret =3D scpsys_bus_protect_set(pd, bpd); + else + ret =3D scpsys_bus_protect_clear(pd, bpd); if (ret) return ret; } @@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys= *scpsys, struct device_no return ERR_CAST(pd->smi); } =20 + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) { + pd->infracfg_nao =3D syscon_regmap_lookup_by_phandle(node, "mediatek,inf= racfg-nao"); + if (IS_ERR(pd->infracfg_nao)) + return ERR_CAST(pd->infracfg_nao); + } else { + pd->infracfg_nao =3D NULL; + } + num_clks =3D of_clk_get_parent_count(node); if (num_clks > 0) { /* Calculate number of subsys_clks */ diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/= mediatek/mtk-pm-domains.h index 209f68dcaeac..17c033217704 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -11,6 +11,7 @@ /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) #define MTK_SCPD_EXT_BUCK_ISO BIT(6) +#define MTK_SCPD_HAS_INFRA_NAO BIT(7) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -45,8 +46,10 @@ enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE =3D BIT(1), BUS_PROT_IGNORE_CLR_ACK =3D BIT(2), + BUS_PROT_INVERTED =3D BIT(3), BUS_PROT_COMPONENT_INFRA =3D BIT(4), BUS_PROT_COMPONENT_SMI =3D BIT(5), + BUS_PROT_STA_COMPONENT_INFRA_NAO =3D BIT(6), }; =20 #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ --=20 2.40.1