From nobody Thu Feb 12 06:41:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42144EE020C for ; Fri, 15 Sep 2023 02:17:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231609AbjIOCRV (ORCPT ); Thu, 14 Sep 2023 22:17:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231772AbjIOCRG (ORCPT ); Thu, 14 Sep 2023 22:17:06 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 459C62D53; Thu, 14 Sep 2023 19:17:00 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38F1vjdb031638; Fri, 15 Sep 2023 02:16:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=4g+QORFF76ZfWsHBcB4mVPvnWyc4sJCKXGtdQn0dNz0=; b=Uowb6CZ3BSwBCgkWOE2i9HTb/mOOcFS1bweyoWfxLHygnVJPX8s+f3EYCkSUyg0EiW7t Sb8y7MOmbLiovMpMR37M5PnHsYSWtLd8R457EvBWPbOuR5hf5WHD1TOlz9H3Dm8o2Jvm 5VrylCUlAD6SFP8qXGsSBWkeFZWnTs6n7zN9CYaRMEdhpBbkBn8E7GLOz9NTrtK4fxHy FByl30v3zzON1U/NEFtLWBdMKJ5z92oqovrE7Q64xoJzXCAEJ6UKE7TJV46Sl4IOuSLD wTAaTy/gdjzOMjppn6NdtN1PccXSmFrq8hjkOTZxuQHjWv52Ewf/Dd7gtGyut0otFkF0 KQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t4e2b01j0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Sep 2023 02:16:38 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38F2GbvY017116 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Sep 2023 02:16:37 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 14 Sep 2023 19:16:28 -0700 From: Tengfei Fan To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , Tengfei Fan Subject: [PATCH v2 7/8] arm64: dts: qcom: add uart console support for SM4450 Date: Fri, 15 Sep 2023 10:15:08 +0800 Message-ID: <20230915021509.25773-9-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230915021509.25773-1-quic_tengfan@quicinc.com> References: <20230915021509.25773-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: UlfP3JkXXVsbq4T2UByZ8f4tpp8urihd X-Proofpoint-ORIG-GUID: UlfP3JkXXVsbq4T2UByZ8f4tpp8urihd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-15_02,2023-09-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309150018 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add base description of UART, TLMM, interconnect, TCSRCC and SMMU nodes which helps SM4450 boot to shell with console on boards with this SoC. Signed-off-by: Tengfei Fan --- arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 +- arch/arm64/boot/dts/qcom/sm4450.dtsi | 313 +++++++++++++++++++++--- 2 files changed, 301 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/= qcom/sm4450-qrd.dts index 00a1c81ca397..0f253a2ba170 100644 --- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts @@ -10,9 +10,23 @@ model =3D "Qualcomm Technologies, Inc. SM4450 QRD"; compatible =3D "qcom,sm4450-qrd", "qcom,sm4450"; =20 - aliases { }; + aliases { + serial0 =3D &uart7; + }; =20 chosen { - bootargs =3D "console=3Dhvc0"; + stdout-path =3D "serial0:115200n8"; }; }; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&tlmm { + gpio-reserved-ranges =3D <0 4>, <136 1>; +}; + +&uart7 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qco= m/sm4450.dtsi index df59027a2f93..3af976478d0d 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include =20 / { @@ -262,6 +264,26 @@ }; }; =20 + firmware { + scm: scm { + compatible =3D "qcom,scm-sm4450", "qcom,scm"; + interconnects =3D <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + #reset-cells =3D <1>; + }; + }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,sm4450-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible =3D "qcom,sm4450-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + memory@a0000000 { device_type =3D "memory"; /* We expect the bootloader to fill in the size */ @@ -350,34 +372,6 @@ dma-ranges =3D <0 0 0 0 0x10 0>; compatible =3D "simple-bus"; =20 - apps_rsc: rsc@17a00000 { - compatible =3D "qcom,rpmh-rsc"; - reg =3D <0 0x17a00000 0 0x10000>, - <0 0x17a10000 0 0x10000>, - <0 0x17a20000 0 0x10000>; - reg-names =3D "drv-0", "drv-1", "drv-2"; - interrupts =3D , - , - ; - label =3D "apps_rsc"; - qcom,tcs-offset =3D <0xd00>; - qcom,drv-id =3D <2>; - qcom,tcs-config =3D , , - , ; - power-domains =3D <&CLUSTER_PD>; - - apps_bcm_voter: bcm-voter { - compatible =3D "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible =3D "qcom,sm4450-rpmh-clk"; - #clock-cells =3D <1>; - clock-names =3D "xo"; - clocks =3D <&xo_board>; - }; - }; - gcc: clock-controller@100000 { compatible =3D "qcom,sm4450-gcc"; reg =3D <0x0 0x00100000 0x0 0x1f4200>; @@ -387,12 +381,111 @@ clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; }; =20 + qupv3_id_0: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x2000>; + ranges; + clock-names =3D "m-ahb", "s-ahb"; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus =3D <&apps_smmu 0x163 0x0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CO= RE_0 0>; + interconnect-names =3D "qup-core"; + #address-cells =3D <2>; + #size-cells =3D <2>; + status =3D "disabled"; + + uart7: serial@a88000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0 0x00a88000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_uart7_tx>, <&qup_uart7_rx>; + status =3D "disabled"; + }; + }; + + cnoc2: interconnect@1500000 { + compatible =3D "qcom,sm4450-cnoc2"; + reg =3D <0 0x1500000 0 0x6200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + cnoc3: interconnect@1510000 { + compatible =3D "qcom,sm4450-cnoc3"; + reg =3D <0 0x01510000 0 0xF200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,sm4450-system-noc"; + reg =3D <0 0x1680000 0 0x19080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@16c0000 { + compatible =3D "qcom,sm4450-pcie-anoc"; + reg =3D <0 0x16C0000 0 0x7080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + }; + + aggre1_noc: interconnect@16e0000 { + tible =3D "qcom,sm4450-aggre1-noc"; + reg =3D <0 0x016e0000 0 0x1c080>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,sm4450-aggre2-noc"; + reg =3D <0 0x01700000 0 0x31080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&rpmhcc RPMH_IPA_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + }; + + mmss_noc: interconnect@1740000 { + compatible =3D "qcom,sm4450-mmss-noc"; + reg =3D <0 0x1740000 0 0x19080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + video_aggre_noc: interconnect@1760000 { + compatible =3D "qcom,sm4450-video-aggre-noc"; + reg =3D <0 0x1760000 0 0x1100>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0x0 0x01f40000 0x0 0x40000>; #hwlock-cells =3D <1>; }; =20 + tcsr: syscon@1fc0000 { + compatible =3D "qcom,sm4450-tcsr", "syscon"; + reg =3D <0x0 0x1fc0000 0x0 0x30000>; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible =3D "qcom,sm4450-lpass-ag-noc"; + reg =3D <0 0x3C40000 0 0x17200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm4450-pdc", "qcom,pdc"; reg =3D <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; @@ -403,6 +496,135 @@ interrupt-controller; }; =20 + tlmm: pinctrl@f100000 { + compatible =3D "qcom,sm4450-tlmm"; + reg =3D <0 0x0f100000 0 0x300000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 137>; + wakeup-parent =3D <&pdc>; + + qup_uart7_rx: qup-uart7-rx-state { + pins =3D "gpio22"; + function =3D "qup1_se2_l2"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins =3D "gpio22"; + function =3D "qup1_se2_l2"; + drive-strength =3D <2>; + bias-disable; + }; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,sm4450-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0 0x15000000 0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17200000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0x17200000 0x0 0x10000>, /* GICD */ @@ -471,6 +693,41 @@ status =3D "disabled"; }; }; + + apps_rsc: rsc@17a00000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0 0x17a00000 0 0x10000>, + <0 0x17a10000 0 0x10000>, + <0 0x17a20000 0 0x10000>; + reg-names =3D "drv-0", "drv-1", "drv-2"; + interrupts =3D , + , + ; + label =3D "apps_rsc"; + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , , + , ; + power-domains =3D <&CLUSTER_PD>; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,sm4450-rpmh-clk"; + #clock-cells =3D <1>; + clock-names =3D "xo"; + clocks =3D <&xo_board>; + }; + }; + + gem_noc: interconnect@19100000 { + compatible =3D "qcom,sm4450-gem-noc"; + reg =3D <0 0x19100000 0 0xBC080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; }; =20 timer { --=20 2.17.1