From nobody Thu Feb 12 02:01:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C875EE0211 for ; Wed, 13 Sep 2023 21:05:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232755AbjIMVFr (ORCPT ); Wed, 13 Sep 2023 17:05:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232757AbjIMVFp (ORCPT ); Wed, 13 Sep 2023 17:05:45 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9CD81BCE for ; Wed, 13 Sep 2023 14:05:41 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-26b44247123so215837a91.2 for ; Wed, 13 Sep 2023 14:05:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1694639141; x=1695243941; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tv4HEesTHW83aQBsr6P2xoLUTJCnxlrDYoQTHgTGZUs=; b=yMMVHq3w7jKxBpZjbaflfAxAPqVheqSLwcu/9+Bg8Nfv2TK5wrbljw2K76nukd0WcO Rk+6sMdAjtjn9qrxLwbaIoaVBQIAASWOf3FkLSTc6Bh8wL3ZEWe0sNCoT2CQ67h6wbSQ DhF69jDcYPl/373rbdmMrLBnc9Hg6sFuqHKCmj0dRWZ+mqanvfcf0g32LERHwKmNQzSF +UAZy+is8KTC/0ApbScye4GHNCQHKFsw4mIeQTYlT9VRD/qJ9NY3JhzcCVpMEdfjFcDu ueVOo4D8eVqQuk3SK+pORG4ts2DIRLQRyv7sCpaKsfHD18IDR5RtxmU+d+I2mZ8YJwfz ClDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694639141; x=1695243941; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tv4HEesTHW83aQBsr6P2xoLUTJCnxlrDYoQTHgTGZUs=; b=sOg22YsobcAkw140Xv+Io3WxxSWBwhDAY6CUBLzXMtw4V4Q7a+FHDrDkwdBuGlO3Tq 495r8vGWUifereZhG49+NQf5dEKIbPVQCcftnOJw6RpYwmINnGSgpaSj2nLNR0AqWPr5 bIS+S++ElRVvpbZC+ZC3A3/XVPqixX+Pj1GVgU6xFDv79WvNQQbW93ps3rmVZD6HblRa oXD1MP4jXelyUdk1uAceawKKtO9xaz+MWHfNu2jxV46/NVnNknREU8zIPTLsMMi8T0xn aOGt6xSVWhJaKKJcX4V1utvXyCR5AQ3ieHIRSHIXj548jYTkN70O4zKNbamZ7ItmRP7L VMTQ== X-Gm-Message-State: AOJu0YxBaCautntQcny/PN7sLMszlqDHznjfVRAu3lEEKxoi+/BfZgQC i16M96gJ5Xi2wfZi76P6qMl//w== X-Google-Smtp-Source: AGHT+IH2HbmEtNOynkX0zr0oLruKiSRDM4H7cJW1h7yisDs6ojif78Cju0rEahVIqL0qD3qnbuibtg== X-Received: by 2002:a17:90b:4ad0:b0:262:ee7d:2d20 with SMTP id mh16-20020a17090b4ad000b00262ee7d2d20mr3514022pjb.12.1694639141273; Wed, 13 Sep 2023 14:05:41 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id z16-20020a170903019000b001ab2b4105ddsm66323plg.60.2023.09.13.14.05.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Sep 2023 14:05:40 -0700 (PDT) From: Charlie Jenkins Date: Wed, 13 Sep 2023 14:04:49 -0700 Subject: [PATCH 1/2] riscv: Add remaining module relocations MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230913-module_relocations-v1-1-bb3d8467e793@rivosinc.com> References: <20230913-module_relocations-v1-0-bb3d8467e793@rivosinc.com> In-Reply-To: <20230913-module_relocations-v1-0-bb3d8467e793@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add all final module relocations and add error logs explaining the ones that are not supported. Signed-off-by: Charlie Jenkins --- arch/riscv/include/uapi/asm/elf.h | 6 +- arch/riscv/kernel/module.c | 191 +++++++++++++++++++++++++++++++++-= ---- 2 files changed, 171 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/as= m/elf.h index d696d6610231..a9307a1c9ceb 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -49,6 +49,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_TLS_DTPREL64 9 #define R_RISCV_TLS_TPREL32 10 #define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_IRELATIVE 58 =20 /* Relocation types not used by the dynamic linker */ #define R_RISCV_BRANCH 16 @@ -81,7 +82,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_ALIGN 43 #define R_RISCV_RVC_BRANCH 44 #define R_RISCV_RVC_JUMP 45 -#define R_RISCV_LUI 46 +#define R_RISCV_RVC_LUI 46 #define R_RISCV_GPREL_I 47 #define R_RISCV_GPREL_S 48 #define R_RISCV_TPREL_I 49 @@ -93,6 +94,9 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_SET16 55 #define R_RISCV_SET32 56 #define R_RISCV_32_PCREL 57 +#define R_RISCV_PLT32 59 +#define R_RISCV_SET_ULEB128 60 +#define R_RISCV_SUB_ULEB128 61 =20 =20 #endif /* _UAPI_ASM_RISCV_ELF_H */ diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 7c651d55fcbd..7c0cb03b9035 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -253,6 +253,30 @@ static int apply_r_riscv_call_rela(struct module *me, = u32 *location, return 0; } =20 +static int apply_r_riscv_rvc_lui_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + // Get high 6 bits of 18 bit absolute address + s32 imm =3D ((s32)v + 0x800) >> 12; + + if (v !=3D sign_extend32(v, 6)) { + pr_err("%s: target %016llx can not be addressed by the 6-bit offset from= PC =3D %p\n", + me->name, (long long)v, location); + return -EINVAL; + } + + if (imm =3D=3D 0) { + // imm =3D 0 is invalid for c.lui, convert to c.li + *location =3D (*location & 0x0F83) | 0x4000; + } else { + u16 imm17 =3D ((((s32)v + 0x800) & 0x20000) >> (17 - 12)); + u16 imm16_12 =3D ((((s32)v + 0x800) & 0x1f000) >> (12 - 2)); + *location =3D (*location & 0xef83) | imm17 | imm16_12; + } + + return 0; +} + static int apply_r_riscv_relax_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -268,6 +292,12 @@ static int apply_r_riscv_align_rela(struct module *me,= u32 *location, return -EINVAL; } =20 +static int apply_r_riscv_add8_rela(struct module *me, u32 *location, Elf_A= ddr v) +{ + *(u8 *)location +=3D (u8)v; + return 0; +} + static int apply_r_riscv_add16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -289,6 +319,12 @@ static int apply_r_riscv_add64_rela(struct module *me,= u32 *location, return 0; } =20 +static int apply_r_riscv_sub8_rela(struct module *me, u32 *location, Elf_A= ddr v) +{ + *(u8 *)location -=3D (u8)v; + return 0; +} + static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -310,31 +346,136 @@ static int apply_r_riscv_sub64_rela(struct module *m= e, u32 *location, return 0; } =20 -static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, - Elf_Addr v) =3D { - [R_RISCV_32] =3D apply_r_riscv_32_rela, - [R_RISCV_64] =3D apply_r_riscv_64_rela, - [R_RISCV_BRANCH] =3D apply_r_riscv_branch_rela, - [R_RISCV_JAL] =3D apply_r_riscv_jal_rela, - [R_RISCV_RVC_BRANCH] =3D apply_r_riscv_rvc_branch_rela, - [R_RISCV_RVC_JUMP] =3D apply_r_riscv_rvc_jump_rela, - [R_RISCV_PCREL_HI20] =3D apply_r_riscv_pcrel_hi20_rela, - [R_RISCV_PCREL_LO12_I] =3D apply_r_riscv_pcrel_lo12_i_rela, - [R_RISCV_PCREL_LO12_S] =3D apply_r_riscv_pcrel_lo12_s_rela, - [R_RISCV_HI20] =3D apply_r_riscv_hi20_rela, - [R_RISCV_LO12_I] =3D apply_r_riscv_lo12_i_rela, - [R_RISCV_LO12_S] =3D apply_r_riscv_lo12_s_rela, - [R_RISCV_GOT_HI20] =3D apply_r_riscv_got_hi20_rela, - [R_RISCV_CALL_PLT] =3D apply_r_riscv_call_plt_rela, - [R_RISCV_CALL] =3D apply_r_riscv_call_rela, - [R_RISCV_RELAX] =3D apply_r_riscv_relax_rela, - [R_RISCV_ALIGN] =3D apply_r_riscv_align_rela, - [R_RISCV_ADD16] =3D apply_r_riscv_add16_rela, - [R_RISCV_ADD32] =3D apply_r_riscv_add32_rela, - [R_RISCV_ADD64] =3D apply_r_riscv_add64_rela, - [R_RISCV_SUB16] =3D apply_r_riscv_sub16_rela, - [R_RISCV_SUB32] =3D apply_r_riscv_sub32_rela, - [R_RISCV_SUB64] =3D apply_r_riscv_sub64_rela, +static int dynamic_linking_not_supported(struct module *me, u32 *location, + Elf_Addr v) +{ + pr_err("%s: Dynamic linking not supported in kernel modules PC =3D %p\n", + me->name, location); + return -EINVAL; +} + +static int tls_not_supported(struct module *me, u32 *location, Elf_Addr v) +{ + pr_err("%s: Thread local storage not supported in kernel modules PC =3D %= p\n", + me->name, location); + return -EINVAL; +} + +static int apply_r_riscv_sub6_rela(struct module *me, u32 *location, Elf_A= ddr v) +{ + *(u8 *)location -=3D (u8)v & 0x3F; + return 0; +} + +static int apply_r_riscv_set6_rela(struct module *me, u32 *location, Elf_A= ddr v) +{ + *(u8 *)location =3D (*(u8 *)location & 0xc0) | ((u8)v & 0x3F); + return 0; +} + +static int apply_r_riscv_set8_rela(struct module *me, u32 *location, Elf_A= ddr v) +{ + *(u8 *)location =3D (u8)v; + return 0; +} + +static int apply_r_riscv_set16_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u16 *)location =3D (u16)v; + return 0; +} + +static int apply_r_riscv_set32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location =3D (u32)v; + return 0; +} + +static int apply_r_riscv_32_pcrel_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location =3D (u32)v; + return 0; +} + +static int apply_r_riscv_plt32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location =3D (u32)v; + return 0; +} + +static int uleb128_not_supported(struct module *me, u32 *location, Elf_Add= r v) +{ + pr_err("%s: R_RISCV_SET_ULEB128 and R_RISCV_SUB_ULEB128 not supported PC = =3D %p\n", + me->name, location); + return -EINVAL; +} + +/* + * Relocations defined in the riscv-elf-psabi-doc. + * This handles static linking only. + */ +static int (*reloc_handlers_rela[])(struct module *me, u32 *location, + Elf_Addr v) =3D { + [R_RISCV_32] =3D apply_r_riscv_32_rela, + [R_RISCV_64] =3D apply_r_riscv_64_rela, + [R_RISCV_RELATIVE] =3D dynamic_linking_not_supported, + [R_RISCV_COPY] =3D dynamic_linking_not_supported, + [R_RISCV_JUMP_SLOT] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD64] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL64] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL32] =3D dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL64] =3D dynamic_linking_not_supported, + /* 12-15 undefined */ + [R_RISCV_BRANCH] =3D apply_r_riscv_branch_rela, + [R_RISCV_JAL] =3D apply_r_riscv_jal_rela, + [R_RISCV_CALL] =3D apply_r_riscv_call_rela, + [R_RISCV_CALL_PLT] =3D apply_r_riscv_call_plt_rela, + [R_RISCV_GOT_HI20] =3D apply_r_riscv_got_hi20_rela, + [R_RISCV_TLS_GOT_HI20] =3D tls_not_supported, + [R_RISCV_TLS_GD_HI20] =3D tls_not_supported, + [R_RISCV_PCREL_HI20] =3D apply_r_riscv_pcrel_hi20_rela, + [R_RISCV_PCREL_LO12_I] =3D apply_r_riscv_pcrel_lo12_i_rela, + [R_RISCV_PCREL_LO12_S] =3D apply_r_riscv_pcrel_lo12_s_rela, + [R_RISCV_HI20] =3D apply_r_riscv_hi20_rela, + [R_RISCV_LO12_I] =3D apply_r_riscv_lo12_i_rela, + [R_RISCV_LO12_S] =3D apply_r_riscv_lo12_s_rela, + [R_RISCV_TPREL_HI20] =3D tls_not_supported, + [R_RISCV_TPREL_LO12_I] =3D tls_not_supported, + [R_RISCV_TPREL_LO12_S] =3D tls_not_supported, + [R_RISCV_TPREL_ADD] =3D tls_not_supported, + [R_RISCV_ADD8] =3D apply_r_riscv_add8_rela, + [R_RISCV_ADD16] =3D apply_r_riscv_add16_rela, + [R_RISCV_ADD32] =3D apply_r_riscv_add32_rela, + [R_RISCV_ADD64] =3D apply_r_riscv_add64_rela, + [R_RISCV_SUB8] =3D apply_r_riscv_sub8_rela, + [R_RISCV_SUB16] =3D apply_r_riscv_sub16_rela, + [R_RISCV_SUB32] =3D apply_r_riscv_sub32_rela, + [R_RISCV_SUB64] =3D apply_r_riscv_sub64_rela, + /* 41-42 reserved for future standard use */ + [R_RISCV_ALIGN] =3D apply_r_riscv_align_rela, + [R_RISCV_RVC_BRANCH] =3D apply_r_riscv_rvc_branch_rela, + [R_RISCV_RVC_JUMP] =3D apply_r_riscv_rvc_jump_rela, + [R_RISCV_RVC_LUI] =3D apply_r_riscv_rvc_lui_rela, + /* 47-50 reserved for future standard use */ + [R_RISCV_RELAX] =3D apply_r_riscv_relax_rela, + [R_RISCV_SUB6] =3D apply_r_riscv_sub6_rela, + [R_RISCV_SET6] =3D apply_r_riscv_set6_rela, + [R_RISCV_SET8] =3D apply_r_riscv_set8_rela, + [R_RISCV_SET16] =3D apply_r_riscv_set16_rela, + [R_RISCV_SET32] =3D apply_r_riscv_set32_rela, + [R_RISCV_32_PCREL] =3D apply_r_riscv_32_pcrel_rela, + [R_RISCV_IRELATIVE] =3D dynamic_linking_not_supported, + [R_RISCV_PLT32] =3D apply_r_riscv_plt32_rela, + [R_RISCV_SET_ULEB128] =3D uleb128_not_supported, + [R_RISCV_SUB_ULEB128] =3D uleb128_not_supported, + /* 62-191 reserved for future standard use */ + /* 192-255 nonstandard ABI extensions */ }; =20 int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, --=20 2.34.1 From nobody Thu Feb 12 02:01:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BD81EE020D for ; Wed, 13 Sep 2023 21:05:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232789AbjIMVFu (ORCPT ); Wed, 13 Sep 2023 17:05:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232759AbjIMVFr (ORCPT ); Wed, 13 Sep 2023 17:05:47 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F06C19B for ; Wed, 13 Sep 2023 14:05:42 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1c3bd829b86so2021125ad.0 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230913-module_relocations-v1-2-bb3d8467e793@rivosinc.com> References: <20230913-module_relocations-v1-0-bb3d8467e793@rivosinc.com> In-Reply-To: <20230913-module_relocations-v1-0-bb3d8467e793@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add test cases for the two main groups of relocations added: SUB and SET. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.debug | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/tests/Kconfig.debug | 32 +++++++++++ arch/riscv/kernel/tests/Makefile | 1 + arch/riscv/kernel/tests/module_test/Makefile | 11 ++++ .../tests/module_test/test_module_linking_main.c | 64 ++++++++++++++++++= ++++ arch/riscv/kernel/tests/module_test/test_set16.S | 23 ++++++++ arch/riscv/kernel/tests/module_test/test_set32.S | 20 +++++++ arch/riscv/kernel/tests/module_test/test_set6.S | 23 ++++++++ arch/riscv/kernel/tests/module_test/test_set8.S | 23 ++++++++ arch/riscv/kernel/tests/module_test/test_sub16.S | 22 ++++++++ arch/riscv/kernel/tests/module_test/test_sub32.S | 22 ++++++++ arch/riscv/kernel/tests/module_test/test_sub6.S | 22 ++++++++ arch/riscv/kernel/tests/module_test/test_sub64.S | 27 +++++++++ arch/riscv/kernel/tests/module_test/test_sub8.S | 22 ++++++++ 15 files changed, 314 insertions(+) diff --git a/arch/riscv/Kconfig.debug b/arch/riscv/Kconfig.debug index e69de29bb2d1..eafe17ebf710 100644 --- a/arch/riscv/Kconfig.debug +++ b/arch/riscv/Kconfig.debug @@ -0,0 +1 @@ +source "arch/riscv/kernel/tests/Kconfig.debug" diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 6ac56af42f4a..8310f62732fe 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -56,6 +56,7 @@ obj-y +=3D stacktrace.o obj-y +=3D cacheinfo.o obj-y +=3D patch.o obj-y +=3D probes/ +obj-y +=3D tests/ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ =20 obj-$(CONFIG_RISCV_M_MODE) +=3D traps_misaligned.o diff --git a/arch/riscv/kernel/tests/Kconfig.debug b/arch/riscv/kernel/test= s/Kconfig.debug new file mode 100644 index 000000000000..05ca55fb4645 --- /dev/null +++ b/arch/riscv/kernel/tests/Kconfig.debug @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "arch/riscv/kernel Testing and Coverage" + +menuconfig RUNTIME_KERNEL_TESTING_MENU + bool "arch/riscv/kernel runtime Testing" + def_bool y + help + Enable riscv kernel runtime testing. + +if RUNTIME_KERNEL_TESTING_MENU + +config RISCV_MODULE_LINKING_KUNIT + bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TES= TS + depends on KUNIT + default KUNIT_ALL_TESTS + help + Enable this option to test riscv module linking at boot. This will + enable a module called "test_module_linking". + + KUnit tests run during boot and output the results to the debug l= og + in TAP format (http://testanything.org/). Only useful for kernel = devs + running the KUnit test harness, and not intended for inclusion in= to a + production build. + + For more information on KUnit and unit tests in general please re= fer + to the KUnit documentation in Documentation/dev-tools/kunit/. + + If unsure, say N. + +endif # RUNTIME_TESTING_MENU + +endmenu # "arch/riscv/kernel runtime Testing" diff --git a/arch/riscv/kernel/tests/Makefile b/arch/riscv/kernel/tests/Mak= efile new file mode 100644 index 000000000000..7d6c76cffe20 --- /dev/null +++ b/arch/riscv/kernel/tests/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_RISCV_MODULE_LINKING_KUNIT) +=3D module_test/ diff --git a/arch/riscv/kernel/tests/module_test/Makefile b/arch/riscv/kern= el/tests/module_test/Makefile new file mode 100644 index 000000000000..4b54978468ec --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/Makefile @@ -0,0 +1,11 @@ +obj-m +=3D test_module_linking.o + +test_sub :=3D test_sub6.o test_sub8.o test_sub16.o test_sub32.o test_sub64= .o + +test_set :=3D test_set6.o test_set8.o test_set16.o test_set32.o + +test_module_linking-objs +=3D $(test_sub) + +test_module_linking-objs +=3D $(test_set) + +test_module_linking-objs +=3D test_module_linking_main.o diff --git a/arch/riscv/kernel/tests/module_test/test_module_linking_main.c= b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c new file mode 100644 index 000000000000..61e053520b83 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Rivos Inc. + */ + +#include +#include +#include +#include + +MODULE_LICENSE("GPL"); + +extern int test_set32(void); +extern int test_set16(void); +extern int test_set8(void); +extern int test_set6(void); +extern long test_sub64(void); +extern int test_sub32(void); +extern int test_sub16(void); +extern int test_sub8(void); +extern int test_sub6(void); + +#define CHECK_EQ(lhs, rhs) KUNIT_ASSERT_EQ(test, lhs, rhs) + +void run_test_set(struct kunit *test) +{ + int val32 =3D test_set32(); + int val16 =3D test_set16(); + int val8 =3D test_set8(); + int val6 =3D test_set6(); + + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +void run_test_sub(struct kunit *test) +{ + int val64 =3D test_sub64(); + int val32 =3D test_sub32(); + int val16 =3D test_sub16(); + int val8 =3D test_sub8(); + int val6 =3D test_sub6(); + + CHECK_EQ(val64, 0); + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +static struct kunit_case __refdata riscv_module_linking_test_cases[] =3D { + KUNIT_CASE(run_test_set), + KUNIT_CASE(run_test_sub), + {} +}; + +static struct kunit_suite riscv_module_linking_test_suite =3D { + .name =3D "riscv_checksum", + .test_cases =3D riscv_module_linking_test_cases, +}; + +kunit_test_suites(&riscv_module_linking_test_suite); diff --git a/arch/riscv/kernel/tests/module_test/test_set16.S b/arch/riscv/= kernel/tests/module_test/test_set16.S new file mode 100644 index 000000000000..2be0e441a12e --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set16.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set16 +test_set16: + lw a0, set16 + la t0, set16 +#ifdef CONFIG_32BIT + slli t0, t0, 16 + srli t0, t0, 16 +#else + slli t0, t0, 48 + srli t0, t0, 48 +#endif + sub a0, a0, t0 + ret +.data +set16: + .reloc set16, R_RISCV_SET16, set16 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set32.S b/arch/riscv/= kernel/tests/module_test/test_set32.S new file mode 100644 index 000000000000..de0444537e67 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set32.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set32 +test_set32: + lw a0, set32 + la t0, set32 +#ifndef CONFIG_32BIT + slli t0, t0, 32 + srli t0, t0, 32 +#endif + sub a0, a0, t0 + ret +.data +set32: + .reloc set32, R_RISCV_SET32, set32 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set6.S b/arch/riscv/k= ernel/tests/module_test/test_set6.S new file mode 100644 index 000000000000..c39ce4c219eb --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set6.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set6 +test_set6: + lw a0, set6 + la t0, set6 +#ifdef CONFIG_32BIT + slli t0, t0, 26 + srli t0, t0, 26 +#else + slli t0, t0, 58 + srli t0, t0, 58 +#endif + sub a0, a0, t0 + ret +.data +set6: + .reloc set6, R_RISCV_SET6, set6 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set8.S b/arch/riscv/k= ernel/tests/module_test/test_set8.S new file mode 100644 index 000000000000..a656173f6f99 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set8.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set8 +test_set8: + lw a0, set8 + la t0, set8 +#ifdef CONFIG_32BIT + slli t0, t0, 24 + srli t0, t0, 24 +#else + slli t0, t0, 56 + srli t0, t0, 56 +#endif + sub a0, a0, t0 + ret +.data +set8: + .reloc set8, R_RISCV_SET8, set8 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub16.S b/arch/riscv/= kernel/tests/module_test/test_sub16.S new file mode 100644 index 000000000000..c561e155d1db --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub16.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub16 +test_sub16: + lh a0, sub16 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub16: + .reloc sub16, R_RISCV_ADD16, second + .reloc sub16, R_RISCV_SUB16, first + .half 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub32.S b/arch/riscv/= kernel/tests/module_test/test_sub32.S new file mode 100644 index 000000000000..93232c70cae6 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub32.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub32 +test_sub32: + lw a0, sub32 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub32: + .reloc sub32, R_RISCV_ADD32, second + .reloc sub32, R_RISCV_SUB32, first + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub6.S b/arch/riscv/k= ernel/tests/module_test/test_sub6.S new file mode 100644 index 000000000000..d9c9526ceb62 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub6.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub6 +test_sub6: + lb a0, sub6 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub6: + .reloc sub6, R_RISCV_SET6, second + .reloc sub6, R_RISCV_SUB6, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub64.S b/arch/riscv/= kernel/tests/module_test/test_sub64.S new file mode 100644 index 000000000000..6d260e2a5d98 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub64.S @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub64 +test_sub64: +#ifdef CONFIG_32BIT + lw a0, sub64 +#else + ld a0, sub64 +#endif + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub64: + .reloc sub64, R_RISCV_ADD64, second + .reloc sub64, R_RISCV_SUB64, first + .word 0 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub8.S b/arch/riscv/k= ernel/tests/module_test/test_sub8.S new file mode 100644 index 000000000000..af7849115d4d --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub8.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub8 +test_sub8: + lb a0, sub8 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub8: + .reloc sub8, R_RISCV_ADD8, second + .reloc sub8, R_RISCV_SUB8, first + .byte 0 --=20 2.34.1