From nobody Mon Feb 9 09:38:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BBABCA0EC3 for ; Tue, 12 Sep 2023 13:13:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235431AbjILNNX (ORCPT ); Tue, 12 Sep 2023 09:13:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235295AbjILNNU (ORCPT ); Tue, 12 Sep 2023 09:13:20 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F02B10CA for ; Tue, 12 Sep 2023 06:13:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694524396; x=1726060396; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nJXlvOEO+czS205YyxCyTKdJGR4h9EWvKCOOlBcmerk=; b=J263f2A+SPUE4dY8t5lEVpj88lErK8RzfC9dLb2kuxYtsY304NJOytoM 0tVohKPxeWaL3jCdgxCfjtqOemaL9gGAzzsYREyb/IjVCvJtyg73YHMBU k/m+AwInKXbZs4GMl9zYkbzQtjxcA0nMHd9tsmAgj4dqzu+uU8AQrXWM7 HzjK1opEfizpbNCNDqcutQ94GulIUk16w4Cm6MvNEXsxCrxmHjYe1G4xL l6Z+jwv4hNyTIxGTHe3yjrCyv4g2DZirNnIQCECFluI0NggETZOD2pv43 6YW45XC0frs6NRPMRnT8ioQ/KK6GoEnqG1HB8H8Yxuk/u4ixnZc9e5Ro0 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10831"; a="464740085" X-IronPort-AV: E=Sophos;i="6.02,139,1688454000"; d="scan'208";a="464740085" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2023 06:13:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10831"; a="737116342" X-IronPort-AV: E=Sophos;i="6.02,139,1688454000"; d="scan'208";a="737116342" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2023 06:13:13 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Lucas De Marchi , Daniele Ceraolo Spurio , Rodrigo Vivi Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] drm/xe/gsc: add HECI2 register offsets Date: Tue, 12 Sep 2023 16:08:32 +0300 Message-Id: <20230912130835.2488728-2-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230912130835.2488728-1-alexander.usyskin@intel.com> References: <20230912130835.2488728-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Vitaly Lubart Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/regs/xe_regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe= _regs.h index 77aa3dab321a..5d9380f307cc 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -33,6 +33,10 @@ #define XEHPC_BCS6_RING_BASE 0x3ea000 #define XEHPC_BCS7_RING_BASE 0x3ec000 #define XEHPC_BCS8_RING_BASE 0x3ee000 + +#define DG1_GSC_HECI2_BASE 0x00259000 +#define DG2_GSC_HECI2_BASE 0x00374000 + #define GSCCS_RING_BASE 0x11a000 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) --=20 2.34.1