From nobody Fri Sep 20 11:31:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD6A6CA0EC3 for ; Tue, 12 Sep 2023 07:59:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231887AbjILH7W (ORCPT ); Tue, 12 Sep 2023 03:59:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232192AbjILH6s (ORCPT ); Tue, 12 Sep 2023 03:58:48 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 870E32127; Tue, 12 Sep 2023 00:58:14 -0700 (PDT) X-UUID: 1c478d2c514211eea33bb35ae8d461a2-20230912 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qVXAH/IOPlb4ZbYsnEi9BR7Q1+6g1xboU/NAeYRoxmk=; b=lfP8lUxrezwZcRIASUH+o8MfLK2UiDn2DrfALs5gpf0bqpi11KT6XHWG41UwUUJRTX773sJyrO2vCXaK5L73x0iwknMdlyxXRYxWxY4c+pcHIxNiZve0gq1zsiR+vW684hqxgvZ+fvtZBI0MqTMTr28EE1ya+m8U778ww6XOB44=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:8e00f6b9-940c-48f6-bb05-6a06e8cf910a,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:cb29d713-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 1c478d2c514211eea33bb35ae8d461a2-20230912 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2129602178; Tue, 12 Sep 2023 15:58:07 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 12 Sep 2023 15:58:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 12 Sep 2023 15:58:06 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil CC: AngeloGioacchino Del Regno , , , , , , , "Moudy Ho" Subject: [PATCH v5 03/14] media: platform: mtk-mdp3: add support second sets of MMSYS Date: Tue, 12 Sep 2023 15:57:54 +0800 Message-ID: <20230912075805.11432-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230912075805.11432-1-moudy.ho@mediatek.com> References: <20230912075805.11432-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.899000-8.000000 X-TMASE-MatchedRID: SLF7MkaTajMmiXUXx9FN5QPZZctd3P4BK2i9pofGVSsKogmGusPLbw6B lGN0WKrNVYAhfitWUenIwrufi9pnN8ZR5zLxbV5qFYJUGv4DL3yscK/K2Dlvjsnc0Uc0m8WZEUS 33ulD4Ly5T7dW/d57L2mevJVqJe6AHxPMjOKY7A8LbigRnpKlKTpcQTtiHDgWy7OVZWMu5NZ/bD wXTjqInPOyt166k3k81j4ehKdGTHzAKdUOVLwMLg== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.899000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 38FA8BBB71F6830F7D47BCA2FFC102881C19403BF40A429C0E903C70A7621EDA2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8195 has two MMSYS sets, VPPSYS0 and VPPSYS1. These sets coordinate and control the clock, power, and register settings needed for the components of MDP3. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mdp_cfg_data.c | 44 +++++++++---------- .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 1 + .../platform/mediatek/mdp3/mtk-mdp3-core.c | 40 +++++++++++------ .../platform/mediatek/mdp3/mtk-mdp3-core.h | 3 ++ 4 files changed, 53 insertions(+), 35 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/= media/platform/mediatek/mdp3/mdp_cfg_data.c index 502eeae0bfdc..58792902abb5 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -73,75 +73,75 @@ static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = =3D { =20 static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT]= =3D { [MDP_COMP_WPEI] =3D { - {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI}, + {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI, 0}, {0, 0, 0} }, [MDP_COMP_WPEO] =3D { - {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO}, + {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO, 0}, {0, 0, 0} }, [MDP_COMP_WPEI2] =3D { - {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2}, + {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2, 0}, {0, 0, 0} }, [MDP_COMP_WPEO2] =3D { - {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2}, + {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2, 0}, {0, 0, 0} }, [MDP_COMP_ISP_IMGI] =3D { - {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI}, + {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI, 0}, {0, 0, 4} }, [MDP_COMP_ISP_IMGO] =3D { - {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO}, + {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO, 0}, {0, 0, 4} }, [MDP_COMP_ISP_IMG2O] =3D { - {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O}, + {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O, 0}, {0, 0, 0} }, [MDP_COMP_CAMIN] =3D { - {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN}, + {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN, 0}, {2, 2, 1} }, [MDP_COMP_CAMIN2] =3D { - {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2}, + {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2, 0}, {2, 4, 1} }, [MDP_COMP_RDMA0] =3D { - {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0}, + {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0, 0}, {2, 0, 0} }, [MDP_COMP_CCORR0] =3D { - {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0}, + {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0, 0}, {1, 0, 0} }, [MDP_COMP_RSZ0] =3D { - {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0}, + {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0, 0}, {1, 0, 0} }, [MDP_COMP_RSZ1] =3D { - {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1}, + {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1, 0}, {1, 0, 0} }, [MDP_COMP_TDSHP0] =3D { - {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0}, + {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0, 0}, {0, 0, 0} }, [MDP_COMP_PATH0_SOUT] =3D { - {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT}, + {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT, 0}, {0, 0, 0} }, [MDP_COMP_PATH1_SOUT] =3D { - {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT}, + {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT, 0}, {0, 0, 0} }, [MDP_COMP_WROT0] =3D { - {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0}, + {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0, 0}, {1, 0, 0} }, [MDP_COMP_WDMA] =3D { - {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA}, + {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA, 0}, {1, 0, 0} }, }; @@ -402,10 +402,10 @@ static const struct mdp_limit mt8183_mdp_def_limit = =3D { }; =20 static const struct mdp_pipe_info mt8183_pipe_info[] =3D { - [MDP_PIPE_WPEI] =3D {MDP_PIPE_WPEI, 0}, - [MDP_PIPE_WPEI2] =3D {MDP_PIPE_WPEI2, 1}, - [MDP_PIPE_IMGI] =3D {MDP_PIPE_IMGI, 2}, - [MDP_PIPE_RDMA0] =3D {MDP_PIPE_RDMA0, 3} + [MDP_PIPE_WPEI] =3D {MDP_PIPE_WPEI, 0, 0}, + [MDP_PIPE_WPEI2] =3D {MDP_PIPE_WPEI2, 0, 1}, + [MDP_PIPE_IMGI] =3D {MDP_PIPE_IMGI, 0, 2}, + [MDP_PIPE_RDMA0] =3D {MDP_PIPE_RDMA0, 0, 3} }; =20 const struct mtk_mdp_driver_data mt8183_mdp_driver_data =3D { diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-comp.h index 20d2bcb77ef9..ddc6b654864a 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -138,6 +138,7 @@ struct mdp_comp_match { enum mdp_comp_type type; u32 alias_id; s32 inner_id; + u32 mmsys_id; }; =20 /* Used to describe the item order in MDP property */ diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-core.c index cc44be10fdb7..9c33d3aaf9cd 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -26,39 +26,45 @@ static const struct of_device_id mdp_of_ids[] =3D { MODULE_DEVICE_TABLE(of, mdp_of_ids); =20 static struct platform_device *__get_pdev_by_id(struct platform_device *pd= ev, + struct platform_device *from, enum mdp_infra_id id) { - struct device_node *node; + struct device_node *node, *f =3D NULL; struct platform_device *mdp_pdev =3D NULL; const struct mtk_mdp_driver_data *mdp_data; const char *compat; =20 if (!pdev) - return NULL; + return ERR_PTR(-ENODEV); =20 if (id < MDP_INFRA_MMSYS || id >=3D MDP_INFRA_MAX) { dev_err(&pdev->dev, "Illegal infra id %d\n", id); - return NULL; + return ERR_PTR(-ENODEV); } =20 mdp_data =3D of_device_get_match_data(&pdev->dev); if (!mdp_data) { dev_err(&pdev->dev, "have no driver data to find node\n"); - return NULL; + return ERR_PTR(-ENODEV); } + compat =3D mdp_data->mdp_probe_infra[id].compatible; + if (strlen(compat) =3D=3D 0) + return NULL; =20 - node =3D of_find_compatible_node(NULL, NULL, compat); + if (from) + f =3D from->dev.of_node; + node =3D of_find_compatible_node(f, NULL, compat); if (WARN_ON(!node)) { dev_err(&pdev->dev, "find node from id %d failed\n", id); - return NULL; + return ERR_PTR(-ENODEV); } =20 mdp_pdev =3D of_find_device_by_node(node); of_node_put(node); if (WARN_ON(!mdp_pdev)) { dev_err(&pdev->dev, "find pdev from id %d failed\n", id); - return NULL; + return ERR_PTR(-ENODEV); } =20 return mdp_pdev; @@ -152,7 +158,7 @@ static int mdp_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct mdp_dev *mdp; - struct platform_device *mm_pdev; + struct platform_device *mm_pdev, *mm2_pdev; int ret, i, mutex_id; =20 mdp =3D kzalloc(sizeof(*mdp), GFP_KERNEL); @@ -164,15 +170,23 @@ static int mdp_probe(struct platform_device *pdev) mdp->pdev =3D pdev; mdp->mdp_data =3D of_device_get_match_data(&pdev->dev); =20 - mm_pdev =3D __get_pdev_by_id(pdev, MDP_INFRA_MMSYS); - if (!mm_pdev) { + mm_pdev =3D __get_pdev_by_id(pdev, NULL, MDP_INFRA_MMSYS); + if (IS_ERR_OR_NULL(mm_pdev)) { ret =3D -ENODEV; goto err_destroy_device; } mdp->mdp_mmsys =3D &mm_pdev->dev; =20 - mm_pdev =3D __get_pdev_by_id(pdev, MDP_INFRA_MUTEX); - if (WARN_ON(!mm_pdev)) { + /* MMSYS2 is not available on all chips, so the config may be null. */ + mm2_pdev =3D __get_pdev_by_id(pdev, mm_pdev, MDP_INFRA_MMSYS2); + if (IS_ERR(mm2_pdev)) { + ret =3D PTR_ERR(mm2_pdev); + goto err_destroy_device; + } + mdp->mdp_mmsys2 =3D &mm2_pdev->dev; + + mm_pdev =3D __get_pdev_by_id(pdev, NULL, MDP_INFRA_MUTEX); + if (IS_ERR_OR_NULL(mm_pdev)) { ret =3D -ENODEV; goto err_destroy_device; } @@ -208,7 +222,7 @@ static int mdp_probe(struct platform_device *pdev) goto err_destroy_job_wq; } =20 - mm_pdev =3D __get_pdev_by_id(pdev, MDP_INFRA_SCP); + mm_pdev =3D __get_pdev_by_id(pdev, NULL, MDP_INFRA_SCP); if (WARN_ON(!mm_pdev)) { dev_err(&pdev->dev, "Could not get scp device\n"); ret =3D -ENODEV; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-core.h index 7e21d226ceb8..0434b70e1fc9 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -20,6 +20,7 @@ =20 enum mdp_infra_id { MDP_INFRA_MMSYS, + MDP_INFRA_MMSYS2, MDP_INFRA_MUTEX, MDP_INFRA_SCP, MDP_INFRA_MAX @@ -68,6 +69,7 @@ struct mtk_mdp_driver_data { struct mdp_dev { struct platform_device *pdev; struct device *mdp_mmsys; + struct device *mdp_mmsys2; struct mtk_mutex *mdp_mutex[MDP_PIPE_MAX]; struct mdp_comp *comp[MDP_MAX_COMP_COUNT]; const struct mtk_mdp_driver_data *mdp_data; @@ -96,6 +98,7 @@ struct mdp_dev { =20 struct mdp_pipe_info { enum mdp_pipe_id pipe_id; + u32 mmsys_id; u32 mutex_id; }; =20 --=20 2.18.0