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Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V3 06/30] x86/microcode/intel: Cleanup code further References: <20230912065249.695681286@linutronix.de> MIME-Version: 1.0 Date: Tue, 12 Sep 2023 09:57:52 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Sanitize the microcode scan loop, fixup printks and move the initrd loading function next to the place where it is used and mark it __init. Signed-off-by: Thomas Gleixner --- V2: Fix changelog - Nikolay --- arch/x86/kernel/cpu/microcode/intel.c | 76 ++++++++++++++---------------= ----- 1 file changed, 32 insertions(+), 44 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -36,7 +36,7 @@ static const char ucode_path[] =3D "kernel static struct microcode_intel *intel_ucode_patch __read_mostly; =20 /* last level cache size per core */ -static int llc_size_per_core __ro_after_init; +static unsigned int llc_size_per_core __ro_after_init; =20 /* microcode format is extended from prescott processors */ struct extended_signature { @@ -296,29 +296,6 @@ static struct microcode_intel *scan_micr return patch; } =20 -static bool load_builtin_intel_microcode(struct cpio_data *cp) -{ - unsigned int eax =3D 1, ebx, ecx =3D 0, edx; - struct firmware fw; - char name[30]; - - if (IS_ENABLED(CONFIG_X86_32)) - return false; - - native_cpuid(&eax, &ebx, &ecx, &edx); - - sprintf(name, "intel-ucode/%02x-%02x-%02x", - x86_family(eax), x86_model(eax), x86_stepping(eax)); - - if (firmware_request_builtin(&fw, name)) { - cp->size =3D fw.size; - cp->data =3D (void *)fw.data; - return true; - } - - return false; -} - static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; @@ -362,6 +339,28 @@ static int apply_microcode_early(struct return 0; } =20 +static bool load_builtin_intel_microcode(struct cpio_data *cp) +{ + unsigned int eax =3D 1, ebx, ecx =3D 0, edx; + struct firmware fw; + char name[30]; + + if (IS_ENABLED(CONFIG_X86_32)) + return false; + + native_cpuid(&eax, &ebx, &ecx, &edx); + + sprintf(name, "intel-ucode/%02x-%02x-%02x", + x86_family(eax), x86_model(eax), x86_stepping(eax)); + + if (firmware_request_builtin(&fw, name)) { + cp->size =3D fw.size; + cp->data =3D (void *)fw.data; + return true; + } + return false; +} + int __init save_microcode_in_initrd_intel(void) { struct ucode_cpu_info uci; @@ -434,25 +433,16 @@ void load_ucode_intel_ap(void) apply_microcode_early(&uci, true); } =20 -/* Accessor for microcode pointer */ -static struct microcode_intel *ucode_get_patch(void) -{ - return intel_ucode_patch; -} - void reload_ucode_intel(void) { - struct microcode_intel *p; struct ucode_cpu_info uci; =20 intel_cpu_collect_info(&uci); =20 - p =3D ucode_get_patch(); - if (!p) + uci.mc =3D intel_ucode_patch; + if (!uci.mc) return; =20 - uci.mc =3D p; - apply_microcode_early(&uci, false); } =20 @@ -490,8 +480,7 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() !=3D cpu)) return UCODE_ERROR; =20 - /* Look for a newer patch in our cache: */ - mc =3D ucode_get_patch(); + mc =3D intel_ucode_patch; if (!mc) { mc =3D uci->mc; if (!mc) @@ -682,18 +671,17 @@ static enum ucode_state request_microcod } =20 static struct microcode_ops microcode_intel_ops =3D { - .request_microcode_fw =3D request_microcode_fw, - .collect_cpu_info =3D collect_cpu_info, - .apply_microcode =3D apply_microcode_intel, + .request_microcode_fw =3D request_microcode_fw, + .collect_cpu_info =3D collect_cpu_info, + .apply_microcode =3D apply_microcode_intel, }; =20 -static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c) +static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) { u64 llc_size =3D c->x86_cache_size * 1024ULL; =20 do_div(llc_size, c->x86_max_cores); - - return (int)llc_size; + llc_size_per_core =3D (unsigned int)llc_size; } =20 struct microcode_ops * __init init_intel_microcode(void) @@ -706,7 +694,7 @@ struct microcode_ops * __init init_intel return NULL; } =20 - llc_size_per_core =3D calc_llc_size_per_core(c); + calc_llc_size_per_core(c); =20 return µcode_intel_ops; }