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([82.78.167.145]) by smtp.gmail.com with ESMTPSA id f21-20020a05640214d500b0051e22660835sm5422415edx.46.2023.09.11.21.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 21:53:09 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, ulf.hansson@linaro.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com, arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Subject: [PATCH 26/37] pinctrl: renesas: rzg2l: move ds and oi to SoC specific configuration Date: Tue, 12 Sep 2023 07:51:46 +0300 Message-Id: <20230912045157.177966-27-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> References: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Move drive strength and output impedance values to SoC specific configuration data structure (struct rzg2l_hwcfg). This allows extending the drive strength support for RZ/G3S. Along with this the DS values were converted to uA for simple integration with RZ/G3S support. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 38 ++++++++++++++++++------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 80cacac7ec95..1277bb26069c 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -133,13 +133,27 @@ struct rzg2l_register_offsets { u16 sd_ch; }; =20 +/** + * enum rzg2l_iolh_index - starting indexes in IOLH specific arrays + * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source + * @RZG2L_IOLH_IDX_MAX: maximum index + */ +enum rzg2l_iolh_index { + RZG2L_IOLH_IDX_3V3 =3D 0, + RZG2L_IOLH_IDX_MAX =3D 4, +}; + /** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets + * @iolh_groupa_ua: IOLH group A micro amps specific values + * @iolh_groupb_oi: IOLH group B output impedance specific values * @func_base: base number for port function (see register PFC) */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; + u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; + u16 iolh_groupb_oi[RZG2L_IOLH_IDX_MAX]; u8 func_base; }; =20 @@ -177,9 +191,6 @@ struct rzg2l_pinctrl { struct mutex mutex; /* serialize adding groups and functions */ }; =20 -static const unsigned int iolh_groupa_mA[] =3D { 2, 4, 8, 12 }; -static const unsigned int iolh_groupb_oi[] =3D { 100, 66, 50, 33 }; - static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -609,7 +620,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev= *pctldev, return -EINVAL; =20 index =3D rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); - arg =3D iolh_groupa_mA[index]; + arg =3D hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; break; } =20 @@ -620,7 +631,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev= *pctldev, return -EINVAL; =20 index =3D rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); - arg =3D iolh_groupb_oi[index]; + arg =3D hwcfg->iolh_groupb_oi[index]; break; } =20 @@ -708,11 +719,11 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_d= ev *pctldev, if (!(cfg & PIN_CFG_IOLH_A)) return -EINVAL; =20 - for (index =3D 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) { - if (arg =3D=3D iolh_groupa_mA[index]) + for (index =3D RZG2L_IOLH_IDX_3V3; index < RZG2L_IOLH_IDX_3V3 + 4; inde= x++) { + if (arg =3D=3D (hwcfg->iolh_groupa_ua[index] / 1000)) break; } - if (index >=3D ARRAY_SIZE(iolh_groupa_mA)) + if (index =3D=3D (RZG2L_IOLH_IDX_3V3 + 4)) return -EINVAL; =20 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); @@ -726,11 +737,11 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_d= ev *pctldev, if (!(cfg & PIN_CFG_IOLH_B)) return -EINVAL; =20 - for (index =3D 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) { - if (arg =3D=3D iolh_groupb_oi[index]) + for (index =3D 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { + if (arg =3D=3D hwcfg->iolh_groupb_oi[index]) break; } - if (index >=3D ARRAY_SIZE(iolh_groupb_oi)) + if (index =3D=3D ARRAY_SIZE(hwcfg->iolh_groupb_oi)) return -EINVAL; =20 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); @@ -1562,6 +1573,11 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg =3D { .pwpr =3D 0x3014, .sd_ch =3D 0x3000, }, + .iolh_groupa_ua =3D { + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] =3D 2000, 4000, 8000, 12000, + }, + .iolh_groupb_oi =3D { 100, 66, 50, 33, }, }; =20 static struct rzg2l_pinctrl_data r9a07g043_data =3D { --=20 2.39.2