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([82.78.167.145]) by smtp.gmail.com with ESMTPSA id f21-20020a05640214d500b0051e22660835sm5422415edx.46.2023.09.11.21.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 21:52:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, ulf.hansson@linaro.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com, arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Subject: [PATCH 15/37] clk: renesas: rzg2l: add support for RZ/G3S PLL Date: Tue, 12 Sep 2023 07:51:35 +0300 Message-Id: <20230912045157.177966-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> References: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for reading the frequency of PLL1/4/6 available on RZ/G3S. The computation formula for PLL frequency is as follows: Fout =3D (nir + nfr / 4096) * Fin / (mr * pr) Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/rzg2l-cpg.c | 44 ++++++++++++++++++++++++++++++--- drivers/clk/renesas/rzg2l-cpg.h | 3 +++ 2 files changed, 43 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 50f69bbe1a6e..638501e493e2 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -718,11 +718,43 @@ static const struct clk_ops rzg2l_cpg_pll_ops =3D { .recalc_rate =3D rzg2l_cpg_pll_clk_recalc_rate, }; =20 +static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzg2l_cpg_priv *priv =3D pll_clk->priv; + u32 nir, nfr, mr, pr, val; + u64 rate; + + if (pll_clk->type !=3D CLK_TYPE_G3S_SAM_PLL) + return parent_rate; + + val =3D readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); + + pr =3D 1 << FIELD_GET(GENMASK(28, 26), val); + /* Hardware interprets values higher than 8 as p =3D 16. */ + if (pr > 8) + pr =3D 16; + + mr =3D FIELD_GET(GENMASK(25, 22), val) + 1; + nir =3D FIELD_GET(GENMASK(21, 13), val) + 1; + nfr =3D FIELD_GET(GENMASK(12, 1), val); + + rate =3D DIV_ROUND_CLOSEST_ULL((u64)parent_rate * nfr, 4096); + rate +=3D (u64)parent_rate * nir; + return DIV_ROUND_CLOSEST_ULL(rate, (mr + pr)); +} + +static const struct clk_ops rzg3s_cpg_pll_ops =3D { + .recalc_rate =3D rzg3s_cpg_pll_clk_recalc_rate, +}; + static struct clk * __init rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, struct clk **clks, void __iomem *base, - struct rzg2l_cpg_priv *priv) + struct rzg2l_cpg_priv *priv, + const struct clk_ops *ops) { struct device *dev =3D priv->dev; const struct clk *parent; @@ -740,7 +772,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *c= ore, =20 parent_name =3D __clk_get_name(parent); init.name =3D core->name; - init.ops =3D &rzg2l_cpg_pll_ops; + init.ops =3D ops; init.flags =3D 0; init.parent_names =3D &parent_name; init.num_parents =3D 1; @@ -835,8 +867,12 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk = *core, core->mult, div); break; case CLK_TYPE_SAM_PLL: - clk =3D rzg2l_cpg_pll_clk_register(core, priv->clks, - priv->base, priv); + clk =3D rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv, + &rzg2l_cpg_pll_ops); + break; + case CLK_TYPE_G3S_SAM_PLL: + clk =3D rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv, + &rzg3s_cpg_pll_ops); break; case CLK_TYPE_SIPLL5: clk =3D rzg2l_cpg_sipll5_register(core, priv->clks, priv); diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 0b28870a6f9d..16f7a1872814 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -102,6 +102,7 @@ enum clk_types { CLK_TYPE_IN, /* External Clock Input */ CLK_TYPE_FF, /* Fixed Factor Clock */ CLK_TYPE_SAM_PLL, + CLK_TYPE_G3S_SAM_PLL, =20 /* Clock with divider */ CLK_TYPE_DIV, @@ -129,6 +130,8 @@ enum clk_types { DEF_TYPE(_name, _id, _type, .parent =3D _parent) #define DEF_SAMPLL(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent =3D _parent, .conf =3D _co= nf) +#define DEF_G3S_SAMPLL(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3S_SAM_PLL, .parent =3D _parent, .conf =3D= _conf) #define DEF_INPUT(_name, _id) \ DEF_TYPE(_name, _id, CLK_TYPE_IN) #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ --=20 2.39.2