From nobody Wed Feb 11 18:12:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4F5BCA0EC6 for ; Mon, 11 Sep 2023 22:24:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240332AbjIKWWP (ORCPT ); Mon, 11 Sep 2023 18:22:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243677AbjIKR3T (ORCPT ); Mon, 11 Sep 2023 13:29:19 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53B24189; Mon, 11 Sep 2023 10:29:13 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 38BHT3PV082643; Mon, 11 Sep 2023 12:29:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1694453343; bh=PVQPaRp5IlzLcS2dTVXIMLqYtvoC7+GRQ7NX6AOEpAw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Yee2TpbU3ox5yEBjLBgZPoDZS2NNJWrvxLZOAN25pHxycm6ndEJBnlvdEPDctXP8j zuGoYp/twkC1DKvuNaYvPJkVHoOnzDh8piBPMdTdDgLsNnGSjTABq8nlhlEhtkbyEm IyiMrCBQkMMW/T5KQojwa4YNA45/T33vJyVeyJaQ= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 38BHT3Tp065690 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Sep 2023 12:29:03 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 11 Sep 2023 12:29:03 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 11 Sep 2023 12:29:03 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 38BHT3aN109063; Mon, 11 Sep 2023 12:29:03 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Vignesh CC: , , , Tero Kristo , Nishanth Menon , Tom Rini , Bryan , Praneeth , Roger Quadros Subject: [PATCH 1/3] arm64: dts: ti: k3-am64: Add phase tags marking Date: Mon, 11 Sep 2023 12:29:00 -0500 Message-ID: <20230911172902.1057417-2-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230911172902.1057417-1-nm@ti.com> References: <20230911172902.1057417-1-nm@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. On TI K3 AM642 SoC, only esm nodes are exclusively used by R5 bootloader, rest of the dts nodes with bootph-* are used by later boot stages also. Add bootph-all for all other nodes that are used in the bootloader on K3 AM642 SoC, and bootph-pre-ram is not needed specifically for any other node in kernel dts. Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 11 +++++++++++ arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am64.dtsi | 2 ++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index 0df54a741824..1933c9dd1d9f 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -38,6 +38,7 @@ sproxy-sram@1fc000 { }; =20 main_conf: syscon@43000000 { + bootph-all; compatible =3D "ti,j721e-system-controller", "syscon", "simple-mfd"; reg =3D <0x0 0x43000000 0x0 0x20000>; #address-cells =3D <1>; @@ -45,6 +46,7 @@ main_conf: syscon@43000000 { ranges =3D <0x0 0x0 0x43000000 0x20000>; =20 chipid@14 { + bootph-all; compatible =3D "ti,am654-chipid"; reg =3D <0x00000014 0x4>; }; @@ -96,6 +98,7 @@ gic_its: msi-controller@1820000 { }; =20 dmss: bus@48000000 { + bootph-all; compatible =3D "simple-mfd"; #address-cells =3D <2>; #size-cells =3D <2>; @@ -105,6 +108,7 @@ dmss: bus@48000000 { ti,sci-dev-id =3D <25>; =20 secure_proxy_main: mailbox@4d000000 { + bootph-all; compatible =3D "ti,am654-secure-proxy"; #mbox-cells =3D <1>; reg-names =3D "target_data", "rt", "scfg"; @@ -188,6 +192,7 @@ main_pktdma: dma-controller@485c0000 { }; =20 dmsc: system-controller@44043000 { + bootph-all; compatible =3D "ti,k2g-sci"; ti,host-id =3D <12>; mbox-names =3D "rx", "tx"; @@ -197,22 +202,26 @@ dmsc: system-controller@44043000 { reg =3D <0x00 0x44043000 0x00 0xfe0>; =20 k3_pds: power-controller { + bootph-all; compatible =3D "ti,sci-pm-domain"; #power-domain-cells =3D <2>; }; =20 k3_clks: clock-controller { + bootph-all; compatible =3D "ti,k2g-sci-clk"; #clock-cells =3D <2>; }; =20 k3_reset: reset-controller { + bootph-all; compatible =3D "ti,sci-reset"; #reset-cells =3D <2>; }; }; =20 main_pmx0: pinctrl@f4000 { + bootph-all; compatible =3D "pinctrl-single"; reg =3D <0x00 0xf4000 0x00 0x2d0>; #pinctrl-cells =3D <1>; @@ -221,6 +230,7 @@ main_pmx0: pinctrl@f4000 { }; =20 main_timer0: timer@2400000 { + bootph-all; compatible =3D "ti,am654-timer"; reg =3D <0x00 0x2400000 0x00 0x400>; interrupts =3D ; @@ -365,6 +375,7 @@ main_timer11: timer@24b0000 { }; =20 main_esm: esm@420000 { + bootph-pre-ram; compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x420000 0x00 0x1000>; ti,esm-pins =3D <160>, <161>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am64-mcu.dtsi index 686d49790721..b9508072bebb 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -146,6 +146,7 @@ mcu_gpio0: gpio@4201000 { }; =20 mcu_pmx0: pinctrl@4084000 { + bootph-all; compatible =3D "pinctrl-single"; reg =3D <0x00 0x4084000 0x00 0x84>; #pinctrl-cells =3D <1>; @@ -154,6 +155,7 @@ mcu_pmx0: pinctrl@4084000 { }; =20 mcu_esm: esm@4100000 { + bootph-pre-ram; compatible =3D "ti,j721e-esm"; reg =3D <0x00 0x4100000 0x00 0x1000>; ti,esm-pins =3D <0>, <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k= 3-am64.dtsi index 8e9c2bc70f4d..0187c42aed4f 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -47,6 +47,7 @@ pmu: pmu { }; =20 cbass_main: bus@f4000 { + bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; @@ -85,6 +86,7 @@ cbass_main: bus@f4000 { <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; =20 cbass_mcu: bus@4000000 { + bootph-all; compatible =3D "simple-bus"; #address-cells =3D <2>; #size-cells =3D <2>; --=20 2.40.0 From nobody Wed Feb 11 18:12:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4263FCA0ECE for ; Mon, 11 Sep 2023 22:22:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359491AbjIKWRG (ORCPT ); Mon, 11 Sep 2023 18:17:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243678AbjIKR3U (ORCPT ); Mon, 11 Sep 2023 13:29:20 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1A031B9; 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Mon, 11 Sep 2023 12:29:03 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 38BHT3hI003693; Mon, 11 Sep 2023 12:29:03 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Vignesh CC: , , , Tero Kristo , Nishanth Menon , Tom Rini , Bryan , Praneeth , Roger Quadros Subject: [PATCH 2/3] arm64: dts: ti: k3-am642-evm: Add boot phase tags marking Date: Mon, 11 Sep 2023 12:29:01 -0500 Message-ID: <20230911172902.1057417-3-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230911172902.1057417-1-nm@ti.com> References: <20230911172902.1057417-1-nm@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Describe the same for AM642-evm boot devices. Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index b4a1f73d4fb1..d0e1191baecd 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -35,6 +35,7 @@ aliases { }; =20 memory@80000000 { + bootph-all; device_type =3D "memory"; /* 2G RAM */ reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>; @@ -108,6 +109,7 @@ rtos_ipc_memory_region: ipc-memories@a5000000 { =20 evm_12v0: regulator-0 { /* main DC jack */ + bootph-all; compatible =3D "regulator-fixed"; regulator-name =3D "evm_12v0"; regulator-min-microvolt =3D <12000000>; @@ -129,6 +131,7 @@ vsys_5v0: regulator-1 { =20 vsys_3v3: regulator-2 { /* output of LM5140 */ + bootph-all; compatible =3D "regulator-fixed"; regulator-name =3D "vsys_3v3"; regulator-min-microvolt =3D <3300000>; @@ -140,6 +143,7 @@ vsys_3v3: regulator-2 { =20 vdd_mmc1: regulator-3 { /* TPS2051BD */ + bootph-all; compatible =3D "regulator-fixed"; regulator-name =3D "vdd_mmc1"; regulator-min-microvolt =3D <3300000>; @@ -161,6 +165,7 @@ vddb: regulator-4 { }; =20 vtt_supply: regulator-5 { + bootph-all; compatible =3D "regulator-fixed"; regulator-name =3D "vtt"; pinctrl-names =3D "default"; @@ -251,6 +256,7 @@ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD = */ }; =20 main_uart0_pins_default: main-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ @@ -269,6 +275,7 @@ AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ }; =20 main_i2c0_pins_default: main-i2c0-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ @@ -276,6 +283,7 @@ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_= SDA */ }; =20 main_i2c1_pins_default: main-i2c1-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ @@ -283,6 +291,7 @@ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_= SDA */ }; =20 mdio1_pins_default: mdio1-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ @@ -290,6 +299,7 @@ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO= 18.MDIO0_MDIO */ }; =20 rgmii1_pins_default: rgmii1-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ @@ -307,6 +317,7 @@ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_G= PO9.RGMII1_TX_CTL */ }; =20 rgmii2_pins_default: rgmii2-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ @@ -324,6 +335,7 @@ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_G= PO15.RGMII2_TX_CTL */ }; =20 main_usb0_pins_default: main-usb0-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; @@ -366,6 +378,7 @@ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ }; =20 ddr_vtt_pins_default: ddr-vtt-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 = */ >; @@ -373,6 +386,7 @@ AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI= 0_CSN1.GPIO0_12 */ }; =20 &main_uart0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; @@ -387,6 +401,7 @@ &main_uart1 { }; =20 &main_i2c0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_pins_default>; @@ -400,12 +415,14 @@ eeprom@50 { }; =20 &main_i2c1 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c1_pins_default>; clock-frequency =3D <400000>; =20 exp1: gpio@22 { + bootph-all; compatible =3D "ti,tca6424"; reg =3D <0x22>; gpio-controller; @@ -438,6 +455,10 @@ display@3c { }; }; =20 +&main_gpio0 { + bootph-all; +}; + /* mcu_gpio0 is reserved for mcu firmware usage */ &mcu_gpio0 { status =3D "reserved"; @@ -467,6 +488,7 @@ &sdhci0 { =20 &sdhci1 { /* SD/MMC */ + bootph-all; vmmc-supply =3D <&vdd_mmc1>; pinctrl-names =3D "default"; bus-width =3D <4>; @@ -476,11 +498,13 @@ &sdhci1 { }; =20 &usbss0 { + bootph-all; ti,vbus-divider; ti,usb2-only; }; =20 &usb0 { + bootph-all; dr_mode =3D "otg"; maximum-speed =3D "high-speed"; pinctrl-names =3D "default"; @@ -488,11 +512,13 @@ &usb0 { }; =20 &cpsw3g { + bootph-all; pinctrl-names =3D "default"; pinctrl-0 =3D <&rgmii1_pins_default>, <&rgmii2_pins_default>; }; =20 &cpsw_port1 { + bootph-all; phy-mode =3D "rgmii-rxid"; phy-handle =3D <&cpsw3g_phy0>; }; @@ -503,11 +529,13 @@ &cpsw_port2 { }; =20 &cpsw3g_mdio { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mdio1_pins_default>; =20 cpsw3g_phy0: ethernet-phy@0 { + bootph-all; reg =3D <0>; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; --=20 2.40.0 From nobody Wed Feb 11 18:12:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58396EEB581 for ; Mon, 11 Sep 2023 20:47:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232151AbjIKUr0 (ORCPT ); Mon, 11 Sep 2023 16:47:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243674AbjIKR3T (ORCPT ); Mon, 11 Sep 2023 13:29:19 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9688A1B8; Mon, 11 Sep 2023 10:29:13 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 38BHT3S2082647; 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Mon, 11 Sep 2023 12:29:03 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 38BHT3uf007969; Mon, 11 Sep 2023 12:29:03 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Vignesh CC: , , , Tero Kristo , Nishanth Menon , Tom Rini , Bryan , Praneeth , Roger Quadros Subject: [PATCH 3/3] arm64: dts: ti: k3-am642-sk: Add boot phase tags marking Date: Mon, 11 Sep 2023 12:29:02 -0500 Message-ID: <20230911172902.1057417-4-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230911172902.1057417-1-nm@ti.com> References: <20230911172902.1057417-1-nm@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Describe the same for AM642-sk boot devices. Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 29 ++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 722fd285a34e..f29c8a9b59ba 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -34,6 +34,7 @@ aliases { }; =20 memory@80000000 { + bootph-pre-ram; device_type =3D "memory"; /* 2G RAM */ reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>; @@ -107,6 +108,7 @@ rtos_ipc_memory_region: ipc-memories@a5000000 { =20 vusb_main: regulator-0 { /* USB MAIN INPUT 5V DC */ + bootph-all; compatible =3D "regulator-fixed"; regulator-name =3D "vusb_main5v0"; regulator-min-microvolt =3D <5000000>; @@ -117,6 +119,7 @@ vusb_main: regulator-0 { =20 vcc_3v3_sys: regulator-1 { /* output of LP8733xx */ + bootph-all; compatible =3D "regulator-fixed"; regulator-name =3D "vcc_3v3_sys"; regulator-min-microvolt =3D <3300000>; @@ -128,6 +131,7 @@ vcc_3v3_sys: regulator-1 { =20 vdd_mmc1: regulator-2 { /* TPS2051BD */ + bootph-all; compatible =3D "regulator-fixed"; regulator-name =3D "vdd_mmc1"; regulator-min-microvolt =3D <3300000>; @@ -234,6 +238,7 @@ led-7 { =20 &main_pmx0 { main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ @@ -248,6 +253,7 @@ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_= DAT3 */ }; =20 main_uart0_pins_default: main-uart0-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ @@ -257,6 +263,7 @@ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ }; =20 main_uart1_pins_default: main-uart1-default-pins { + bootph-pre-ram; pinctrl-single,pins =3D < AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ @@ -266,12 +273,14 @@ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD= */ }; =20 main_usb0_pins_default: main-usb0-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; =20 main_i2c0_pins_default: main-i2c0-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ @@ -279,6 +288,7 @@ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_= SDA */ }; =20 main_i2c1_pins_default: main-i2c1-default-pins { + bootph-all; pinctrl-single,pins =3D < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ @@ -367,6 +377,7 @@ AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ }; =20 &main_uart0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; @@ -375,12 +386,14 @@ &main_uart0 { =20 &main_uart1 { /* main_uart1 is reserved for firmware usage */ + bootph-pre-ram; status =3D "reserved"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart1_pins_default>; }; =20 &main_i2c0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_pins_default>; @@ -393,12 +406,14 @@ eeprom@51 { }; =20 &main_i2c1 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c1_pins_default>; clock-frequency =3D <400000>; =20 exp1: gpio@70 { + bootph-all; compatible =3D "nxp,pca9538"; reg =3D <0x70>; gpio-controller; @@ -445,6 +460,7 @@ wlcore: wlcore@2 { =20 &sdhci1 { /* SD/MMC */ + bootph-all; vmmc-supply =3D <&vdd_mmc1>; pinctrl-names =3D "default"; bus-width =3D <4>; @@ -454,11 +470,22 @@ &sdhci1 { }; =20 &serdes_ln_ctrl { + bootph-all; idle-states =3D ; }; =20 +&serdes_refclk { + bootph-all; +}; + +&serdes_wiz0 { + bootph-all; +}; + &serdes0 { + bootph-all; serdes0_usb_link: phy@0 { + bootph-all; reg =3D <0>; cdns,num-lanes =3D <1>; #phy-cells =3D <0>; @@ -468,10 +495,12 @@ serdes0_usb_link: phy@0 { }; =20 &usbss0 { + bootph-all; ti,vbus-divider; }; =20 &usb0 { + bootph-all; dr_mode =3D "host"; maximum-speed =3D "super-speed"; pinctrl-names =3D "default"; --=20 2.40.0