From nobody Fri Dec 19 04:03:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2656ECA0EDB for ; Mon, 11 Sep 2023 21:48:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351398AbjIKVnG (ORCPT ); Mon, 11 Sep 2023 17:43:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237869AbjIKNQj (ORCPT ); Mon, 11 Sep 2023 09:16:39 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 337EAEB for ; Mon, 11 Sep 2023 06:16:34 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-401ec23be82so49528575e9.0 for ; Mon, 11 Sep 2023 06:16:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1694438192; x=1695042992; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JvOXQ7FYd4bs7bkUZT+Erh5aGWPCjNF5TJ6uV/v/MCg=; b=qWzvC8iw5Wl2Alcpq0dB7ra1Cb1LdAlqcQ8dLg4BFKMUHQ9PQvpFEpvnM+Hc9BzG25 b07Ld2Ln9QnFb16138Gg9qvHgNaLL5UlXOcVNoOg92TOw24R7pr5cV0bfVlFMGch+z+/ Te8nmn9eNp/ZzdSBEo7wLylFkZSffOex94gteiVpmxKsJx4Be5DjYqZ2O8xGu2RzRisB D2v/dYj762deSLTa4cY0NQit2jGZ8d61mFN3g/EdcvgB0Uf8rTBC5Qcv/096tphY9NFc Z7ndSSG+m05RQg56VcxpjwbbsUdyq2BF6nkAoYCtiSj9PSbO8GU7UOTUcd0dMMKe3LsF C74A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694438192; x=1695042992; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JvOXQ7FYd4bs7bkUZT+Erh5aGWPCjNF5TJ6uV/v/MCg=; b=xDvfS1VZkCTmIMyR9PQtK+S3DWbev5rOEhTFhNRaDVoLHRxgHD2krN0n9yWL8ucFco 2ARhw3ovVN8Xlr2WL02XbCT92sVExdsfnZaEZQu2WpZYQhtRvvE2pZiMyF3Ptek+NWZG 7B6yoMSyTpby/vSysV7DN0aiGbrUC/axeagchlcloO8jCiEJ7zbbPodNvEQZh+/xVfOy TaViVVtwj39CTTrHH5y1725Sikbv/2+JtcmxxXmMNAfw7cghLHeyzZrpGLuIeeWS6PYL 34psKGRkpET0qmmMnWk5A9u2Pw1n/rMRNCocSvHbp3Iuj0bawZNI19GXZfz1H04dkkxL DSkg== X-Gm-Message-State: AOJu0YxBIUPAG0HFtksIMRViTXDF8L6mZBJTLOhSBlCqExmSfQbCoD0+ sFiB9SQtM0mZaOHOkFYjz0ldNQ== X-Google-Smtp-Source: AGHT+IFRHd7EuaFwA1K1cfF+a13jKeLBoTHGF7TEiz4nS9tv95i5qHxXArflq3jWzwYQ4//q7JLqPw== X-Received: by 2002:a05:600c:1c8f:b0:402:f55c:faee with SMTP id k15-20020a05600c1c8f00b00402f55cfaeemr7265932wms.26.1694438192211; Mon, 11 Sep 2023 06:16:32 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id b11-20020a5d4d8b000000b0031416362e23sm10134340wru.3.2023.09.11.06.16.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 06:16:31 -0700 (PDT) From: Alexandre Ghiti To: Will Deacon , "Aneesh Kumar K . V" , Andrew Morton , Nick Piggin , Peter Zijlstra , Mayuresh Chitale , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland , Lad Prabhakar Cc: Alexandre Ghiti , Andrew Jones Subject: [PATCH v4 4/4] riscv: Improve flush_tlb_kernel_range() Date: Mon, 11 Sep 2023 15:12:24 +0200 Message-Id: <20230911131224.61924-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230911131224.61924-1-alexghiti@rivosinc.com> References: <20230911131224.61924-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This function used to simply flush the whole tlb of all harts, be more subtile and try to only flush the range. The problem is that we can only use PAGE_SIZE as stride since we don't know the size of the underlying mapping and then this function will be improved only if the size of the region to flush is < threshold * PAGE_SIZE. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Tested-by: Lad Prabhakar # --- arch/riscv/include/asm/tlbflush.h | 11 ++++++----- arch/riscv/mm/tlbflush.c | 33 ++++++++++++++++++++++--------- 2 files changed, 30 insertions(+), 14 deletions(-) diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlb= flush.h index 170a49c531c6..8f3418c5f172 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -40,6 +40,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned lo= ng start, void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); +void flush_tlb_kernel_range(unsigned long start, unsigned long end); #ifdef CONFIG_TRANSPARENT_HUGEPAGE #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, @@ -56,15 +57,15 @@ static inline void flush_tlb_range(struct vm_area_struc= t *vma, local_flush_tlb_all(); } =20 -#define flush_tlb_mm(mm) flush_tlb_all() -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() -#endif /* !CONFIG_SMP || !CONFIG_MMU */ - /* Flush a range of kernel pages */ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - flush_tlb_all(); + local_flush_tlb_all(); } =20 +#define flush_tlb_mm(mm) flush_tlb_all() +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all() +#endif /* !CONFIG_SMP || !CONFIG_MMU */ + #endif /* _ASM_RISCV_TLBFLUSH_H */ diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 2c1136d73411..28cd8539b575 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -97,19 +97,27 @@ static void __flush_tlb_range(struct mm_struct *mm, uns= igned long start, unsigned long size, unsigned long stride) { struct flush_tlb_range_data ftd; - struct cpumask *cmask =3D mm_cpumask(mm); + struct cpumask *cmask, full_cmask; unsigned long asid =3D FLUSH_TLB_NO_ASID; - unsigned int cpuid; bool broadcast; =20 - if (cpumask_empty(cmask)) - return; + if (mm) { + unsigned int cpuid; + + cmask =3D mm_cpumask(mm); + if (cpumask_empty(cmask)) + return; =20 - cpuid =3D get_cpu(); - /* check if the tlbflush needs to be sent to other CPUs */ - broadcast =3D cpumask_any_but(cmask, cpuid) < nr_cpu_ids; + cpuid =3D get_cpu(); + /* check if the tlbflush needs to be sent to other CPUs */ + broadcast =3D cpumask_any_but(cmask, cpuid) < nr_cpu_ids; + } else { + cpumask_setall(&full_cmask); + cmask =3D &full_cmask; + broadcast =3D true; + } =20 - if (static_branch_unlikely(&use_asid_allocator)) + if (static_branch_unlikely(&use_asid_allocator) && mm) asid =3D atomic_long_read(&mm->context.id) & asid_mask; =20 if (broadcast) { @@ -128,7 +136,8 @@ static void __flush_tlb_range(struct mm_struct *mm, uns= igned long start, local_flush_tlb_range_asid(start, size, stride, asid); } =20 - put_cpu(); + if (mm) + put_cpu(); } =20 void flush_tlb_mm(struct mm_struct *mm) @@ -189,6 +198,12 @@ void flush_tlb_range(struct vm_area_struct *vma, unsig= ned long start, =20 __flush_tlb_range(vma->vm_mm, start, end - start, stride_size); } + +void flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + __flush_tlb_range(NULL, start, end - start, PAGE_SIZE); +} + #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) --=20 2.39.2