From nobody Fri Dec 19 03:44:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35632CA0EC8 for ; Mon, 11 Sep 2023 22:42:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378107AbjIKWaZ (ORCPT ); Mon, 11 Sep 2023 18:30:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237211AbjIKMPc (ORCPT ); Mon, 11 Sep 2023 08:15:32 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC8B8198; Mon, 11 Sep 2023 05:15:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694434527; x=1725970527; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tyR7vrTUqTU08Ju+QLeqb/DiAnQ3Ts82L5iKvQhwvII=; b=bV5WlB9ZvMxsWQsgtYP7gvNwH3UjnuzfUXG0fG6wcatmUVta5eBekOeQ Qn4lD1chojE+03q5a9mQHFxgaykDPcwugtnMo/pQ6jBZ9R2nUiJjWWnUt bpM7fPAo/QxSYqmYb08ZZLFUwll5IlAdtP8qigOxTrYjGI8Ns+WHWuXuX b4UPXsjZtRAKkD9Oh3OTDePlbXTra2MW/puG7dBl/g4jGTL0eYXsknFRH jtrfJn5Rcuz55lUGyrY9hEgnbeocmjtFhGGmzreCOIvF23WkT6YTwTn3F hJyTyj7sTdJoTrryhUGlGYH3pLXLu+td8PPgu1Y+O0On1XuhCJJjlENED Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10830"; a="381863531" X-IronPort-AV: E=Sophos;i="6.02,244,1688454000"; d="scan'208";a="381863531" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2023 05:15:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10830"; a="746383294" X-IronPort-AV: E=Sophos;i="6.02,244,1688454000"; d="scan'208";a="746383294" Received: from mzarkov-mobl3.ger.corp.intel.com (HELO ijarvine-mobl2.ger.corp.intel.com) ([10.252.36.200]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2023 05:15:22 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 4/8] PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields Date: Mon, 11 Sep 2023 15:14:57 +0300 Message-Id: <20230911121501.21910-5-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230911121501.21910-1-ilpo.jarvinen@linux.intel.com> References: <20230911121501.21910-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use FIELD_GET() to extract PCIe Negotiated Link Width field instead of custom masking and shifting. Similarly, change custom code that misleadingly used PCI_EXP_LNKSTA_NLW_SHIFT to prepare value for PCI_EXP_LNKCAP write to use FIELD_PREP() with correct field define (PCI_EXP_LNKCAP_MLW). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/controller/dwc/pcie-tegra194.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 4bba31502ce1..248cd9347e8f 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -9,6 +9,7 @@ * Author: Vidya Sagar */ =20 +#include #include #include #include @@ -346,8 +347,7 @@ static void apply_bad_link_workaround(struct dw_pcie_rp= *pp) */ val =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); if (val & PCI_EXP_LNKSTA_LBMS) { - current_link_width =3D (val & PCI_EXP_LNKSTA_NLW) >> - PCI_EXP_LNKSTA_NLW_SHIFT; + current_link_width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, val); if (pcie->init_link_width > current_link_width) { dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); val =3D dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + @@ -760,8 +760,7 @@ static void tegra_pcie_enable_system_interrupts(struct = dw_pcie_rp *pp) =20 val_w =3D dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); - pcie->init_link_width =3D (val_w & PCI_EXP_LNKSTA_NLW) >> - PCI_EXP_LNKSTA_NLW_SHIFT; + pcie->init_link_width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w); =20 val_w =3D dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL); @@ -920,7 +919,7 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *p= p) /* Configure Max lane width from DT */ val =3D dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); val &=3D ~PCI_EXP_LNKCAP_MLW; - val |=3D (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT); + val |=3D FIELD_PREP(PCI_EXP_LNKCAP_MLW, pcie->num_lanes); dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val); =20 /* Clear Slot Clock Configuration bit if SRNS configuration */ --=20 2.30.2