From nobody Fri Sep 20 11:41:21 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2A02CA0EC7 for ; Mon, 11 Sep 2023 22:43:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244045AbjIKWfX (ORCPT ); Mon, 11 Sep 2023 18:35:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237165AbjIKMIG (ORCPT ); Mon, 11 Sep 2023 08:08:06 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2643CEB; Mon, 11 Sep 2023 05:07:52 -0700 (PDT) X-UUID: d1d8ff6a509b11eea33bb35ae8d461a2-20230911 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=vo2+Ht37rnzqncUjP5jQLU3n66LjuW5bTm8lsUZgRBs=; b=cxjUr8GVZQ/7AK54Bk5oI274CX1haREkAjeEh3Db+TidObOT4GOkW9gYdK4DLL1FKQ39BOAoGC2jseNdmBuJznCXBRZMkBKNPVhidlGKoG1noHYhCKL1gpK00/EJ+L5e2PF5COI0go992Uhcnek3aqEFDwpDb8yGYUiLvY1ZUVw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:f52b5986-b4fe-48e9-ab8e-0c5296812f8a,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:0ad78a4,CLOUDID:bd71e4c2-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: d1d8ff6a509b11eea33bb35ae8d461a2-20230911 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2032066479; Mon, 11 Sep 2023 20:07:46 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.194) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 20:07:45 +0800 Received: from mszsdhlt06.gcn.mediatek.inc (10.16.6.206) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 20:07:44 +0800 From: Shuijing Li To: , , , , , , , , , CC: , , , , , , Shuijing Li Subject: [PATCH v4,2/3] drm/mediatek: dsi: Add dsi cmdq_ctl to send panel initial code Date: Mon, 11 Sep 2023 20:07:59 +0800 Message-ID: <20230911120800.17369-3-shuijing.li@mediatek.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230911120800.17369-1-shuijing.li@mediatek.com> References: <20230911120800.17369-1-shuijing.li@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For mt8188, add dsi cmdq reg control to send long packets to panel initialization. MT8188 hardware has been changed to automatically set the cmdq_size value by default when sending long packets. In this patch, the cmdq_size value is set manually instead. Remain consistent with previous IC. Signed-off-by: Shuijing Li Reviewed-by: AngeloGioacchino Del Regno --- Changes in v4: Add a comment per suggestion from the previous thread: https://lore.kernel.org/all/14e03873-3723-8293-0190-445a71828b25@collabora.= com/ Changes in v3: reorder patch 2/3 and 3/3, and describe more about why mt8188 need this patch, per suggestion from the previous thread: https://lore.kernel.org/lkml/411ddbf95e2c2298b84899065691d478069ec273.camel= @mediatek.com/ Changes in v2: use mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL); directl= y, per suggestion from the previous thread: https://lore.kernel.org/lkml/015f4c60-ed77-9e1f-8a6b-cda6e4f6ac93@gmail.com/ --- drivers/gpu/drm/mediatek/mtk_dsi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index d8bfc2cce54d..623aa829ef6b 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -86,6 +86,7 @@ =20 #define DSI_CMDQ_SIZE 0x60 #define CMDQ_SIZE 0x3f +#define CMDQ_SIZE_SEL BIT(15) =20 #define DSI_HSTX_CKL_WC 0x64 =20 @@ -178,6 +179,7 @@ struct mtk_dsi_driver_data { const u32 reg_cmdq_off; bool has_shadow_ctl; bool has_size_ctl; + bool cmdq_long_packet_ctl; }; =20 struct mtk_dsi { @@ -996,6 +998,10 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const st= ruct mipi_dsi_msg *msg) =20 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val); mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size); + if (dsi->driver_data->cmdq_long_packet_ctl) { + /* Disable setting cmdq_size automatically for long packets */ + mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL); + } } =20 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi, --=20 2.40.1