From nobody Thu Dec 18 08:16:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7495CCA0EC0 for ; Mon, 11 Sep 2023 21:30:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346844AbjIKVYD (ORCPT ); Mon, 11 Sep 2023 17:24:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235579AbjIKJCl (ORCPT ); Mon, 11 Sep 2023 05:02:41 -0400 Received: from out-210.mta1.migadu.com (out-210.mta1.migadu.com [95.215.58.210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80411CCD for ; Mon, 11 Sep 2023 02:02:35 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1694422953; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LndWoYmqwjtYxuiej2TnFNqBgTCS5sl6zf8MU2NSSKo=; b=gzjgehLqrp0Fh7xuROuGE/c2VQUjvV1DKEmoQQWzwwWfGzKKY0KHHzuhYNqLzZ+jBg8ZpD xQeFPFIjFfRAvmcp+n0bpn2p1SC2bKD2AOaxIrBv0dysNFj7kKd30m6wy5CAGZp8YMgwo0 w3hcsr0E3+W4SovSW8pCVIkoOdSx/eT0Wf8sDzwovfU2UAh5bPH2/Vgn1UukP42Zpn2cpb WqQ7oUOkYXD98mikxZKreoVvTwbYSZOSJEbH/k13GNuj308F9fJ8Tk/EBO1Z/Jl0bzhOwd zJhKLtSuWND9jXO4BoSKSWx7b84r3xZROB80hqwRCZDonMIMNO6A6J86vB1rKg== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Guo , Chris Morgan , Jagan Teki , John Watts , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 1/8] drm/panel: nv3052c: Document known register names Date: Mon, 11 Sep 2023 19:01:59 +1000 Message-ID: <20230911090206.3121440-2-contact@jookia.org> In-Reply-To: <20230911090206.3121440-1-contact@jookia.org> References: <20230911090206.3121440-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Many of these registers have a known name in the public datasheet. Document them as comments for reference. Signed-off-by: John Watts Reviewed-by: Jessica Zhang --- .../gpu/drm/panel/panel-newvision-nv3052c.c | 261 +++++++++--------- 1 file changed, 132 insertions(+), 129 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 71e57de6d8b2..589431523ce7 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -42,9 +42,9 @@ struct nv3052c_reg { }; =20 static const struct nv3052c_reg nv3052c_panel_regs[] =3D { - { 0xff, 0x30 }, - { 0xff, 0x52 }, - { 0xff, 0x01 }, + // EXTC Command set enable, select page 1 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, + // Mostly unknown registers { 0xe3, 0x00 }, { 0x40, 0x00 }, { 0x03, 0x40 }, @@ -62,15 +62,15 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = =3D { { 0x25, 0x06 }, { 0x26, 0x14 }, { 0x27, 0x14 }, - { 0x38, 0xcc }, - { 0x39, 0xd7 }, - { 0x3a, 0x4a }, + { 0x38, 0xcc }, // VCOM_ADJ1 + { 0x39, 0xd7 }, // VCOM_ADJ2 + { 0x3a, 0x4a }, // VCOM_ADJ3 { 0x28, 0x40 }, { 0x29, 0x01 }, { 0x2a, 0xdf }, { 0x49, 0x3c }, - { 0x91, 0x77 }, - { 0x92, 0x77 }, + { 0x91, 0x77 }, // EXTPW_CTRL2 + { 0x92, 0x77 }, // EXTPW_CTRL3 { 0xa0, 0x55 }, { 0xa1, 0x50 }, { 0xa4, 0x9c }, @@ -94,123 +94,126 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = =3D { { 0xb8, 0x26 }, { 0xf0, 0x00 }, { 0xf6, 0xc0 }, - { 0xff, 0x30 }, - { 0xff, 0x52 }, - { 0xff, 0x02 }, - { 0xb0, 0x0b }, - { 0xb1, 0x16 }, - { 0xb2, 0x17 }, - { 0xb3, 0x2c }, - { 0xb4, 0x32 }, - { 0xb5, 0x3b }, - { 0xb6, 0x29 }, - { 0xb7, 0x40 }, - { 0xb8, 0x0d }, - { 0xb9, 0x05 }, - { 0xba, 0x12 }, - { 0xbb, 0x10 }, - { 0xbc, 0x12 }, - { 0xbd, 0x15 }, - { 0xbe, 0x19 }, - { 0xbf, 0x0e }, - { 0xc0, 0x16 }, - { 0xc1, 0x0a }, - { 0xd0, 0x0c }, - { 0xd1, 0x17 }, - { 0xd2, 0x14 }, - { 0xd3, 0x2e }, - { 0xd4, 0x32 }, - { 0xd5, 0x3c }, - { 0xd6, 0x22 }, - { 0xd7, 0x3d }, - { 0xd8, 0x0d }, - { 0xd9, 0x07 }, - { 0xda, 0x13 }, - { 0xdb, 0x13 }, - { 0xdc, 0x11 }, - { 0xdd, 0x15 }, - { 0xde, 0x19 }, - { 0xdf, 0x10 }, - { 0xe0, 0x17 }, - { 0xe1, 0x0a }, - { 0xff, 0x30 }, - { 0xff, 0x52 }, - { 0xff, 0x03 }, - { 0x00, 0x2a }, - { 0x01, 0x2a }, - { 0x02, 0x2a }, - { 0x03, 0x2a }, - { 0x04, 0x61 }, - { 0x05, 0x80 }, - { 0x06, 0xc7 }, - { 0x07, 0x01 }, - { 0x08, 0x03 }, - { 0x09, 0x04 }, - { 0x70, 0x22 }, - { 0x71, 0x80 }, - { 0x30, 0x2a }, - { 0x31, 0x2a }, - { 0x32, 0x2a }, - { 0x33, 0x2a }, - { 0x34, 0x61 }, - { 0x35, 0xc5 }, - { 0x36, 0x80 }, - { 0x37, 0x23 }, - { 0x40, 0x03 }, - { 0x41, 0x04 }, - { 0x42, 0x05 }, - { 0x43, 0x06 }, - { 0x44, 0x11 }, - { 0x45, 0xe8 }, - { 0x46, 0xe9 }, - { 0x47, 0x11 }, - { 0x48, 0xea }, - { 0x49, 0xeb }, - { 0x50, 0x07 }, - { 0x51, 0x08 }, - { 0x52, 0x09 }, - { 0x53, 0x0a }, - { 0x54, 0x11 }, - { 0x55, 0xec }, - { 0x56, 0xed }, - { 0x57, 0x11 }, - { 0x58, 0xef }, - { 0x59, 0xf0 }, - { 0xb1, 0x01 }, - { 0xb4, 0x15 }, - { 0xb5, 0x16 }, - { 0xb6, 0x09 }, - { 0xb7, 0x0f }, - { 0xb8, 0x0d }, - { 0xb9, 0x0b }, - { 0xba, 0x00 }, - { 0xc7, 0x02 }, - { 0xca, 0x17 }, - { 0xcb, 0x18 }, - { 0xcc, 0x0a }, - { 0xcd, 0x10 }, - { 0xce, 0x0e }, - { 0xcf, 0x0c }, - { 0xd0, 0x00 }, - { 0x81, 0x00 }, - { 0x84, 0x15 }, - { 0x85, 0x16 }, - { 0x86, 0x10 }, - { 0x87, 0x0a }, - { 0x88, 0x0c }, - { 0x89, 0x0e }, - { 0x8a, 0x02 }, - { 0x97, 0x00 }, - { 0x9a, 0x17 }, - { 0x9b, 0x18 }, - { 0x9c, 0x0f }, - { 0x9d, 0x09 }, - { 0x9e, 0x0b }, - { 0x9f, 0x0d }, - { 0xa0, 0x01 }, - { 0xff, 0x30 }, - { 0xff, 0x52 }, - { 0xff, 0x02 }, + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Set gray scale voltage to adjust gamma + { 0xb0, 0x0b }, // PGAMVR0 + { 0xb1, 0x16 }, // PGAMVR1 + { 0xb2, 0x17 }, // PGAMVR2 + { 0xb3, 0x2c }, // PGAMVR3 + { 0xb4, 0x32 }, // PGAMVR4 + { 0xb5, 0x3b }, // PGAMVR5 + { 0xb6, 0x29 }, // PGAMPR0 + { 0xb7, 0x40 }, // PGAMPR1 + { 0xb8, 0x0d }, // PGAMPK0 + { 0xb9, 0x05 }, // PGAMPK1 + { 0xba, 0x12 }, // PGAMPK2 + { 0xbb, 0x10 }, // PGAMPK3 + { 0xbc, 0x12 }, // PGAMPK4 + { 0xbd, 0x15 }, // PGAMPK5 + { 0xbe, 0x19 }, // PGAMPK6 + { 0xbf, 0x0e }, // PGAMPK7 + { 0xc0, 0x16 }, // PGAMPK8 + { 0xc1, 0x0a }, // PGAMPK9 + // Set gray scale voltage to adjust gamma + { 0xd0, 0x0c }, // NGAMVR0 + { 0xd1, 0x17 }, // NGAMVR0 + { 0xd2, 0x14 }, // NGAMVR1 + { 0xd3, 0x2e }, // NGAMVR2 + { 0xd4, 0x32 }, // NGAMVR3 + { 0xd5, 0x3c }, // NGAMVR4 + { 0xd6, 0x22 }, // NGAMPR0 + { 0xd7, 0x3d }, // NGAMPR1 + { 0xd8, 0x0d }, // NGAMPK0 + { 0xd9, 0x07 }, // NGAMPK1 + { 0xda, 0x13 }, // NGAMPK2 + { 0xdb, 0x13 }, // NGAMPK3 + { 0xdc, 0x11 }, // NGAMPK4 + { 0xdd, 0x15 }, // NGAMPK5 + { 0xde, 0x19 }, // NGAMPK6 + { 0xdf, 0x10 }, // NGAMPK7 + { 0xe0, 0x17 }, // NGAMPK8 + { 0xe1, 0x0a }, // NGAMPK9 + // EXTC Command set enable, select page 3 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, + // Set various timing settings + { 0x00, 0x2a }, // GIP_VST_1 + { 0x01, 0x2a }, // GIP_VST_2 + { 0x02, 0x2a }, // GIP_VST_3 + { 0x03, 0x2a }, // GIP_VST_4 + { 0x04, 0x61 }, // GIP_VST_5 + { 0x05, 0x80 }, // GIP_VST_6 + { 0x06, 0xc7 }, // GIP_VST_7 + { 0x07, 0x01 }, // GIP_VST_8 + { 0x08, 0x03 }, // GIP_VST_9 + { 0x09, 0x04 }, // GIP_VST_10 + { 0x70, 0x22 }, // GIP_ECLK1 + { 0x71, 0x80 }, // GIP_ECLK2 + { 0x30, 0x2a }, // GIP_CLK_1 + { 0x31, 0x2a }, // GIP_CLK_2 + { 0x32, 0x2a }, // GIP_CLK_3 + { 0x33, 0x2a }, // GIP_CLK_4 + { 0x34, 0x61 }, // GIP_CLK_5 + { 0x35, 0xc5 }, // GIP_CLK_6 + { 0x36, 0x80 }, // GIP_CLK_7 + { 0x37, 0x23 }, // GIP_CLK_8 + { 0x40, 0x03 }, // GIP_CLKA_1 + { 0x41, 0x04 }, // GIP_CLKA_2 + { 0x42, 0x05 }, // GIP_CLKA_3 + { 0x43, 0x06 }, // GIP_CLKA_4 + { 0x44, 0x11 }, // GIP_CLKA_5 + { 0x45, 0xe8 }, // GIP_CLKA_6 + { 0x46, 0xe9 }, // GIP_CLKA_7 + { 0x47, 0x11 }, // GIP_CLKA_8 + { 0x48, 0xea }, // GIP_CLKA_9 + { 0x49, 0xeb }, // GIP_CLKA_10 + { 0x50, 0x07 }, // GIP_CLKB_1 + { 0x51, 0x08 }, // GIP_CLKB_2 + { 0x52, 0x09 }, // GIP_CLKB_3 + { 0x53, 0x0a }, // GIP_CLKB_4 + { 0x54, 0x11 }, // GIP_CLKB_5 + { 0x55, 0xec }, // GIP_CLKB_6 + { 0x56, 0xed }, // GIP_CLKB_7 + { 0x57, 0x11 }, // GIP_CLKB_8 + { 0x58, 0xef }, // GIP_CLKB_9 + { 0x59, 0xf0 }, // GIP_CLKB_10 + // Map internal GOA signals to GOA output pad + { 0xb1, 0x01 }, // PANELD2U2 + { 0xb4, 0x15 }, // PANELD2U5 + { 0xb5, 0x16 }, // PANELD2U6 + { 0xb6, 0x09 }, // PANELD2U7 + { 0xb7, 0x0f }, // PANELD2U8 + { 0xb8, 0x0d }, // PANELD2U9 + { 0xb9, 0x0b }, // PANELD2U10 + { 0xba, 0x00 }, // PANELD2U11 + { 0xc7, 0x02 }, // PANELD2U24 + { 0xca, 0x17 }, // PANELD2U27 + { 0xcb, 0x18 }, // PANELD2U28 + { 0xcc, 0x0a }, // PANELD2U29 + { 0xcd, 0x10 }, // PANELD2U30 + { 0xce, 0x0e }, // PANELD2U31 + { 0xcf, 0x0c }, // PANELD2U32 + { 0xd0, 0x00 }, // PANELD2U33 + // Map internal GOA signals to GOA output pad + { 0x81, 0x00 }, // PANELU2D2 + { 0x84, 0x15 }, // PANELU2D5 + { 0x85, 0x16 }, // PANELU2D6 + { 0x86, 0x10 }, // PANELU2D7 + { 0x87, 0x0a }, // PANELU2D8 + { 0x88, 0x0c }, // PANELU2D9 + { 0x89, 0x0e }, // PANELU2D10 + { 0x8a, 0x02 }, // PANELU2D11 + { 0x97, 0x00 }, // PANELU2D24 + { 0x9a, 0x17 }, // PANELU2D27 + { 0x9b, 0x18 }, // PANELU2D28 + { 0x9c, 0x0f }, // PANELU2D29 + { 0x9d, 0x09 }, // PANELU2D30 + { 0x9e, 0x0b }, // PANELU2D31 + { 0x9f, 0x0d }, // PANELU2D32 + { 0xa0, 0x01 }, // PANELU2D33 + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Unknown registers { 0x01, 0x01 }, { 0x02, 0xda }, { 0x03, 0xba }, @@ -227,10 +230,10 @@ static const struct nv3052c_reg nv3052c_panel_regs[] = =3D { { 0x0e, 0x48 }, { 0x0f, 0x38 }, { 0x10, 0x2b }, - { 0xff, 0x30 }, - { 0xff, 0x52 }, - { 0xff, 0x00 }, - { 0x36, 0x0a }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, + // Display Access Control + { 0x36, 0x0a }, // bgr =3D 1, ss =3D 1, gs =3D 0 }; =20 static inline struct nv3052c *to_nv3052c(struct drm_panel *panel) --=20 2.42.0 From nobody Thu Dec 18 08:16:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFB99CA0ED3 for ; Mon, 11 Sep 2023 22:11:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240121AbjIKWJv (ORCPT ); Mon, 11 Sep 2023 18:09:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235582AbjIKJCs (ORCPT ); Mon, 11 Sep 2023 05:02:48 -0400 Received: from out-219.mta1.migadu.com (out-219.mta1.migadu.com [95.215.58.219]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A29AFCCD for ; Mon, 11 Sep 2023 02:02:42 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1694422961; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ekcF3Bi8RuigTkjZz8yzaTQ4wC4D41rIRScarwtkG1A=; b=Rx1r9SCTGSwY+YD2ad9mfOyDPYx1WNVtFqwZXiCvMHLHoy8kAJe697YPbr/Mp2BpRHLik5 /DOx4El0C+uDkEI9kDmJTmfzQ8/UB5TQ3HZkDIotigbp+PKxMp2QokuMq0prVCfGGroD+M CFuwGn1sezZV47xjpD0lo/UfDowOnsYoYD47rHXsdXKKqVesf8qaeniH//MCFpTufLsFOe QE9zywaXZtjq/REHTCCXNYAnTFQxXMSjFnIbI9MUrUjZD/NRHNbt38ZE9YIaG9k/ilE+XD Rl7F4KRQNQTS1uuY5BUd84Nx2ugwIFwwGWLJZeS+a+3vAthZ5oIs3h8cVNfSIA== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Guo , Chris Morgan , Jagan Teki , John Watts , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/8] drm/panel: nv3052c: Add SPI device IDs Date: Mon, 11 Sep 2023 19:02:00 +1000 Message-ID: <20230911090206.3121440-3-contact@jookia.org> In-Reply-To: <20230911090206.3121440-1-contact@jookia.org> References: <20230911090206.3121440-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SPI drivers needs their own list of compatible device IDs in order for automatic module loading to work. Add those for this driver. Signed-off-by: John Watts Reviewed-by: Jessica Zhang --- drivers/gpu/drm/panel/panel-newvision-nv3052c.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 589431523ce7..90dea21f9856 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -465,6 +465,12 @@ static const struct nv3052c_panel_info ltk035c5444t_pa= nel_info =3D { .bus_flags =3D DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, }; =20 +static const struct spi_device_id nv3052c_ids[] =3D { + { "ltk035c5444t", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(spi, nv3052c_ids); + static const struct of_device_id nv3052c_of_match[] =3D { { .compatible =3D "leadtek,ltk035c5444t", .data =3D <k035c5444t_panel_i= nfo }, { /* sentinel */ } @@ -476,6 +482,7 @@ static struct spi_driver nv3052c_driver =3D { .name =3D "nv3052c", .of_match_table =3D nv3052c_of_match, }, + .id_table =3D nv3052c_ids, .probe =3D nv3052c_probe, .remove =3D nv3052c_remove, }; --=20 2.42.0 From nobody Thu Dec 18 08:16:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFFD9CA0EC6 for ; Mon, 11 Sep 2023 22:50:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1355620AbjIKWBb (ORCPT ); Mon, 11 Sep 2023 18:01:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235588AbjIKJCy (ORCPT ); Mon, 11 Sep 2023 05:02:54 -0400 Received: from out-210.mta0.migadu.com (out-210.mta0.migadu.com [IPv6:2001:41d0:1004:224b::d2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B20ECD3 for ; Mon, 11 Sep 2023 02:02:50 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1694422968; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QEybRG/z/QiYL8x5ls+wYPU1myIjvupP8IAsRIKh5xg=; b=L4zZ4w9E6I3vJ/yHBEDZ7bNzpDYIxT6oC471yPAYUPUVy8khFrdLFoGbR4WnLs5hsEKiSB yHusLh1PHnuyZPA4BNjhQBBidEshgfx5A1dEMNboZAcGagMxOFU01LEPA1AhaKM0pNg4+T 5nup4MOhOpwkbTG3+NfIxAg1IaJukZKvnmP/o9Sd2LGDG4Wp9T5zYTAh9vWlDXqO40veRm UTNMhxi2NR7MUecIEaC/BmngFO7QdNK3jP2iIgbRBiGGA8JVXo7DrkU9dgyTsqn6Tdo7Zs dxjoikuMXmYExpEv8H61JgiNqhxL+cRz+YzU810n4zRb9NmmP0v+LKEwvw86Gg== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Guo , Chris Morgan , Jagan Teki , John Watts , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 3/8] drm/panel: nv3052c: Sleep for 150ms after reset Date: Mon, 11 Sep 2023 19:02:01 +1000 Message-ID: <20230911090206.3121440-4-contact@jookia.org> In-Reply-To: <20230911090206.3121440-1-contact@jookia.org> References: <20230911090206.3121440-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The current code waits after resets for 5 to 20 milliseconds. This is appropriate when resetting a sleeping panel, but an awake panel requires at least 120ms of waiting. Sleep for 150ms so the panel always completes it reset properly. Signed-off-by: John Watts --- drivers/gpu/drm/panel/panel-newvision-nv3052c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 90dea21f9856..2526b123b1f5 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -258,7 +258,7 @@ static int nv3052c_prepare(struct drm_panel *panel) gpiod_set_value_cansleep(priv->reset_gpio, 1); usleep_range(10, 1000); gpiod_set_value_cansleep(priv->reset_gpio, 0); - usleep_range(5000, 20000); + msleep(150); =20 for (i =3D 0; i < ARRAY_SIZE(nv3052c_panel_regs); i++) { err =3D mipi_dbi_command(dbi, nv3052c_panel_regs[i].cmd, --=20 2.42.0 From nobody Thu Dec 18 08:16:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 072ABCA0EC1 for ; Mon, 11 Sep 2023 21:27:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344766AbjIKVTH (ORCPT ); Mon, 11 Sep 2023 17:19:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235592AbjIKJDC (ORCPT ); Mon, 11 Sep 2023 05:03:02 -0400 Received: from out-228.mta0.migadu.com (out-228.mta0.migadu.com [IPv6:2001:41d0:1004:224b::e4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7A32CCC for ; Mon, 11 Sep 2023 02:02:57 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1694422976; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZJIBmn1MRAFelLIOs/v4ao97mYf3xkRoyjgfFYfZY14=; b=h2+CPJ5n6FG/Sg7078ZD3xLsQBydsH9E9T2kRBW1UChwcxUUeiN7x/F0k4vsInj4jTgvtX NRqXYUYQoIgDckiKjbCC7flEEBc7uD518qyFptvoSJ0/F0Yeyb5EfPr7JZjqHg0dsn4zjt Qi+wBWdCDhVjvcXZTue1HQryypiAlAqKoruQrmqBN7WACzt+Nma2LH4B0E3fdlw+FinEu1 ABj/50O1c21W5dPvPYiWHFPgjWMM2e/zphNMR8eTF4CsmE9XGKwF39VveVx7IPeRdYumKv vxoVY6+w+9IleTP3RwzNWEt4zrYiTYH5VKRtXB6m/wARvzQzWdmpJFnQP5ZLCA== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Guo , Chris Morgan , Jagan Teki , John Watts , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 4/8] drm/panel: nv3052c: Wait before entering sleep mode Date: Mon, 11 Sep 2023 19:02:02 +1000 Message-ID: <20230911090206.3121440-5-contact@jookia.org> In-Reply-To: <20230911090206.3121440-1-contact@jookia.org> References: <20230911090206.3121440-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The panel needs us to wait 120ms between exiting and entering sleep. Guarantee that by always waiting 150ms before entering sleep mode. Signed-off-by: John Watts --- drivers/gpu/drm/panel/panel-newvision-nv3052c.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 2526b123b1f5..307335d0f1fc 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -289,6 +289,9 @@ static int nv3052c_unprepare(struct drm_panel *panel) struct mipi_dbi *dbi =3D &priv->dbi; int err; =20 + /* Wait 150ms in case we just exited sleep mode */ + msleep(150); + err =3D mipi_dbi_command(dbi, MIPI_DCS_ENTER_SLEEP_MODE); if (err) dev_err(priv->dev, "Unable to enter sleep mode: %d\n", err); --=20 2.42.0 From nobody Thu Dec 18 08:16:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75A04CA0ECD for ; Mon, 11 Sep 2023 22:24:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377436AbjIKWVd (ORCPT ); Mon, 11 Sep 2023 18:21:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235594AbjIKJDK (ORCPT ); Mon, 11 Sep 2023 05:03:10 -0400 Received: from out-220.mta1.migadu.com (out-220.mta1.migadu.com [95.215.58.220]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36D1ECCD for ; Mon, 11 Sep 2023 02:03:06 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1694422984; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ICC/SzyHwq6OWg2Vbcao+ENYPJZEyCaFguUig4QftpI=; b=zDWg5jC2P6F0x0iELGO62R3P8c638vuT/a7cEaoY5Uuy8K6n2rNcqYHcvMflGSOz7hmpXC clmQSzjrLcwD9IHkIjIKuaR8VkkAG+2POyviG/5e86djVfoqxYgj2cwa8u/2nQSXcTohqf +mUoIofWCtok+FoHwXPMG/VQUAxRO/fx5fUiq1RMWmCx2zx+2LniQ6PPVuEUz8caQSNOxe D9jDXe0O3dVub+j0ZETWRC4qZFWtXiuXDfU72zDrtpbxfvbxEvW/nIR6oLN3cQ0aPvLPDh 2Ypki3ORVtzkxwYYAfABmeXbTXP/Kd2e0OHuea/2MhKoPdKl5NF2N3Bb43UkvQ== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Guo , Chris Morgan , Jagan Teki , John Watts , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 5/8] drm/panel: nv3052c: Allow specifying registers per panel Date: Mon, 11 Sep 2023 19:02:03 +1000 Message-ID: <20230911090206.3121440-6-contact@jookia.org> In-Reply-To: <20230911090206.3121440-1-contact@jookia.org> References: <20230911090206.3121440-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Panel initialization registers are per-display and not tied to the controller itself. Different panels will specify their own registers. Attach the sequences to the panel info struct so future panels can specify their own sequences. Signed-off-by: John Watts Reviewed-by: Jessica Zhang --- .../gpu/drm/panel/panel-newvision-nv3052c.c | 25 ++++++++++++------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 307335d0f1fc..b2ad9b3a5eb7 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -20,11 +20,18 @@ #include #include =20 +struct nv3052c_reg { + u8 cmd; + u8 val; +}; + struct nv3052c_panel_info { const struct drm_display_mode *display_modes; unsigned int num_modes; u16 width_mm, height_mm; u32 bus_format, bus_flags; + const struct nv3052c_reg *panel_regs; + int panel_regs_len; }; =20 struct nv3052c { @@ -36,12 +43,7 @@ struct nv3052c { struct gpio_desc *reset_gpio; }; =20 -struct nv3052c_reg { - u8 cmd; - u8 val; -}; - -static const struct nv3052c_reg nv3052c_panel_regs[] =3D { +static const struct nv3052c_reg ltk035c5444t_panel_regs[] =3D { // EXTC Command set enable, select page 1 { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, // Mostly unknown registers @@ -244,6 +246,7 @@ static inline struct nv3052c *to_nv3052c(struct drm_pan= el *panel) static int nv3052c_prepare(struct drm_panel *panel) { struct nv3052c *priv =3D to_nv3052c(panel); + const struct nv3052c_reg *panel_regs =3D priv->panel_info->panel_regs; struct mipi_dbi *dbi =3D &priv->dbi; unsigned int i; int err; @@ -260,9 +263,11 @@ static int nv3052c_prepare(struct drm_panel *panel) gpiod_set_value_cansleep(priv->reset_gpio, 0); msleep(150); =20 - for (i =3D 0; i < ARRAY_SIZE(nv3052c_panel_regs); i++) { - err =3D mipi_dbi_command(dbi, nv3052c_panel_regs[i].cmd, - nv3052c_panel_regs[i].val); + int panel_regs_len =3D priv->panel_info->panel_regs_len; + + for (i =3D 0; i < panel_regs_len; i++) { + err =3D mipi_dbi_command(dbi, panel_regs[i].cmd, + panel_regs[i].val); =20 if (err) { dev_err(priv->dev, "Unable to set register: %d\n", err); @@ -466,6 +471,8 @@ static const struct nv3052c_panel_info ltk035c5444t_pan= el_info =3D { .height_mm =3D 64, .bus_format =3D MEDIA_BUS_FMT_RGB888_1X24, .bus_flags =3D DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, + .panel_regs =3D ltk035c5444t_panel_regs, + .panel_regs_len =3D ARRAY_SIZE(ltk035c5444t_panel_regs), }; =20 static const struct spi_device_id nv3052c_ids[] =3D { --=20 2.42.0 From nobody Thu Dec 18 08:16:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 680F0CA0ECC for ; Mon, 11 Sep 2023 21:21:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344764AbjIKVOo (ORCPT ); Mon, 11 Sep 2023 17:14:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235598AbjIKJDT (ORCPT ); Mon, 11 Sep 2023 05:03:19 -0400 Received: from out-221.mta0.migadu.com (out-221.mta0.migadu.com [91.218.175.221]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86D87CCC for ; Mon, 11 Sep 2023 02:03:14 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1694422992; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KO0iN5pcufvitjkyFg21lI/JgJaYK3wy6vmVBmRt3vw=; b=f9nn7RmZSLcay4M2vismbLFTejBcVnxPlxLp52UH95dxJNICiClVQrq+9OWmxsIrKoiMfB Wv2jhI/pHrHwnsqFe+F9u6Hl5gJOAC0GBcYrYzSCNJ9iVprL1lYbarEyWqTZs51wQYnOGE rCK5BpYGQqHXl9TlTu5CIiX8H8AyBfa6LKr1lbtGxyT6q05H4LllHQEyGm2UZGLaTs495N VBOFnfJ0Aq1wy5ZTEc86cjCngFs3RRC5vc5KrA9Q5LSqxkvcMm5lvQOHH1vvtdvB0d2SpB ibYrJ9JOrQTLvHJtFndCYlaBrjYo1dokhWjmGG3FgVyeNOajAky0tcRMzaYAgg== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Guo , Chris Morgan , Jagan Teki , John Watts , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 6/8] drm/panel: nv3052c: Add Fascontek FS035VG158 LCD display Date: Mon, 11 Sep 2023 19:02:04 +1000 Message-ID: <20230911090206.3121440-7-contact@jookia.org> In-Reply-To: <20230911090206.3121440-1-contact@jookia.org> References: <20230911090206.3121440-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This display is extremely similar to the LTK035C5444T, but still has some minor variations in panel initialization. Signed-off-by: John Watts --- .../gpu/drm/panel/panel-newvision-nv3052c.c | 223 ++++++++++++++++++ 1 file changed, 223 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index b2ad9b3a5eb7..3b1ec34491f1 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -238,6 +238,201 @@ static const struct nv3052c_reg ltk035c5444t_panel_re= gs[] =3D { { 0x36, 0x0a }, // bgr =3D 1, ss =3D 1, gs =3D 0 }; =20 +static const struct nv3052c_reg fs035vg158_panel_regs[] =3D { + // EXTC Command set enable, select page 1 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, + // Mostly unknown registers + { 0xe3, 0x00 }, + { 0x40, 0x00 }, + { 0x03, 0x40 }, + { 0x04, 0x00 }, + { 0x05, 0x03 }, + { 0x08, 0x00 }, + { 0x09, 0x07 }, + { 0x0a, 0x01 }, + { 0x0b, 0x32 }, + { 0x0c, 0x32 }, + { 0x0d, 0x0b }, + { 0x0e, 0x00 }, + { 0x23, 0x20 }, // RGB interface control: DE MODE PCLK-N + { 0x24, 0x0c }, + { 0x25, 0x06 }, + { 0x26, 0x14 }, + { 0x27, 0x14 }, + { 0x38, 0x9c }, //VCOM_ADJ1, different to ltk035c5444t + { 0x39, 0xa7 }, //VCOM_ADJ2, different to ltk035c5444t + { 0x3a, 0x50 }, //VCOM_ADJ3, different to ltk035c5444t + { 0x28, 0x40 }, + { 0x29, 0x01 }, + { 0x2a, 0xdf }, + { 0x49, 0x3c }, + { 0x91, 0x57 }, //EXTPW_CTRL2, different to ltk035c5444t + { 0x92, 0x57 }, //EXTPW_CTRL3, different to ltk035c5444t + { 0xa0, 0x55 }, + { 0xa1, 0x50 }, + { 0xa4, 0x9c }, + { 0xa7, 0x02 }, + { 0xa8, 0x01 }, + { 0xa9, 0x01 }, + { 0xaa, 0xfc }, + { 0xab, 0x28 }, + { 0xac, 0x06 }, + { 0xad, 0x06 }, + { 0xae, 0x06 }, + { 0xaf, 0x03 }, + { 0xb0, 0x08 }, + { 0xb1, 0x26 }, + { 0xb2, 0x28 }, + { 0xb3, 0x28 }, + { 0xb4, 0x03 }, // Unknown, different to ltk035c5444 + { 0xb5, 0x08 }, + { 0xb6, 0x26 }, + { 0xb7, 0x08 }, + { 0xb8, 0x26 }, + { 0xf0, 0x00 }, + { 0xf6, 0xc0 }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Set gray scale voltage to adjust gamma + { 0xb0, 0x0b }, // PGAMVR0 + { 0xb1, 0x16 }, // PGAMVR1 + { 0xb2, 0x17 }, // PGAMVR2 + { 0xb3, 0x2c }, // PGAMVR3 + { 0xb4, 0x32 }, // PGAMVR4 + { 0xb5, 0x3b }, // PGAMVR5 + { 0xb6, 0x29 }, // PGAMPR0 + { 0xb7, 0x40 }, // PGAMPR1 + { 0xb8, 0x0d }, // PGAMPK0 + { 0xb9, 0x05 }, // PGAMPK1 + { 0xba, 0x12 }, // PGAMPK2 + { 0xbb, 0x10 }, // PGAMPK3 + { 0xbc, 0x12 }, // PGAMPK4 + { 0xbd, 0x15 }, // PGAMPK5 + { 0xbe, 0x19 }, // PGAMPK6 + { 0xbf, 0x0e }, // PGAMPK7 + { 0xc0, 0x16 }, // PGAMPK8 + { 0xc1, 0x0a }, // PGAMPK9 + // Set gray scale voltage to adjust gamma + { 0xd0, 0x0c }, // NGAMVR0 + { 0xd1, 0x17 }, // NGAMVR0 + { 0xd2, 0x14 }, // NGAMVR1 + { 0xd3, 0x2e }, // NGAMVR2 + { 0xd4, 0x32 }, // NGAMVR3 + { 0xd5, 0x3c }, // NGAMVR4 + { 0xd6, 0x22 }, // NGAMPR0 + { 0xd7, 0x3d }, // NGAMPR1 + { 0xd8, 0x0d }, // NGAMPK0 + { 0xd9, 0x07 }, // NGAMPK1 + { 0xda, 0x13 }, // NGAMPK2 + { 0xdb, 0x13 }, // NGAMPK3 + { 0xdc, 0x11 }, // NGAMPK4 + { 0xdd, 0x15 }, // NGAMPK5 + { 0xde, 0x19 }, // NGAMPK6 + { 0xdf, 0x10 }, // NGAMPK7 + { 0xe0, 0x17 }, // NGAMPK8 + { 0xe1, 0x0a }, // NGAMPK9 + // EXTC Command set enable, select page 3 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, + // Set various timing settings + { 0x00, 0x2a }, // GIP_VST_1 + { 0x01, 0x2a }, // GIP_VST_2 + { 0x02, 0x2a }, // GIP_VST_3 + { 0x03, 0x2a }, // GIP_VST_4 + { 0x04, 0x61 }, // GIP_VST_5 + { 0x05, 0x80 }, // GIP_VST_6 + { 0x06, 0xc7 }, // GIP_VST_7 + { 0x07, 0x01 }, // GIP_VST_8 + { 0x08, 0x03 }, // GIP_VST_9 + { 0x09, 0x04 }, // GIP_VST_10 + { 0x70, 0x22 }, // GIP_ECLK1 + { 0x71, 0x80 }, // GIP_ECLK2 + { 0x30, 0x2a }, // GIP_CLK_1 + { 0x31, 0x2a }, // GIP_CLK_2 + { 0x32, 0x2a }, // GIP_CLK_3 + { 0x33, 0x2a }, // GIP_CLK_4 + { 0x34, 0x61 }, // GIP_CLK_5 + { 0x35, 0xc5 }, // GIP_CLK_6 + { 0x36, 0x80 }, // GIP_CLK_7 + { 0x37, 0x23 }, // GIP_CLK_8 + { 0x40, 0x03 }, // GIP_CLKA_1 + { 0x41, 0x04 }, // GIP_CLKA_2 + { 0x42, 0x05 }, // GIP_CLKA_3 + { 0x43, 0x06 }, // GIP_CLKA_4 + { 0x44, 0x11 }, // GIP_CLKA_5 + { 0x45, 0xe8 }, // GIP_CLKA_6 + { 0x46, 0xe9 }, // GIP_CLKA_7 + { 0x47, 0x11 }, // GIP_CLKA_8 + { 0x48, 0xea }, // GIP_CLKA_9 + { 0x49, 0xeb }, // GIP_CLKA_10 + { 0x50, 0x07 }, // GIP_CLKB_1 + { 0x51, 0x08 }, // GIP_CLKB_2 + { 0x52, 0x09 }, // GIP_CLKB_3 + { 0x53, 0x0a }, // GIP_CLKB_4 + { 0x54, 0x11 }, // GIP_CLKB_5 + { 0x55, 0xec }, // GIP_CLKB_6 + { 0x56, 0xed }, // GIP_CLKB_7 + { 0x57, 0x11 }, // GIP_CLKB_8 + { 0x58, 0xef }, // GIP_CLKB_9 + { 0x59, 0xf0 }, // GIP_CLKB_10 + // Map internal GOA signals to GOA output pad + { 0xb1, 0x01 }, // PANELD2U2 + { 0xb4, 0x15 }, // PANELD2U5 + { 0xb5, 0x16 }, // PANELD2U6 + { 0xb6, 0x09 }, // PANELD2U7 + { 0xb7, 0x0f }, // PANELD2U8 + { 0xb8, 0x0d }, // PANELD2U9 + { 0xb9, 0x0b }, // PANELD2U10 + { 0xba, 0x00 }, // PANELD2U11 + { 0xc7, 0x02 }, // PANELD2U24 + { 0xca, 0x17 }, // PANELD2U27 + { 0xcb, 0x18 }, // PANELD2U28 + { 0xcc, 0x0a }, // PANELD2U29 + { 0xcd, 0x10 }, // PANELD2U30 + { 0xce, 0x0e }, // PANELD2U31 + { 0xcf, 0x0c }, // PANELD2U32 + { 0xd0, 0x00 }, // PANELD2U33 + // Map internal GOA signals to GOA output pad + { 0x81, 0x00 }, // PANELU2D2 + { 0x84, 0x15 }, // PANELU2D5 + { 0x85, 0x16 }, // PANELU2D6 + { 0x86, 0x10 }, // PANELU2D7 + { 0x87, 0x0a }, // PANELU2D8 + { 0x88, 0x0c }, // PANELU2D9 + { 0x89, 0x0e }, // PANELU2D10 + { 0x8a, 0x02 }, // PANELU2D11 + { 0x97, 0x00 }, // PANELU2D24 + { 0x9a, 0x17 }, // PANELU2D27 + { 0x9b, 0x18 }, // PANELU2D28 + { 0x9c, 0x0f }, // PANELU2D29 + { 0x9d, 0x09 }, // PANELU2D30 + { 0x9e, 0x0b }, // PANELU2D31 + { 0x9f, 0x0d }, // PANELU2D32 + { 0xa0, 0x01 }, // PANELU2D33 + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Unknown registers + { 0x01, 0x01 }, + { 0x02, 0xda }, + { 0x03, 0xba }, + { 0x04, 0xa8 }, + { 0x05, 0x9a }, + { 0x06, 0x70 }, + { 0x07, 0xff }, + { 0x08, 0x91 }, + { 0x09, 0x90 }, + { 0x0a, 0xff }, + { 0x0b, 0x8f }, + { 0x0c, 0x60 }, + { 0x0d, 0x58 }, + { 0x0e, 0x48 }, + { 0x0f, 0x38 }, + { 0x10, 0x2b }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, + // Display Access Control + { 0x36, 0x0a }, // bgr =3D 1, ss =3D 1, gs =3D 0 +}; + static inline struct nv3052c *to_nv3052c(struct drm_panel *panel) { return container_of(panel, struct nv3052c, panel); @@ -464,6 +659,21 @@ static const struct drm_display_mode ltk035c5444t_mode= s[] =3D { }, }; =20 +static const struct drm_display_mode fs035vg158_modes[] =3D { + { /* 60 Hz */ + .clock =3D 21000, + .hdisplay =3D 640, + .hsync_start =3D 640 + 34, + .hsync_end =3D 640 + 34 + 4, + .htotal =3D 640 + 34 + 4 + 20, + .vdisplay =3D 480, + .vsync_start =3D 480 + 12, + .vsync_end =3D 480 + 12 + 4, + .vtotal =3D 480 + 12 + 4 + 6, + .flags =3D DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + }, +}; + static const struct nv3052c_panel_info ltk035c5444t_panel_info =3D { .display_modes =3D ltk035c5444t_modes, .num_modes =3D ARRAY_SIZE(ltk035c5444t_modes), @@ -475,14 +685,27 @@ static const struct nv3052c_panel_info ltk035c5444t_p= anel_info =3D { .panel_regs_len =3D ARRAY_SIZE(ltk035c5444t_panel_regs), }; =20 +static const struct nv3052c_panel_info fs035vg158_panel_info =3D { + .display_modes =3D fs035vg158_modes, + .num_modes =3D ARRAY_SIZE(fs035vg158_modes), + .width_mm =3D 70, + .height_mm =3D 53, + .bus_format =3D MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags =3D DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, + .panel_regs =3D fs035vg158_panel_regs, + .panel_regs_len =3D ARRAY_SIZE(fs035vg158_panel_regs), +}; + static const struct spi_device_id nv3052c_ids[] =3D { { "ltk035c5444t", }, + { "fs035vg158", }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(spi, nv3052c_ids); =20 static const struct of_device_id nv3052c_of_match[] =3D { { .compatible =3D "leadtek,ltk035c5444t", .data =3D <k035c5444t_panel_i= nfo }, + { .compatible =3D "fascontek,fs035vg158", .data =3D &fs035vg158_panel_inf= o }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, nv3052c_of_match); --=20 2.42.0 From nobody Thu Dec 18 08:16:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B7C1CA0EC7 for ; Mon, 11 Sep 2023 22:24:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377325AbjIKWVX (ORCPT ); Mon, 11 Sep 2023 18:21:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235602AbjIKJD0 (ORCPT ); Mon, 11 Sep 2023 05:03:26 -0400 Received: from out-220.mta1.migadu.com (out-220.mta1.migadu.com [95.215.58.220]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01ADDCCC for ; Mon, 11 Sep 2023 02:03:21 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1694423000; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gjbKgFOz59nnUk71iTtHr1/2T5zg9+ijv4cv5B921ro=; b=OdFPW17OCefsBXB8LZh2xRN8zTCx0ZFoCi6B82sw4yoRkj3g8z4TAqtEVYtyrcRXZDGlg1 WdOgloklI96tfYjBmSYofmu1yOBSy8sMgYNCx0UnLKPyH3zRUltfPYkltjaTF+5ZKkcP09 3VRSQ9c2EV+3T4rpNpKMSrrN27r47dNMckFdYloyzJve+sisunJwMClNbsmbxzgZyKEhv3 5jaUcs3LMrHTQBmLXFNBwKYpO54Xw0iDkAcjAza9gCtY07Y9JCCpWQzpHQxE9JadMKAkE2 5AN4LlCTwOoM2zboHKhbiiB00cxipZO29G9a6hGC6DV3neZieRH+woY7JKTnZw== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Guo , Chris Morgan , Jagan Teki , John Watts , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 7/8] dt-bindings: vendor-prefixes: Add fascontek Date: Mon, 11 Sep 2023 19:02:05 +1000 Message-ID: <20230911090206.3121440-8-contact@jookia.org> In-Reply-To: <20230911090206.3121440-1-contact@jookia.org> References: <20230911090206.3121440-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fascontek manufactures LCD panels such as the FS035VG158. Signed-off-by: John Watts Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 573578db9509..69befb76b6ce 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -468,6 +468,8 @@ patternProperties: description: Fairphone B.V. "^faraday,.*": description: Faraday Technology Corporation + "^fascontek,.*": + description: Fascontek "^fastrax,.*": description: Fastrax Oy "^fcs,.*": --=20 2.42.0 From nobody Thu Dec 18 08:16:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A1F0CA0ECF for ; Mon, 11 Sep 2023 21:58:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354940AbjIKVzu (ORCPT ); Mon, 11 Sep 2023 17:55:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235611AbjIKJDf (ORCPT ); Mon, 11 Sep 2023 05:03:35 -0400 Received: from out-211.mta0.migadu.com (out-211.mta0.migadu.com [91.218.175.211]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2698FCCD for ; Mon, 11 Sep 2023 02:03:30 -0700 (PDT) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1694423008; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=A+17NGCWlO9ZPfr0by0avVLIVRjlYOBsfODw41O82xI=; b=e5n3NPR+qdfHu6HoJXg9ALnUGk/dkhRjS3SpTdMdr6uxm5Y1XcSCWd/hmyOImWSUMARX2f Oq82kTOx1z1Jd3del9L9FhEjogil25q2AAPIj4dDhiE+ylp4isUIvB9Q/AbGYhFNbjmHaK gVnfl/WRegKz2vkehk7hcHUEgnQB58Hk9Fx3nFkaIuM8YZmuP03W39wu91bhGYtEZuI1dT QJ7UqyXWysIex5J6RXL8X3vUkQwNaHuu9/QNhVkSu/MD5FzJxJ0vQ3/Au/9sZO1EgvbTd9 7TV+44e3oaCoJjUH24oI9OuSRn6PXOWxe4uDhCLIX3HNOFwcOfJ+pp7zEgMuLA== From: John Watts To: dri-devel@lists.freedesktop.org Cc: Neil Armstrong , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Guo , Chris Morgan , Jagan Teki , John Watts , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 8/8] dt-bindings: display: panel: add Fascontek FS035VG158 panel Date: Mon, 11 Sep 2023 19:02:06 +1000 Message-ID: <20230911090206.3121440-9-contact@jookia.org> In-Reply-To: <20230911090206.3121440-1-contact@jookia.org> References: <20230911090206.3121440-1-contact@jookia.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a small 3.5" 640x480 IPS LCD panel. Signed-off-by: John Watts --- .../display/panel/fascontek,fs035vg158.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/fascont= ek,fs035vg158.yaml diff --git a/Documentation/devicetree/bindings/display/panel/fascontek,fs03= 5vg158.yaml b/Documentation/devicetree/bindings/display/panel/fascontek,fs0= 35vg158.yaml new file mode 100644 index 000000000000..00d43ef8a33d --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/fascontek,fs035vg158.= yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/fascontek,fs035vg158.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Fascontek FS035VG158 3.5" (640x480 pixels) 24-bit IPS LCD panel + +maintainers: + - John Watts + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: fascontek,fs035vg158 + + backlight: true + port: true + power-supply: true + reg: true + reset-gpios: true + + spi-3wire: true + +required: + - compatible + - power-supply + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + panel@0 { + compatible =3D "fascontek,fs035vg158"; + reg =3D <0>; + + spi-3wire; + spi-max-frequency =3D <3125000>; + + reset-gpios =3D <&gpe 2 GPIO_ACTIVE_LOW>; + + backlight =3D <&backlight>; + power-supply =3D <&vcc>; + + port { + panel_input: endpoint { + remote-endpoint =3D <&panel_output>; + }; + }; + }; + }; --=20 2.42.0