From nobody Fri Sep 20 14:32:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF3F9EE7FF4 for ; Mon, 11 Sep 2023 07:43:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234789AbjIKHnU (ORCPT ); Mon, 11 Sep 2023 03:43:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234589AbjIKHnC (ORCPT ); Mon, 11 Sep 2023 03:43:02 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2CA0CDE; Mon, 11 Sep 2023 00:42:54 -0700 (PDT) X-UUID: cd07e35e507611ee8051498923ad61e6-20230911 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=XBB2/I17G8CRZPsxs6oYwgV1jgbOqMXm8SNk9ZoUuSU=; b=fbJDdfK0eKWEd1p4/Ite8iuG9GFHJgezXYL5gwjt3aq8aLuai6ZPpEFmIJXBe+VWNr/7Nom96zp02SzX+4eweSmp0HKb+UQQr/w+oXdJa/W0+em3Phg/ipPU36fnSYWA/pr2SgdTGkkM/fW7fHc3vRbP3JHeMF9GXIsQTquRiqM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:b10de687-bd65-4f03-bd70-639ba24e1504,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:18a7e1c2-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: cd07e35e507611ee8051498923ad61e6-20230911 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1084964828; Mon, 11 Sep 2023 15:42:47 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.194) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 15:42:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 15:42:46 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , "CK Hu" , Krzysztof Kozlowski , Matthias Brugger , Rob Herring CC: Conor Dooley , David Airlie , Daniel Vetter , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Philipp Zabel , , , , , , , Singo Chang , "Nancy . Lin" , "Jason-JH . Lin" , Hsiao Chien Sung Subject: [RESEND PATCH v6 14/20] drm/mediatek: Add component ID to component match structure Date: Mon, 11 Sep 2023 15:42:27 +0800 Message-ID: <20230911074233.31556-15-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911074233.31556-1-shawn.sung@mediatek.com> References: <20230911074233.31556-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--13.105300-8.000000 X-TMASE-MatchedRID: XAa2d/45j8Twi+JtrEQDF72xWbKjBfWPT5++FIORChDJYIv7y0tu9rsI asnPqvyQZClGcL9tHydiFleaZxjZFswdQieqpnTaFYJUGv4DL3zljSRvSGpq3PYST2HmKKfiq/q blcNAsytdB8vqCqzk5B3l7vlEbA5tKHAKadh0NOXil2r2x2Pwta6JG5H2YJq6drZkQLRZOVeqMr VzD+KeE0gj9ylhvtMeDFdIIllfLhKR9GF2J2xqMxRFJJyf5BJe3QfwsVk0UbtuRXh7bFKB7hjDK RqZaja93fBG+SXJ9qIw8PaZeYFkp+AmIjvJmTuOSwwcGKLTYEc= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--13.105300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: E1366D2D8309958CFE886E667758AE3F0CD2393485BA6CC162A7F04670697F042000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add component ID to component match structure so we can configure them with a for-loop. The main reason we do such code refactoring is that there is a new hardware component called "Padding" since MT8188, while MT8195 doesn't have this module, we can't use the original logic to manage the components. While MT8195 does not define Padding in the device tree, the corresponding components will be NULL and being skipped by the functions. Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 69 ++++++++----------- 1 file changed, 30 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 72758e41b1e6..8a52d1301e04 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -52,6 +52,7 @@ enum mtk_ovl_adaptor_comp_id { struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; + enum mtk_ddp_comp_id comp_id; int alias_id; }; @@ -68,19 +69,19 @@ static const char * const private_comp_stem[OVL_ADAPTOR= _TYPE_NUM] =3D { }; static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { - [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, 0 }, - [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 }, - [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, 1 }, - [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, 2 }, - [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, 3 }, - [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, 4 }, + [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MI= XER, 0 }, + [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA0, 0 }, + [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA1, 1 }, + [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA2, 2 }, + [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA3, 3 }, + [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA4, 4 }, + [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA5, 5 }, + [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA6, 6 }, + [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA7, 7 }, + [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, = 1 }, + [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2 }, + [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3 }, + [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4 }, }; void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -314,36 +315,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device = *dev) void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex) { - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4); + int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_add_comp(mutex, comp_matches[i].comp_id); + } } void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mut= ex) { - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4); + int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id); + } } void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev,= unsigned int next) -- 2.18.0