From nobody Thu Dec 18 08:13:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31EE1EE801F for ; Mon, 11 Sep 2023 07:13:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233788AbjIKHNa (ORCPT ); Mon, 11 Sep 2023 03:13:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233656AbjIKHN2 (ORCPT ); Mon, 11 Sep 2023 03:13:28 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78F9FCEB; Mon, 11 Sep 2023 00:13:09 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 38B7D0SC016066; Mon, 11 Sep 2023 02:13:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1694416380; bh=VJXrid2kPeeupJMKwSjbH7n+scpImlf2w0s3YRl2uVQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=S0DnhAHu/JVJtJbJhLKciGT0Gex0qyWv/QJLhGeUgYDYGf5c7/0iOE0/GQQfVLMFY LX2TtEb9Hc0sWlnEtopi4IrasldhZIcequUdKHCIFxhWR1nyWpAZidfGLU40sAJrgw DAr0YBx3m+VJ3bIz+cDQ/ec0k1VdWxjHq/v8AFVU= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 38B7D0en021582 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Sep 2023 02:13:00 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 11 Sep 2023 02:12:59 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 11 Sep 2023 02:12:59 -0500 Received: from lelv0854.itg.ti.com (lelv0854.itg.ti.com [10.181.64.140]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 38B7CxuQ025004; Mon, 11 Sep 2023 02:12:59 -0500 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.199]) by lelv0854.itg.ti.com (8.14.7/8.14.7) with ESMTP id 38B7CwlC013899; Mon, 11 Sep 2023 02:12:59 -0500 From: MD Danish Anwar To: Vignesh Raghavendra , Nishanth Menon CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , , , , , , Subject: [PATCH 1/3] arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes Date: Mon, 11 Sep 2023 12:42:43 +0530 Message-ID: <20230911071245.2173520-2-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230911071245.2173520-1-danishanwar@ti.com> References: <20230911071245.2173520-1-danishanwar@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ICSSG IP on AM65x SoCs have two Industrial Ethernet Peripherals (IEPs) to manage/generate Industrial Ethernet functions such as time stamping. Each IEP sub-module is sourced from an internal clock mux that can be sourced from either of the IP instance's ICSSG_IEP_GCLK or ICSSG_ICLK. Add the IEP nodes for all the ICSSG instances. Signed-off-by: MD Danish Anwar --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index bc460033a37a..fdb042d04ad9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -1151,6 +1151,18 @@ icssg0_iepclk_mux: iepclk-mux@30 { }; }; =20 + icssg0_iep0: iep@2e000 { + compatible =3D "ti,am654-icss-iep"; + reg =3D <0x2e000 0x1000>; + clocks =3D <&icssg0_iepclk_mux>; + }; + + icssg0_iep1: iep@2f000 { + compatible =3D "ti,am654-icss-iep"; + reg =3D <0x2f000 0x1000>; + clocks =3D <&icssg0_iepclk_mux>; + }; + icssg0_mii_rt: mii-rt@32000 { compatible =3D "ti,pruss-mii", "syscon"; reg =3D <0x32000 0x100>; @@ -1293,6 +1305,18 @@ icssg1_iepclk_mux: iepclk-mux@30 { }; }; =20 + icssg1_iep0: iep@2e000 { + compatible =3D "ti,am654-icss-iep"; + reg =3D <0x2e000 0x1000>; + clocks =3D <&icssg1_iepclk_mux>; + }; + + icssg1_iep1: iep@2f000 { + compatible =3D "ti,am654-icss-iep"; + reg =3D <0x2f000 0x1000>; + clocks =3D <&icssg1_iepclk_mux>; + }; + icssg1_mii_rt: mii-rt@32000 { compatible =3D "ti,pruss-mii", "syscon"; reg =3D <0x32000 0x100>; @@ -1435,6 +1459,18 @@ icssg2_iepclk_mux: iepclk-mux@30 { }; }; =20 + icssg2_iep0: iep@2e000 { + compatible =3D "ti,am654-icss-iep"; + reg =3D <0x2e000 0x1000>; + clocks =3D <&icssg2_iepclk_mux>; + }; + + icssg2_iep1: iep@2f000 { + compatible =3D "ti,am654-icss-iep"; + reg =3D <0x2f000 0x1000>; + clocks =3D <&icssg2_iepclk_mux>; + }; + icssg2_mii_rt: mii-rt@32000 { compatible =3D "ti,pruss-mii", "syscon"; reg =3D <0x32000 0x100>; --=20 2.34.1 From nobody Thu Dec 18 08:13:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADCC3EE801F for ; Mon, 11 Sep 2023 07:13:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233966AbjIKHNi (ORCPT ); Mon, 11 Sep 2023 03:13:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233656AbjIKHNe (ORCPT ); Mon, 11 Sep 2023 03:13:34 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8DD5CEC; Mon, 11 Sep 2023 00:13:14 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 38B7D67H025075; Mon, 11 Sep 2023 02:13:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1694416386; bh=43vKiqMcLtCG6Og7yqMpFdYKBm37kTJgJ+bO/lPppF0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ng+3Fq5fNUNPV+yGFGuLh43h+fbJV4snKxUxw2VtzINwDaBVYiIKarvOseHgmbD3M 9Hqd5OHhpmjbqwtNtPkC4Z3g8P92XiIjHgGpTDWuE3UtVfthIIxV/y4zL08wORznrC aIvKLPMZkGtgBvLpKcLl5g6GPe7E3G0zE6XES044= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 38B7D6gr045799 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 11 Sep 2023 02:13:06 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 11 Sep 2023 02:13:06 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 11 Sep 2023 02:13:06 -0500 Received: from lelv0854.itg.ti.com (lelv0854.itg.ti.com [10.181.64.140]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 38B7D69Y004705; Mon, 11 Sep 2023 02:13:06 -0500 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.199]) by lelv0854.itg.ti.com (8.14.7/8.14.7) with ESMTP id 38B7D5vv013912; Mon, 11 Sep 2023 02:13:05 -0500 From: MD Danish Anwar To: Vignesh Raghavendra , Nishanth Menon CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , , , , , , Subject: [PATCH 2/3] arm64: dts: ti: am654-base-board: add ICSSG2 Ethernet support Date: Mon, 11 Sep 2023 12:42:44 +0530 Message-ID: <20230911071245.2173520-3-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230911071245.2173520-1-danishanwar@ti.com> References: <20230911071245.2173520-1-danishanwar@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" ICSSG2 provides dual Gigabit Ethernet support. For support SR2.0 ICSSG Ethernet firmware: - provide different firmware blobs and use TX_PRU. - IEP0 is used as PTP Hardware Clock and can only be used for one port. - TX timestamp notification comes via INTC interrupt. Signed-off-by: MD Danish Anwar --- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index f5c26e9fba98..5cf9546ff9f7 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -25,6 +25,8 @@ aliases { ethernet0 =3D &cpsw_port1; mmc0 =3D &sdhci0; mmc1 =3D &sdhci1; + ethernet1 =3D &icssg2_emac0; + ethernet2 =3D &icssg2_emac1; }; =20 chosen { @@ -144,6 +146,72 @@ vtt_supply: regulator-3 { vin-supply =3D <&vcc3v3_io>; gpio =3D <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>; }; + + /* Dual Ethernet application node on PRU-ICSSG2 */ + icssg2_eth: icssg2-eth { + compatible =3D "ti,am654-icssg-prueth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg2_rgmii_pins_default>; + sram =3D <&msmc_ram>; + ti,prus =3D <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>, + <&pru2_1>, <&rtu2_1>, <&tx_pru2_1>; + firmware-name =3D "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel =3D <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt =3D <&icssg2_mii_g_rt>; + ti,mii-rt =3D <&icssg2_mii_rt>; + ti,iep =3D <&icssg2_iep0>, <&icssg2_iep1>; + + interrupt-parent =3D <&icssg2_intc>; + interrupts =3D <24 0 2>, <25 1 3>; + interrupt-names =3D "tx_ts0", "tx_ts1"; + + dmas =3D <&main_udmap 0xc300>, /* egress slice 0 */ + <&main_udmap 0xc301>, /* egress slice 0 */ + <&main_udmap 0xc302>, /* egress slice 0 */ + <&main_udmap 0xc303>, /* egress slice 0 */ + <&main_udmap 0xc304>, /* egress slice 1 */ + <&main_udmap 0xc305>, /* egress slice 1 */ + <&main_udmap 0xc306>, /* egress slice 1 */ + <&main_udmap 0xc307>, /* egress slice 1 */ + <&main_udmap 0x4300>, /* ingress slice 0 */ + <&main_udmap 0x4301>; /* ingress slice 1 */ + + dma-names =3D "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + icssg2_emac0: port@0 { + reg =3D <0>; + phy-handle =3D <&icssg2_phy0>; + phy-mode =3D "rgmii-id"; + ti,syscon-rgmii-delay =3D <&scm_conf 0x4120>; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + icssg2_emac1: port@1 { + reg =3D <1>; + phy-handle =3D <&icssg2_phy1>; + phy-mode =3D "rgmii-id"; + ti,syscon-rgmii-delay =3D <&scm_conf 0x4124>; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + }; + }; }; =20 &wkup_pmx0 { @@ -300,6 +368,43 @@ usb1_pins_default: usb1-default-pins { AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ >; }; + + icssg2_mdio_pins_default: icssg2-mdio-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_M= DIO */ + AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_= MDC */ + >; + }; + + icssg2_rgmii_pins_default: icssg2-rgmii-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_= RD0 */ + AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_= RD1 */ + AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_= RD2 */ + AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_= RD3 */ + AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2= _TD0 */ + AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2= _TD1 */ + AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII= 2_TD2 */ + AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII= 2_TD3 */ + AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2= _TXC */ + AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2= _TX_CTL */ + AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_= RXC */ + AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_= RX_CTL */ + + AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_= RD0 */ + AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_= RD1 */ + AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_= RD2 */ + AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_= RD3 */ + AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1= _TD0 */ + AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1= _TD1 */ + AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII= 1_TD2 */ + AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII= 1_TD3 */ + AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1= _TXC */ + AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1= _TX_CTL */ + AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_= RXC */ + AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_= RX_CTL */ + >; + }; }; =20 &main_pmx1 { @@ -621,3 +726,21 @@ &cpsw_port1 { &dss { status =3D "disabled"; }; + +&icssg2_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg2_mdio_pins_default>; + + icssg2_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + }; + + icssg2_phy1: ethernet-phy@3 { + reg =3D <3>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + }; +}; --=20 2.34.1 From nobody Thu Dec 18 08:13:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83ED5EE801F for ; Mon, 11 Sep 2023 07:13:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234052AbjIKHNp (ORCPT ); Mon, 11 Sep 2023 03:13:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233656AbjIKHNn (ORCPT ); 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Mon, 11 Sep 2023 02:13:12 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 11 Sep 2023 02:13:12 -0500 Received: from lelv0854.itg.ti.com (lelv0854.itg.ti.com [10.181.64.140]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 38B7DCUw004780; Mon, 11 Sep 2023 02:13:12 -0500 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.199]) by lelv0854.itg.ti.com (8.14.7/8.14.7) with ESMTP id 38B7DC0q013929; Mon, 11 Sep 2023 02:13:12 -0500 From: MD Danish Anwar To: Vignesh Raghavendra , Nishanth Menon CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , , , , , , Subject: [PATCH 3/3] arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports Date: Mon, 11 Sep 2023 12:42:45 +0530 Message-ID: <20230911071245.2173520-4-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230911071245.2173520-1-danishanwar@ti.com> References: <20230911071245.2173520-1-danishanwar@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The IDK application board has 4 Gigabit Ethernet ports. This patch adds support for the 4 Gigabit Ethernet ports which are provided by ICSSG0 and ICSSG1. The IEP0 SYNC_OUT0 pins are used for PPS out on the IDK card. Signed-off-by: MD Danish Anwar --- arch/arm64/boot/dts/ti/Makefile | 2 +- arch/arm64/boot/dts/ti/k3-am654-idk.dtso | 296 +++++++++++++++++++++++ 2 files changed, 297 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am654-idk.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index e7b8e2e7f083..1e8d2ac2d0fe 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -42,7 +42,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-tqma64xxl-mbax4xxl-sd= card.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-tqma64xxl-mbax4xxl-wlan.dtb =20 # Boards with AM65x SoC -k3-am654-gp-evm-dtbs :=3D k3-am654-base-board.dtb k3-am654-base-board-rock= tech-rk101-panel.dtbo +k3-am654-gp-evm-dtbs :=3D k3-am654-base-board.dtb k3-am654-base-board-rock= tech-rk101-panel.dtbo k3-am654-idk.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am6528-iot2050-basic.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am6528-iot2050-basic-pg2.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am6548-iot2050-advanced.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am654-idk.dtso b/arch/arm64/boot/dts= /ti/k3-am654-idk.dtso new file mode 100644 index 000000000000..7aa10827ed65 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for IDK application board on AM654 EVM + * + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet3 =3D "/icssg0-eth/ethernet-ports/port@0"; + ethernet4 =3D "/icssg0-eth/ethernet-ports/port@1"; + ethernet5 =3D "/icssg1-eth/ethernet-ports/port@0"; + ethernet6 =3D "/icssg1-eth/ethernet-ports/port@1"; + }; + + /* Dual Ethernet application node on PRU-ICSSG0 */ + icssg0_eth: icssg0-eth { + compatible =3D "ti,am654-icssg-prueth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg0_rgmii_pins_default>; + sram =3D <&msmc_ram>; + ti,prus =3D <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&= tx_pru0_1>; + firmware-name =3D "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel =3D <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt =3D <&icssg0_mii_g_rt>; + ti,mii-rt =3D <&icssg0_mii_rt>; + ti,iep =3D <&icssg0_iep0>, <&icssg0_iep1>; + + interrupt-parent =3D <&icssg0_intc>; + interrupts =3D <24 0 2>, <25 1 3>; + interrupt-names =3D "tx_ts0", "tx_ts1"; + + dmas =3D <&main_udmap 0xc100>, /* egress slice 0 */ + <&main_udmap 0xc101>, /* egress slice 0 */ + <&main_udmap 0xc102>, /* egress slice 0 */ + <&main_udmap 0xc103>, /* egress slice 0 */ + <&main_udmap 0xc104>, /* egress slice 1 */ + <&main_udmap 0xc105>, /* egress slice 1 */ + <&main_udmap 0xc106>, /* egress slice 1 */ + <&main_udmap 0xc107>, /* egress slice 1 */ + + <&main_udmap 0x4100>, /* ingress slice 0 */ + <&main_udmap 0x4101>, /* ingress slice 1 */ + <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */ + <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */ + dma-names =3D "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + icssg0_emac0: port@0 { + reg =3D <0>; + phy-handle =3D <&icssg0_phy0>; + phy-mode =3D "rgmii-id"; + ti,syscon-rgmii-delay =3D <&scm_conf 0x4100>; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + icssg0_emac1: port@1 { + reg =3D <1>; + phy-handle =3D <&icssg0_phy1>; + phy-mode =3D "rgmii-id"; + ti,syscon-rgmii-delay =3D <&scm_conf 0x4104>; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + }; + }; + + /* Dual Ethernet application node on PRU-ICSSG1 */ + icssg1_eth: icssg1-eth { + compatible =3D "ti,am654-icssg-prueth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg1_rgmii_pins_default>; + sram =3D <&msmc_ram>; + ti,prus =3D <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&= tx_pru1_1>; + firmware-name =3D "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel =3D <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt =3D <&icssg1_mii_g_rt>; + ti,mii-rt =3D <&icssg1_mii_rt>; + ti,iep =3D <&icssg1_iep0>, <&icssg1_iep1>; + + interrupt-parent =3D <&icssg1_intc>; + interrupts =3D <24 0 2>, <25 1 3>; + interrupt-names =3D "tx_ts0", "tx_ts1"; + + dmas =3D <&main_udmap 0xc200>, /* egress slice 0 */ + <&main_udmap 0xc201>, /* egress slice 0 */ + <&main_udmap 0xc202>, /* egress slice 0 */ + <&main_udmap 0xc203>, /* egress slice 0 */ + <&main_udmap 0xc204>, /* egress slice 1 */ + <&main_udmap 0xc205>, /* egress slice 1 */ + <&main_udmap 0xc206>, /* egress slice 1 */ + <&main_udmap 0xc207>, /* egress slice 1 */ + + <&main_udmap 0x4200>, /* ingress slice 0 */ + <&main_udmap 0x4201>, /* ingress slice 1 */ + <&main_udmap 0x4202>, /* mgmnt rsp slice 0 */ + <&main_udmap 0x4203>; /* mgmnt rsp slice 1 */ + dma-names =3D "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + icssg1_emac0: port@0 { + reg =3D <0>; + phy-handle =3D <&icssg1_phy0>; + phy-mode =3D "rgmii-id"; + ti,syscon-rgmii-delay =3D <&scm_conf 0x4110>; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + icssg1_emac1: port@1 { + reg =3D <1>; + phy-handle =3D <&icssg1_phy1>; + phy-mode =3D "rgmii-id"; + ti,syscon-rgmii-delay =3D <&scm_conf 0x4114>; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + }; + }; +}; + +&main_pmx0 { + + icssg0_mdio_pins_default: icssg0-mdio-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */ + AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */ + >; + }; + + icssg0_rgmii_pins_default: icssg0-rgmii-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_= RD0 */ + AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_= RD1 */ + AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_= RD2 */ + AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_= RD3 */ + AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII= 2_TD0 */ + AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII= 2_TD1 */ + AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII= 2_TD2 */ + AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII= 2_TD3 */ + AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2= _TXC */ + AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII= 2_TX_CTL */ + AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_= RXC */ + AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_= RX_CTL */ + + AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_R= D0 */ + AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_R= D1 */ + AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_R= D2 */ + AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_= RD3 */ + AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII= 1_TD0 */ + AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII= 1_TD1 */ + AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII= 1_TD2 */ + AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII= 1_TD3 */ + AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1= _TXC */ + AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII= 1_TX_CTL */ + AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_R= XC */ + AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_R= X_CTL */ + >; + }; + + icssg0_iep0_pins_default: icssg0-iep0-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_ED= C_SYNC_OUT0 */ + >; + }; + + icssg1_mdio_pins_default: icssg1-mdio-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18) PRG1_MDIO0_MDIO */ + AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */ + >; + }; + + icssg1_rgmii_pins_default: icssg1-rgmii-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24) PRG1_PRU1_GPO0.PRG1_RGMII2_= RD0 */ + AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23) PRG1_PRU1_GPO1.PRG1_RGMII2_= RD1 */ + AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21) PRG1_PRU1_GPO2.PRG1_RGMII2_= RD2 */ + AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22) PRG1_PRU1_GPO3.PRG1_RGMII2_= RD3 */ + AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20) PRG1_PRU1_GPO12.PRG1_RGMII= 2_TD0 */ + AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19) PRG1_PRU1_GPO13.PRG1_RGMII= 2_TD1 */ + AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19) PRG1_PRU1_GPO14.PRG1_RGMII= 2_TD2 */ + AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19) PRG1_PRU1_GPO15.PRG1_RGMII= 2_TD3 */ + AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19) PRG1_PRU1_GPO16.PRG1_RGMII2= _TXC */ + AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20) PRG1_PRU1_GPO11.PRG1_RGMII= 2_TX_CTL */ + AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22) PRG1_PRU1_GPO6.PRG1_RGMII2_= RXC */ + AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21) PRG1_PRU1_GPO4.PRG1_RGMII2_= RX_CTL */ + + AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22) PRG1_PRU0_GPO0.PRG1_RGMII1_= RD0 */ + AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24) PRG1_PRU0_GPO1.PRG1_RGMII1_= RD1 */ + AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23) PRG1_PRU0_GPO2.PRG1_RGMII1_= RD2 */ + AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21) PRG1_PRU0_GPO3.PRG1_RGMII1_= RD3 */ + AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_PRU0_GPO12.PRG1_RGMII= 1_TD0 */ + AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_PRU0_GPO13.PRG1_RGMII= 1_TD1 */ + AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_PRU0_GPO14.PRG1_RGMII= 1_TD2 */ + AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_PRU0_GPO15.PRG1_RGMII= 1_TD3 */ + AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20) PRG1_PRU0_GPO16.PRG1_RGMII1= _TXC */ + AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_PRU0_GPO11.PRG1_RGMII= 1_TX_CTL */ + AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22) PRG1_PRU0_GPO6.PRG1_RGMII1_= RXC */ + AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23) PRG1_PRU0_GPO4.PRG1_RGMII1_= RX_CTL */ + >; + }; + + icssg1_iep0_pins_default: icssg1-iep0-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_E= DC_SYNC_OUT0 */ + >; + }; +}; + +&icssg0_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg0_mdio_pins_default>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + icssg0_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + }; + + icssg0_phy1: ethernet-phy@3 { + reg =3D <3>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + }; +}; + +&icssg0_iep0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg0_iep0_pins_default>; +}; + +&icssg1_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg1_mdio_pins_default>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + icssg1_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + }; + + icssg1_phy1: ethernet-phy@3 { + reg =3D <3>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + }; +}; + +&icssg1_iep0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg1_iep0_pins_default>; +}; --=20 2.34.1