From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08EF4EEB57D for ; Mon, 11 Sep 2023 03:17:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232941AbjIKDQ7 (ORCPT ); Sun, 10 Sep 2023 23:16:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230513AbjIKDQw (ORCPT ); Sun, 10 Sep 2023 23:16:52 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 591BD10E for ; Sun, 10 Sep 2023 20:16:46 -0700 (PDT) X-UUID: a0130dd0505111ee8051498923ad61e6-20230911 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Cti+2251drnoe42CDipHrRl7YxLiSGYiQTChaRDnbyg=; b=tmnkBpuymux0z0GQyYy1nSe2Ds1L8X0+Nqm22KD2FyEk2JHluLo9SEbza4G/0/RsKS4Df8JuVW+d7yQjBMHCPHcBSoB8xr2CX7bna5+UDLrjU9c1Yk5oNdBlzXp53kd0xxTQxD1PlwNg/JPNQz1r/Ktzx0JFjzmTw6uni39hT9M=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:a69f9070-58d9-4b07-b8c1-90234a519360,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:0ad78a4,CLOUDID:81f9adbe-14cc-44ca-b657-2d2783296e72,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: a0130dd0505111ee8051498923ad61e6-20230911 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1462342876; Mon, 11 Sep 2023 11:16:40 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 11:16:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:38 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 01/20] dt-bindings: display: mediatek: ethdr: Add compatible for MT8188 Date: Mon, 11 Sep 2023 11:16:11 +0800 Message-ID: <20230911031630.12613-2-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--0.514200-8.000000 X-TMASE-MatchedRID: tiRXYRqWr+sDh1tb/sWFHED6z8N1m1ALqm/9CTn1HV3fUZT83lbkED1/ uZDvFhzjSBg3ErWyNT+HEeMTfR0Cex8TzIzimOwPC24oEZ6SpSmb4wHqRpnaDtr8/EBRy8/L1iW 0V4glpnqrAcTulUhwSnSCez4XD+H2STDwD1yLJpU4sF+9oVt7bq7jtzKgXAd7unnGE+ySwAivii 8/BEfmyUma3zYT97IFAYfQIAUhBayZvmCbKVb49sZL6x5U/HridGByp+zdaDg= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.514200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 8B2E88A0D87F0DBFC1743806BA2E5C0C3FDEC8379E7FF3A97AA3E2CDB59633B62000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible name for MediaTek MT8188 ETHDR. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Hsiao Chien Sung --- .../bindings/display/mediatek/mediatek,ethdr.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,et= hdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethd= r.yaml index 801fa66ae615..677882348ede 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml @@ -23,7 +23,11 @@ description: =20 properties: compatible: - const: mediatek,mt8195-disp-ethdr + oneOf: + - const: mediatek,mt8195-disp-ethdr + - items: + - const: mediatek,mt8188-disp-ethdr + - const: mediatek,mt8195-disp-ethdr =20 reg: maxItems: 7 --=20 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E020EE49A4 for ; Mon, 11 Sep 2023 03:17:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233417AbjIKDRT (ORCPT ); Sun, 10 Sep 2023 23:17:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229441AbjIKDQy (ORCPT ); Sun, 10 Sep 2023 23:16:54 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74FDD10E for ; Sun, 10 Sep 2023 20:16:49 -0700 (PDT) X-UUID: 9ff79140505111ee8051498923ad61e6-20230911 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FV4odRXnNTKOQBhGhBdPOqDzPoH/F1kBWWK+yVCknnM=; b=ccJR34vsad2lZUvAxOtxEM8S1b/vuIFW5dpYkeLJEOXCN/UjDnSzFvddlXMSoMHW4JRnxKXbW0gzLmuLoyauIlhg/Fo4HLskL1AO8xAsNfoUJNgUuqwSO+PzylzRtXv2LYxVIhG5YyLTAvfffnRfSrQJypaoRTx6zeOxypPwVwo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:f0864ed8-8489-4c1f-8de0-56ed4a9a81ac,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:82f9adbe-14cc-44ca-b657-2d2783296e72,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 9ff79140505111ee8051498923ad61e6-20230911 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1584406544; Mon, 11 Sep 2023 11:16:40 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 11:16:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:38 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 02/20] dt-bindings: display: mediatek: mdp-rdma: Add compatible for MT8188 Date: Mon, 11 Sep 2023 11:16:12 +0800 Message-ID: <20230911031630.12613-3-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible name for MediaTek MT8188 MDP-RDMA. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Hsiao Chien Sung --- .../bindings/display/mediatek/mediatek,mdp-rdma.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,md= p-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,m= dp-rdma.yaml index dd12e2ff685c..7570a0684967 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.= yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.= yaml @@ -21,7 +21,11 @@ description: =20 properties: compatible: - const: mediatek,mt8195-vdo1-rdma + oneOf: + - const: mediatek,mt8195-vdo1-rdma + - items: + - const: mediatek,mt8188-vdo1-rdma + - const: mediatek,mt8195-vdo1-rdma =20 reg: maxItems: 1 --=20 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AE5DEE49A4 for ; Mon, 11 Sep 2023 03:17:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232675AbjIKDRs (ORCPT ); Sun, 10 Sep 2023 23:17:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232549AbjIKDQy (ORCPT ); Sun, 10 Sep 2023 23:16:54 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 490BC115 for ; Sun, 10 Sep 2023 20:16:50 -0700 (PDT) X-UUID: 9ff93edc505111ee8051498923ad61e6-20230911 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Bep00Fy8PWOm2Iehibgg/4qH9oRW1bllPKxFoTJBpC0=; b=ZWSI8pGYTaSCUeVWnSCRvKNwA0atEccXD1bQhrL2Om3mKL7+7AMrfuAAXiNC+o1BO3W34+SwiC26J2V7Sg8KYW/WytoDrCyNxpall+0b9xyoCT27M3JCXoH6zvlWYoJAeknk6y91bX7FDGCc19n/uWLjFJuQPPKoH7D3eN+rtF0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:ca8f75e3-bde3-4e37-b975-1ebd4322e4cc,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:83f9adbe-14cc-44ca-b657-2d2783296e72,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 9ff93edc505111ee8051498923ad61e6-20230911 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1613873915; Mon, 11 Sep 2023 11:16:40 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 11:16:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:38 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 03/20] dt-bindings: display: mediatek: merge: Add compatible for MT8188 Date: Mon, 11 Sep 2023 11:16:13 +0800 Message-ID: <20230911031630.12613-4-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible name for MediaTek MT8188 MERGE. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Hsiao Chien Sung --- .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,me= rge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merg= e.yaml index eead5cb8636e..5c678695162e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -27,6 +27,9 @@ properties: - items: - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge + - items: + - const: mediatek,mt8188-disp-merge + - const: mediatek,mt8195-disp-merge =20 reg: maxItems: 1 --=20 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3888EEEB581 for ; Mon, 11 Sep 2023 03:17:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233577AbjIKDRo (ORCPT ); Sun, 10 Sep 2023 23:17:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232796AbjIKDQ4 (ORCPT ); Sun, 10 Sep 2023 23:16:56 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86A8910E for ; Sun, 10 Sep 2023 20:16:51 -0700 (PDT) X-UUID: a1a2d720505111ee8051498923ad61e6-20230911 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=JtH8H/mH3Uz7XL+BMa9kU6gPh56dxzN2XLCuY3hjHsw=; b=UiO6sfKF81bbDv0K5d1R/YFlok+xsKK4DefN2KnJxgdcvFlI6VYk/RHdeLkk72tyT/434rPTjLQCtFofEqG1KHTHaDpTTqV95NgVeFgcr9GVzWdsXQYaY5o4ay/DYnGO1fLRKkHzX9/zN22N01otbwm8GPyBBIbf1EdTmUCPt6Y=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:010a2bd7-15de-43c0-954a-a02e2c1a4ca2,IP:0,U RL:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:20 X-CID-META: VersionHash:0ad78a4,CLOUDID:63a7dec2-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: a1a2d720505111ee8051498923ad61e6-20230911 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1326322862; Mon, 11 Sep 2023 11:16:42 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 11:16:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:39 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 04/20] dt-bindings: display: mediatek: padding: Add MT8188 Date: Mon, 11 Sep 2023 11:16:14 +0800 Message-ID: <20230911031630.12613-5-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--8.027100-8.000000 X-TMASE-MatchedRID: 9nkzMtsPLI7yZ92BnYqk5lz+axQLnAVB6SXuwUgGH0gIgSDinsA6bIpb wG9fIuITLSHDQi/tZU9ZyJKwWJFJUwAwGIAo3Shb71Wx2uUbPLcT0Sn1/3AIbWHZ+cd7VyKXTo+ d5kYVw/ElbBPuTv/lL9eHLWzVm2BdhPc4FTJN6V5LxLYX2WS87+AAYRasBjMekR+/pTNS9t0o0E qA13zQc0cN36UB4MN7MHwFGlhAi2EZjarFLqLUbBuZoNKc6pl+zKnr9zj6h3Hz9QBty8t029xBt 1UDX817nXOXTNRLXkt5pD5YlcDpcqtL0wBaA/G+DB+ErBr0bANimi8LvNfmr87EPIkVcg+OWaGV MLZ5ERLi8zVgXoAltlPcOF1Vw1gmC24oEZ6SpSlsZUSYh+N/e3EQ32xyf6OWA2HUg8E47c0SeDq BtFZYe4Lz5U2zu5EXXXPflUac0Yg= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--8.027100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 5E7F621B658F2080561D6D01FAE0C98F6A3838974500ED543C70BB095789C21E2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Padding is a new hardware module on MediaTek MT8188, add dt-bindings for it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hsiao Chien Sung --- .../display/mediatek/mediatek,padding.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,padding.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pa= dding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pa= dding.yaml new file mode 100644 index 000000000000..db24801ebc48 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.y= aml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Padding + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: + Padding provides ability to add pixels to width and height of a layer wi= th + specified colors. Due to hardware design, Mixer in VDOSYS1 requires + width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is ena= bled, + we need Padding to deal with odd width. + Please notice that even if the Padding is in bypass mode, settings in + register must be cleared to 0, or undefined behaviors could happen. + +properties: + compatible: + const: mediatek,mt8188-padding + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: RDMA Clock + + mediatek,gce-client-reg: + description: + GCE (Global Command Engine) is a multi-core micro processor that hel= ps + its clients to execute commands without interrupting CPU. This prope= rty + describes GCE client's information that is composed by 4 fields. + 1. Phandle of the GCE (there may be several GCE processors) + 2. Sub-system ID defined in the dt-binding like a user ID + (Please refer to include/dt-bindings/gce/-gce.h) + 3. Offset from base address of the subsys you are at + 4. Size of the register the client needs + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: Phandle of the GCE + - description: Subsys ID defined in the dt-binding + - description: Offset from base address of the subsys + - description: Size of register + maxItems: 1 + +required: + - compatible + - reg + - power-domains + - clocks + - mediatek,gce-client-reg + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + padding0: padding@1c11d000 { + compatible =3D "mediatek,mt8188-padding"; + reg =3D <0 0x1c11d000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0xd000 0x10= 00>; + }; + }; --=20 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF399EE49A4 for ; Mon, 11 Sep 2023 03:17:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232460AbjIKDQx (ORCPT ); Sun, 10 Sep 2023 23:16:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229441AbjIKDQw (ORCPT ); Sun, 10 Sep 2023 23:16:52 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8610210F for ; Sun, 10 Sep 2023 20:16:46 -0700 (PDT) X-UUID: a08484ba505111eea33bb35ae8d461a2-20230911 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Dum0ZzdIzX75g8CGTmR32v++7pJ8YrqnJQNjcoVOBkE=; b=T1iSrPh1T9twA/ccw76X1PCAwUbFi1mdaWy5PeoaZWgLHhTVbQPt5zz3BwThaNxuMl/iu9AB+qxvPoeHbh6thxP5KWHxl2O+q7rm6UptvQz45xVf4R5e07m5Oh8pJvYcE37bjBXYuMUu4mz9X1xCeeEJVCP63B+QUpZQSn372Ro=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:ba129e66-0bf9-4693-8560-39c513f08bde,IP:0,U RL:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:0ad78a4,CLOUDID:0922c813-4929-4845-9571-38c601e9c3c9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,D KR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: a08484ba505111eea33bb35ae8d461a2-20230911 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 212799808; Mon, 11 Sep 2023 11:16:41 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 11:16:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:39 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 05/20] dt-bindings: arm: mediatek: Add compatible for MT8188 Date: Mon, 11 Sep 2023 11:16:15 +0800 Message-ID: <20230911031630.12613-6-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.601500-8.000000 X-TMASE-MatchedRID: jhJi18RLqAIDh1tb/sWFHED6z8N1m1ALqm/9CTn1HV3fUZT83lbkEA0F DzFL1GEo4vM1YF6AJbbCCfuIMF6xLSdET58jp62S7UWsD6GWso5QU0K2TvJqIhFMmSX2he18HGC vB9GDrOojPzM73BDrsOmjj90j197PxyH08/2Lzr4S4W+lEBmx76SyLWhqwNOBgITnGkK0NFNRsk XKHhdfKpij9M86UwHhsKHfMTjCprwNQJGvyiKf6Q== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.601500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 36560D98057FDE8641283AABF24B2AF56E0FD901799BEB3F9B5CD88EB162F2CA2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible name for MediaTek MT8188 VDOSYS1. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Hsiao Chien Sung --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.= yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 536f5a5ebd24..642fa2e4736e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8188-vdosys0 + - mediatek,mt8188-vdosys1 - mediatek,mt8192-mmsys - mediatek,mt8195-vdosys1 - mediatek,mt8195-vppsys0 --=20 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D46DDEEB580 for ; Mon, 11 Sep 2023 03:17:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233404AbjIKDRb (ORCPT ); Sun, 10 Sep 2023 23:17:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232555AbjIKDQy (ORCPT ); Sun, 10 Sep 2023 23:16:54 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAA38114 for ; Sun, 10 Sep 2023 20:16:49 -0700 (PDT) X-UUID: a0172ec4505111ee8051498923ad61e6-20230911 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=e3ahd3M0XcppL08N+KpDhIH1BYr1qRQbibyyNReplTw=; b=o6iNGRasa5+u72hwf7ktnynf3mh/pkKFLFNOSUakcw6dAk89zRDitxoXCF8ksWT38VGBf3kHRzPAxBA1+ncWLIN8IXj8xljZBHEE4YTrJtlnxrGjVGGq0ENFl0+5XzUbbPWskJRsC9oApoA8YCZqvEMYWKyNqMzbjH/6M5hQHTk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31,REQID:ef7fae58-caa2-41b3-8648-64cfd3049ba0,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4,CLOUDID:4aa7dec2-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: a0172ec4505111ee8051498923ad61e6-20230911 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2007224458; Mon, 11 Sep 2023 11:16:40 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 11:16:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:39 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 06/20] dt-bindings: reset: mt8188: Add VDOSYS reset control bits Date: Mon, 11 Sep 2023 11:16:16 +0800 Message-ID: <20230911031630.12613-7-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.230700-8.000000 X-TMASE-MatchedRID: tiRXYRqWr+upk9YSiEd5ImNW0DAjL5p+Wot5Z16+u74IgSDinsA6bCzy bVqWyY2NTAa7ihKVJtWAMuqetGVetocnrwAbVlNi3QfwsVk0UbsIoUKaF27lxW/EmO7579ImPdv WDxcnsv62jQK4x7A0yTmv3WIKQz/Ji4gt2mJW428iCqrEag5df9amHb2LHHT+uE6Jn2QVH0KYe5 xoFcRssRdGg+ZY7eN6THB2Q+oKru8MTI34nyF36MJL1aANdU8Knqg/VrSZEiM= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.230700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: EE1B98C348D69B96984F80B884E25F39A483F0824BC4A02DF26A5BD0599ADFEA2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MT8188 VDOSYS0 and VDOSYS1 reset control bits. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Hsiao Chien Sung --- include/dt-bindings/reset/mt8188-resets.h | 75 +++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-binding= s/reset/mt8188-resets.h index ba9a5e9b8899..5a58c54e7d20 100644 --- a/include/dt-bindings/reset/mt8188-resets.h +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -38,4 +38,79 @@ #define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1 #define MT8188_INFRA_RST3_PTP_CTRL_RST 2 =20 +#define MT8188_VDO0_RST_DISP_OVL0 0 +#define MT8188_VDO0_RST_FAKE_ENG0 1 +#define MT8188_VDO0_RST_DISP_CCORR0 2 +#define MT8188_VDO0_RST_DISP_MUTEX0 3 +#define MT8188_VDO0_RST_DISP_GAMMA0 4 +#define MT8188_VDO0_RST_DISP_DITHER0 5 +#define MT8188_VDO0_RST_DISP_WDMA0 6 +#define MT8188_VDO0_RST_DISP_RDMA0 7 +#define MT8188_VDO0_RST_DSI0 8 +#define MT8188_VDO0_RST_DSI1 9 +#define MT8188_VDO0_RST_DSC_WRAP0 10 +#define MT8188_VDO0_RST_VPP_MERGE0 11 +#define MT8188_VDO0_RST_DP_INTF0 12 +#define MT8188_VDO0_RST_DISP_AAL0 13 +#define MT8188_VDO0_RST_INLINEROT0 14 +#define MT8188_VDO0_RST_APB_BUS 15 +#define MT8188_VDO0_RST_DISP_COLOR0 16 +#define MT8188_VDO0_RST_MDP_WROT0 17 +#define MT8188_VDO0_RST_DISP_RSZ0 18 + +#define MT8188_VDO1_RST_SMI_LARB2 0 +#define MT8188_VDO1_RST_SMI_LARB3 1 +#define MT8188_VDO1_RST_GALS 2 +#define MT8188_VDO1_RST_FAKE_ENG0 3 +#define MT8188_VDO1_RST_FAKE_ENG1 4 +#define MT8188_VDO1_RST_MDP_RDMA0 5 +#define MT8188_VDO1_RST_MDP_RDMA1 6 +#define MT8188_VDO1_RST_MDP_RDMA2 7 +#define MT8188_VDO1_RST_MDP_RDMA3 8 +#define MT8188_VDO1_RST_VPP_MERGE0 9 +#define MT8188_VDO1_RST_VPP_MERGE1 10 +#define MT8188_VDO1_RST_VPP_MERGE2 11 +#define MT8188_VDO1_RST_VPP_MERGE3 12 +#define MT8188_VDO1_RST_VPP_MERGE4 13 +#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14 +#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15 +#define MT8188_VDO1_RST_DISP_MUTEX 16 +#define MT8188_VDO1_RST_MDP_RDMA4 17 +#define MT8188_VDO1_RST_MDP_RDMA5 18 +#define MT8188_VDO1_RST_MDP_RDMA6 19 +#define MT8188_VDO1_RST_MDP_RDMA7 20 +#define MT8188_VDO1_RST_DP_INTF1_MMCK 21 +#define MT8188_VDO1_RST_DPI0_MM_CK 22 +#define MT8188_VDO1_RST_DPI1_MM_CK 23 +#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24 +#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25 +#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26 +#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27 +#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28 +#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29 +#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30 +#define MT8188_VDO1_RST_PADDING0 31 +#define MT8188_VDO1_RST_PADDING1 32 +#define MT8188_VDO1_RST_PADDING2 33 +#define MT8188_VDO1_RST_PADDING3 34 +#define MT8188_VDO1_RST_PADDING4 35 +#define MT8188_VDO1_RST_PADDING5 36 +#define MT8188_VDO1_RST_PADDING6 37 +#define MT8188_VDO1_RST_PADDING7 38 +#define MT8188_VDO1_RST_DISP_RSZ0 39 +#define MT8188_VDO1_RST_DISP_RSZ1 40 +#define MT8188_VDO1_RST_DISP_RSZ2 41 +#define MT8188_VDO1_RST_DISP_RSZ3 42 +#define MT8188_VDO1_RST_HDR_VDO_FE0 43 +#define MT8188_VDO1_RST_HDR_GFX_FE0 44 +#define MT8188_VDO1_RST_HDR_VDO_BE 45 +#define MT8188_VDO1_RST_HDR_VDO_FE1 46 +#define MT8188_VDO1_RST_HDR_GFX_FE1 47 +#define MT8188_VDO1_RST_DISP_MIXER 48 +#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49 +#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50 +#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51 +#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52 +#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ --=20 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0409AC71153 for ; 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Mon, 11 Sep 2023 11:16:39 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 07/20] soc: mediatek: Support MT8188 VDOSYS1 in mtk-mmsys Date: Mon, 11 Sep 2023 11:16:17 +0800 Message-ID: <20230911031630.12613-8-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Add register definitions for MT8188 - Add VDOSYS1 routing table - Update MUTEX definitions accordingly - Set VSYNC length from 0x40 (default) to 1 since ETHDR is bypassed Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mt8188-mmsys.h | 126 ++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 9 ++ drivers/soc/mediatek/mtk-mmsys.h | 29 +++++++ drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++ 4 files changed, 199 insertions(+) diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8= 188-mmsys.h index 448cc3761b43..a9490c3c4256 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -67,6 +67,56 @@ #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) =20 +#define MT8188_VDO1_HDR_TOP_CFG 0xd00 +#define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30 +#define MT8188_VDO1_MIXER_IN1_PAD 0xd40 +#define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c +#define MT8188_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 +#define MT8188_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 +#define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 +#define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 +#define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 +#define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 +#define MT8188_VDO1_DISP_DPI1_SEL_IN 0xf10 +#define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 +#define MT8188_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 +#define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 +#define MT8188_VDO1_MERGE4_SOUT_SEL 0xf18 +#define MT8188_MERGE4_SOUT_TO_DPI1_SEL BIT(2) +#define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL BIT(3) +#define MT8188_VDO1_MIXER_IN1_SEL_IN 0xf24 +#define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN2_SEL_IN 0xf28 +#define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN3_SEL_IN 0xf2c +#define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_IN4_SEL_IN 0xf30 +#define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 +#define MT8188_VDO1_MIXER_OUT_SOUT_SEL 0xf34 +#define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 +#define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c +#define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 +#define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 +#define MT8188_SOUT_TO_MIXER_IN1_SEL 1 +#define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 +#define MT8188_SOUT_TO_MIXER_IN2_SEL 1 +#define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 +#define MT8188_SOUT_TO_MIXER_IN3_SEL 1 +#define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c +#define MT8188_SOUT_TO_MIXER_IN4_SEL 1 +#define MT8188_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 +#define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 +#define MT8188_VDO1_MIXER_IN1_SOUT_SEL 0xf58 +#define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN2_SOUT_SEL 0xf5c +#define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN3_SOUT_SEL 0xf60 +#define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_IN4_SOUT_SEL 0xf64 +#define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER 0 +#define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68 +#define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] =3D { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, @@ -146,4 +196,80 @@ static const struct mtk_mmsys_routes mmsys_mt8188_rout= ing_table[] =3D { }, }; =20 +static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] =3D= { + { + DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, + MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 + }, { + DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, + MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 + }, { + DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, + MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), + MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN1_SEL + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN2_SEL + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN3_SEL + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), + MT8188_SOUT_TO_MIXER_IN4_SEL + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), + MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL + }, { + DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT + }, { + DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, + MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), + MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), + MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER + }, { + DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, + MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), + MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), + MT8188_MERGE4_SOUT_TO_DPI1_SEL + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), + MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT + }, { + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, + MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), + MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL + } +}; + #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index ffb75711a1da..84b2d8187011 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -89,6 +89,14 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0= _driver_data =3D { .num_routes =3D ARRAY_SIZE(mmsys_mt8188_routing_table), }; =20 +static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data =3D { + .clk_driver =3D "clk-mt8188-vdo1", + .routes =3D mmsys_mt8188_vdo1_routing_table, + .num_routes =3D ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), + .num_resets =3D 96, + .vsync_len =3D 1, +}; + static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { .clk_driver =3D "clk-mt8192-mm", .routes =3D mmsys_mt8192_routing_table, @@ -431,6 +439,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = =3D { { .compatible =3D "mediatek,mt8183-mmsys", .data =3D &mt8183_mmsys_driver= _data }, { .compatible =3D "mediatek,mt8186-mmsys", .data =3D &mt8186_mmsys_driver= _data }, { .compatible =3D "mediatek,mt8188-vdosys0", .data =3D &mt8188_vdosys0_dr= iver_data }, + { .compatible =3D "mediatek,mt8188-vdosys1", .data =3D &mt8188_vdosys1_dr= iver_data }, { .compatible =3D "mediatek,mt8192-mmsys", .data =3D &mt8192_mmsys_driver= _data }, /* "mediatek,mt8195-mmsys" compatible is deprecated */ { .compatible =3D "mediatek,mt8195-mmsys", .data =3D &mt8195_vdosys0_driv= er_data }, diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mm= sys.h index 6725403d2e3a..964b5449d672 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -86,6 +86,34 @@ struct mtk_mmsys_routes { u32 val; }; =20 +/** + * struct mtk_mmsys_driver_data - settings for the mmsys + * @clk_driver: Clock driver name that the mmsys is using + * (defined in drivers/clk/mediatek/clk-*.c). + * @routes: Routing table of the mmsys. + * It provides mux settings from one module to another. + * @num_routes: Array size of the routes. + * @sw0_rst_offset: Register offset for the reset control. + * @num_resets: Number of reset bits that are defined + * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe) + * or VDOSYS (Video). Only VDOSYS needs to be added to drm dri= ver. + * @vsync_len: VSYNC length of the MIXER. + * VSYNC is usually triggered by the connector, so its length = is + * a fixed value as long as the frame rate is decided, but ETH= DR and + * MIXER generate their own VSYNC due to hardware design, ther= efore + * MIXER has to sync with ETHDR by adjusting VSYNC length. + * On MT8195, there is no such setting so we use the gap betwe= en + * falling edge and rising edge of SOF (Start of Frame) signal= to + * do the job, but since MT8188, VSYNC_LEN setting is introduc= ed to + * solve the problem and is given 0x40 (ticks) as the default = value. + * Please notice that this value has to be set to 1 (minimum) = if + * ETHDR is bypassed, otherwise MIXER could wait too long and = causing + * underflow. + * + * Each MMSYS (multi-media system) may have different settings, they may u= se + * different clock sources, mux settings, reset control ...etc., and these + * differences are all stored here. + */ struct mtk_mmsys_driver_data { const char *clk_driver; const struct mtk_mmsys_routes *routes; @@ -93,6 +121,7 @@ struct mtk_mmsys_driver_data { const u16 sw0_rst_offset; const u32 num_resets; const bool is_vppsys; + const u8 vsync_len; }; =20 /* diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mu= tex.c index 9d9f5ae578ac..e76722289175 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -133,6 +133,22 @@ #define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 #define MT8188_MUTEX_MOD2_DISP_PWM0 33 =20 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24 +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30 +#define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39 + #define MT8195_MUTEX_MOD_DISP_OVL0 0 #define MT8195_MUTEX_MOD_DISP_WDMA0 1 #define MT8195_MUTEX_MOD_DISP_RDMA0 2 @@ -264,6 +280,7 @@ #define MT8183_MUTEX_SOF_DPI0 2 #define MT8188_MUTEX_SOF_DSI0 1 #define MT8188_MUTEX_SOF_DP_INTF0 3 +#define MT8188_MUTEX_SOF_DP_INTF1 4 #define MT8195_MUTEX_SOF_DSI0 1 #define MT8195_MUTEX_SOF_DSI1 2 #define MT8195_MUTEX_SOF_DP_INTF0 3 @@ -275,6 +292,7 @@ #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) #define MT8188_MUTEX_EOF_DSI0 (MT8188_MUTEX_SOF_DSI0 << 7) #define MT8188_MUTEX_EOF_DP_INTF0 (MT8188_MUTEX_SOF_DP_INTF0 << 7) +#define MT8188_MUTEX_EOF_DP_INTF1 (MT8188_MUTEX_SOF_DP_INTF1 << 7) #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) @@ -445,6 +463,21 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONE= NT_ID_MAX] =3D { [DDP_COMPONENT_DSI0] =3D MT8188_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_PWM0] =3D MT8188_MUTEX_MOD2_DISP_PWM0, [DDP_COMPONENT_DP_INTF0] =3D MT8188_MUTEX_MOD_DISP_DP_INTF0, + [DDP_COMPONENT_DP_INTF1] =3D MT8188_MUTEX_MOD_DISP1_DP_INTF1, + [DDP_COMPONENT_ETHDR_MIXER] =3D MT8188_MUTEX_MOD_DISP1_DISP_MIXER, + [DDP_COMPONENT_MDP_RDMA0] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA0, + [DDP_COMPONENT_MDP_RDMA1] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA1, + [DDP_COMPONENT_MDP_RDMA2] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA2, + [DDP_COMPONENT_MDP_RDMA3] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA3, + [DDP_COMPONENT_MDP_RDMA4] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA4, + [DDP_COMPONENT_MDP_RDMA5] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, + [DDP_COMPONENT_MDP_RDMA6] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, + [DDP_COMPONENT_MDP_RDMA7] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_MERGE1] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, + [DDP_COMPONENT_MERGE2] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, + [DDP_COMPONENT_MERGE3] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, + [DDP_COMPONENT_MERGE4] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE3, + [DDP_COMPONENT_MERGE5] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE4, }; =20 static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] =3D { @@ -605,6 +638,8 @@ static const unsigned int mt8188_mutex_sof[DDP_MUTEX_SO= F_MAX] =3D { MT8188_MUTEX_SOF_DSI0 | MT8188_MUTEX_EOF_DSI0, [MUTEX_SOF_DP_INTF0] =3D MT8188_MUTEX_SOF_DP_INTF0 | MT8188_MUTEX_EOF_DP_INTF0, + [MUTEX_SOF_DP_INTF1] =3D + MT8188_MUTEX_SOF_DP_INTF1 | MT8188_MUTEX_EOF_DP_INTF1, }; =20 static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] =3D { --=20 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30A02EEB58C for ; Mon, 11 Sep 2023 03:17:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233340AbjIKDRN (ORCPT ); Sun, 10 Sep 2023 23:17:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232467AbjIKDQx (ORCPT ); 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charset="utf-8" - Add Padding components - Add Mutex module definitions for Padding Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mtk-mutex.c | 16 ++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 8 ++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mu= tex.c index e76722289175..73c256d3950b 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -141,6 +141,14 @@ #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 #define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8188_MUTEX_MOD_DISP1_PADDING0 8 +#define MT8188_MUTEX_MOD_DISP1_PADDING1 9 +#define MT8188_MUTEX_MOD_DISP1_PADDING2 10 +#define MT8188_MUTEX_MOD_DISP1_PADDING3 11 +#define MT8188_MUTEX_MOD_DISP1_PADDING4 12 +#define MT8188_MUTEX_MOD_DISP1_PADDING5 13 +#define MT8188_MUTEX_MOD_DISP1_PADDING6 14 +#define MT8188_MUTEX_MOD_DISP1_PADDING7 15 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 #define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 @@ -473,6 +481,14 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONE= NT_ID_MAX] =3D { [DDP_COMPONENT_MDP_RDMA5] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA5, [DDP_COMPONENT_MDP_RDMA6] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA6, [DDP_COMPONENT_MDP_RDMA7] =3D MT8188_MUTEX_MOD_DISP1_MDP_RDMA7, + [DDP_COMPONENT_PADDING0] =3D MT8188_MUTEX_MOD_DISP1_PADDING0, + [DDP_COMPONENT_PADDING1] =3D MT8188_MUTEX_MOD_DISP1_PADDING1, + [DDP_COMPONENT_PADDING2] =3D MT8188_MUTEX_MOD_DISP1_PADDING2, + [DDP_COMPONENT_PADDING3] =3D MT8188_MUTEX_MOD_DISP1_PADDING3, + [DDP_COMPONENT_PADDING4] =3D MT8188_MUTEX_MOD_DISP1_PADDING4, + [DDP_COMPONENT_PADDING5] =3D MT8188_MUTEX_MOD_DISP1_PADDING5, + [DDP_COMPONENT_PADDING6] =3D MT8188_MUTEX_MOD_DISP1_PADDING6, + [DDP_COMPONENT_PADDING7] =3D MT8188_MUTEX_MOD_DISP1_PADDING7, [DDP_COMPONENT_MERGE1] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE0, [DDP_COMPONENT_MERGE2] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE1, [DDP_COMPONENT_MERGE3] =3D MT8188_MUTEX_MOD_DISP1_VPP_MERGE2, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index 2475ef914746..4885b065b849 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -62,6 +62,14 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_PADDING0, + DDP_COMPONENT_PADDING1, + DDP_COMPONENT_PADDING2, + DDP_COMPONENT_PADDING3, + DDP_COMPONENT_PADDING4, + DDP_COMPONENT_PADDING5, + DDP_COMPONENT_PADDING6, + DDP_COMPONENT_PADDING7, DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, --=20 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 302D3EEB581 for ; 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Mon, 11 Sep 2023 11:16:39 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 09/20] soc: mediatek: Support reset bit mapping in mmsys driver Date: Mon, 11 Sep 2023 11:16:19 +0800 Message-ID: <20230911031630.12613-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Reset ID must starts from 0 and be consecutive, but the reset bits in our hardware design is not continuous, some bits are left unused, we need a map to solve the problem - Use old style 1-to-1 mapping if .rst_tb is not defined Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++ drivers/soc/mediatek/mtk-mmsys.h | 3 +++ 2 files changed, 12 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index 84b2d8187011..6fc59f85f4fa 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -310,6 +310,15 @@ static int mtk_mmsys_reset_update(struct reset_control= ler_dev *rcdev, unsigned l u32 offset; u32 reg; =20 + if (mmsys->data->rst_tb) { + if (id >=3D mmsys->data->num_resets) { + dev_err(rcdev->dev, "Invalid reset ID: %lu (>=3D%u)\n", + id, mmsys->data->num_resets); + return -EINVAL; + } + id =3D mmsys->data->rst_tb[id]; + } + offset =3D (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); id =3D id % MMSYS_SW_RESET_PER_REG; reg =3D mmsys->data->sw0_rst_offset + offset; diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mm= sys.h index 964b5449d672..dfbb742eaa11 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -78,6 +78,8 @@ #define DSI_SEL_IN_RDMA 0x1 #define DSI_SEL_IN_MASK 0x1 =20 +#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit)) + struct mtk_mmsys_routes { u32 from_comp; u32 to_comp; @@ -119,6 +121,7 @@ struct mtk_mmsys_driver_data { const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; + const u8 *rst_tb; const u32 num_resets; const bool is_vppsys; const u8 vsync_len; --=20 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FD37C71153 for ; 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Mon, 11 Sep 2023 11:16:40 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 10/20] soc: mediatek: Add MT8188 VDOSYS reset bit map Date: Mon, 11 Sep 2023 11:16:20 +0800 Message-ID: <20230911031630.12613-11-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--6.042400-8.000000 X-TMASE-MatchedRID: 9DomuZeNnSapk9YSiEd5IufHZObG8Jso6SXuwUgGH0hbKBBN5zqG8EiO 7+wNDdeYRHLRFcKKZXfbCHv011Gy9VSU1d+VJ4IjtG07VELUSnRfohHCqSnabgTozVi1xfq8MJK 6qaU5tN00ULOv9iNOM0q+cX2jmfqvmxh0gY/o+VmiAZ3zAhQYgn0tCKdnhB589yM15V5aWpj6C0 ePs7A07fyjtizU0rhjVyJ6Rrqx+FNSRMjv86A6CPVU14ep5TZkqBHnAYeJC8o= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.042400-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: E82279B5A24B85249DF1994B319FCFB8048AA702ACFE1A26D5C95CD57E1CCD592000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MT8188 reset bit map for VDOSYS0 and VDOSYS1. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mt8188-mmsys.h | 84 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 7 ++- 2 files changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mt8188-mmsys.h b/drivers/soc/mediatek/mt8= 188-mmsys.h index a9490c3c4256..6bebf1a69fc0 100644 --- a/drivers/soc/mediatek/mt8188-mmsys.h +++ b/drivers/soc/mediatek/mt8188-mmsys.h @@ -3,6 +3,10 @@ #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H #define __SOC_MEDIATEK_MT8188_MMSYS_H =20 +#include +#include + +#define MT8188_VDO0_SW0_RST_B 0x190 #define MT8188_VDO0_OVL_MOUT_EN 0xf14 #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) @@ -67,6 +71,7 @@ #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) =20 +#define MT8188_VDO1_SW0_RST_B 0x1d0 #define MT8188_VDO1_HDR_TOP_CFG 0xd00 #define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30 #define MT8188_VDO1_MIXER_IN1_PAD 0xd40 @@ -117,6 +122,85 @@ #define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68 #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 =20 +static const u8 mmsys_mt8188_vdo0_rst_tb[] =3D { + [MT8188_VDO0_RST_DISP_OVL0] =3D MMSYS_RST_NR(0, 0), + [MT8188_VDO0_RST_FAKE_ENG0] =3D MMSYS_RST_NR(0, 2), + [MT8188_VDO0_RST_DISP_CCORR0] =3D MMSYS_RST_NR(0, 4), + [MT8188_VDO0_RST_DISP_MUTEX0] =3D MMSYS_RST_NR(0, 6), + [MT8188_VDO0_RST_DISP_GAMMA0] =3D MMSYS_RST_NR(0, 8), + [MT8188_VDO0_RST_DISP_DITHER0] =3D MMSYS_RST_NR(0, 10), + [MT8188_VDO0_RST_DISP_WDMA0] =3D MMSYS_RST_NR(0, 17), + [MT8188_VDO0_RST_DISP_RDMA0] =3D MMSYS_RST_NR(0, 19), + [MT8188_VDO0_RST_DSI0] =3D MMSYS_RST_NR(0, 21), + [MT8188_VDO0_RST_DSI1] =3D MMSYS_RST_NR(0, 22), + [MT8188_VDO0_RST_DSC_WRAP0] =3D MMSYS_RST_NR(0, 23), + [MT8188_VDO0_RST_VPP_MERGE0] =3D MMSYS_RST_NR(0, 24), + [MT8188_VDO0_RST_DP_INTF0] =3D MMSYS_RST_NR(0, 25), + [MT8188_VDO0_RST_DISP_AAL0] =3D MMSYS_RST_NR(0, 26), + [MT8188_VDO0_RST_INLINEROT0] =3D MMSYS_RST_NR(0, 27), + [MT8188_VDO0_RST_APB_BUS] =3D MMSYS_RST_NR(0, 28), + [MT8188_VDO0_RST_DISP_COLOR0] =3D MMSYS_RST_NR(0, 29), + [MT8188_VDO0_RST_MDP_WROT0] =3D MMSYS_RST_NR(0, 30), + [MT8188_VDO0_RST_DISP_RSZ0] =3D MMSYS_RST_NR(0, 31), +}; + +static const u8 mmsys_mt8188_vdo1_rst_tb[] =3D { + [MT8188_VDO1_RST_SMI_LARB2] =3D MMSYS_RST_NR(0, 0), + [MT8188_VDO1_RST_SMI_LARB3] =3D MMSYS_RST_NR(0, 1), + [MT8188_VDO1_RST_GALS] =3D MMSYS_RST_NR(0, 2), + [MT8188_VDO1_RST_FAKE_ENG0] =3D MMSYS_RST_NR(0, 3), + [MT8188_VDO1_RST_FAKE_ENG1] =3D MMSYS_RST_NR(0, 4), + [MT8188_VDO1_RST_MDP_RDMA0] =3D MMSYS_RST_NR(0, 5), + [MT8188_VDO1_RST_MDP_RDMA1] =3D MMSYS_RST_NR(0, 6), + [MT8188_VDO1_RST_MDP_RDMA2] =3D MMSYS_RST_NR(0, 7), + [MT8188_VDO1_RST_MDP_RDMA3] =3D MMSYS_RST_NR(0, 8), + [MT8188_VDO1_RST_VPP_MERGE0] =3D MMSYS_RST_NR(0, 9), + [MT8188_VDO1_RST_VPP_MERGE1] =3D MMSYS_RST_NR(0, 10), + [MT8188_VDO1_RST_VPP_MERGE2] =3D MMSYS_RST_NR(0, 11), + [MT8188_VDO1_RST_VPP_MERGE3] =3D MMSYS_RST_NR(1, 0), + [MT8188_VDO1_RST_VPP_MERGE4] =3D MMSYS_RST_NR(1, 1), + [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 2), + [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 3), + [MT8188_VDO1_RST_DISP_MUTEX] =3D MMSYS_RST_NR(1, 4), + [MT8188_VDO1_RST_MDP_RDMA4] =3D MMSYS_RST_NR(1, 5), + [MT8188_VDO1_RST_MDP_RDMA5] =3D MMSYS_RST_NR(1, 6), + [MT8188_VDO1_RST_MDP_RDMA6] =3D MMSYS_RST_NR(1, 7), + [MT8188_VDO1_RST_MDP_RDMA7] =3D MMSYS_RST_NR(1, 8), + [MT8188_VDO1_RST_DP_INTF1_MMCK] =3D MMSYS_RST_NR(1, 9), + [MT8188_VDO1_RST_DPI0_MM_CK] =3D MMSYS_RST_NR(1, 10), + [MT8188_VDO1_RST_DPI1_MM_CK] =3D MMSYS_RST_NR(1, 11), + [MT8188_VDO1_RST_MERGE0_DL_ASYNC] =3D MMSYS_RST_NR(1, 13), + [MT8188_VDO1_RST_MERGE1_DL_ASYNC] =3D MMSYS_RST_NR(1, 14), + [MT8188_VDO1_RST_MERGE2_DL_ASYNC] =3D MMSYS_RST_NR(1, 15), + [MT8188_VDO1_RST_MERGE3_DL_ASYNC] =3D MMSYS_RST_NR(1, 16), + [MT8188_VDO1_RST_MERGE4_DL_ASYNC] =3D MMSYS_RST_NR(1, 17), + [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 18), + [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] =3D MMSYS_RST_NR(1, 19), + [MT8188_VDO1_RST_PADDING0] =3D MMSYS_RST_NR(1, 20), + [MT8188_VDO1_RST_PADDING1] =3D MMSYS_RST_NR(1, 21), + [MT8188_VDO1_RST_PADDING2] =3D MMSYS_RST_NR(1, 22), + [MT8188_VDO1_RST_PADDING3] =3D MMSYS_RST_NR(1, 23), + [MT8188_VDO1_RST_PADDING4] =3D MMSYS_RST_NR(1, 24), + [MT8188_VDO1_RST_PADDING5] =3D MMSYS_RST_NR(1, 25), + [MT8188_VDO1_RST_PADDING6] =3D MMSYS_RST_NR(1, 26), + [MT8188_VDO1_RST_PADDING7] =3D MMSYS_RST_NR(1, 27), + [MT8188_VDO1_RST_DISP_RSZ0] =3D MMSYS_RST_NR(1, 28), + [MT8188_VDO1_RST_DISP_RSZ1] =3D MMSYS_RST_NR(1, 29), + [MT8188_VDO1_RST_DISP_RSZ2] =3D MMSYS_RST_NR(1, 30), + [MT8188_VDO1_RST_DISP_RSZ3] =3D MMSYS_RST_NR(1, 31), + [MT8188_VDO1_RST_HDR_VDO_FE0] =3D MMSYS_RST_NR(2, 0), + [MT8188_VDO1_RST_HDR_GFX_FE0] =3D MMSYS_RST_NR(2, 1), + [MT8188_VDO1_RST_HDR_VDO_BE] =3D MMSYS_RST_NR(2, 2), + [MT8188_VDO1_RST_HDR_VDO_FE1] =3D MMSYS_RST_NR(2, 16), + [MT8188_VDO1_RST_HDR_GFX_FE1] =3D MMSYS_RST_NR(2, 17), + [MT8188_VDO1_RST_DISP_MIXER] =3D MMSYS_RST_NR(2, 18), + [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] =3D MMSYS_RST_NR(2, 19), + [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] =3D MMSYS_RST_NR(2, 20), + [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] =3D MMSYS_RST_NR(2, 21), + [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] =3D MMSYS_RST_NR(2, 22), + [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] =3D MMSYS_RST_NR(2, 23), +}; + static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] =3D { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index 6fc59f85f4fa..f89ece6739ce 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -87,13 +87,18 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys= 0_driver_data =3D { .clk_driver =3D "clk-mt8188-vdo0", .routes =3D mmsys_mt8188_routing_table, .num_routes =3D ARRAY_SIZE(mmsys_mt8188_routing_table), + .sw0_rst_offset =3D MT8188_VDO0_SW0_RST_B, + .rst_tb =3D mmsys_mt8188_vdo0_rst_tb, + .num_resets =3D ARRAY_SIZE(mmsys_mt8188_vdo0_rst_tb), }; =20 static const struct mtk_mmsys_driver_data mt8188_vdosys1_driver_data =3D { .clk_driver =3D "clk-mt8188-vdo1", .routes =3D mmsys_mt8188_vdo1_routing_table, .num_routes =3D ARRAY_SIZE(mmsys_mt8188_vdo1_routing_table), - .num_resets =3D 96, + .sw0_rst_offset =3D MT8188_VDO1_SW0_RST_B, + .rst_tb =3D mmsys_mt8188_vdo1_rst_tb, + .num_resets =3D ARRAY_SIZE(mmsys_mt8188_vdo1_rst_tb), .vsync_len =3D 1, }; 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Mon, 11 Sep 2023 11:16:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:40 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 11/20] drm/mediatek: Rename OVL_ADAPTOR_TYPE_RDMA Date: Mon, 11 Sep 2023 11:16:21 +0800 Message-ID: <20230911031630.12613-12-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.179600-8.000000 X-TMASE-MatchedRID: a85J7OO14HQsROGFNX5ZrpJAa1C/+FcuI9yVcHNDU7aOUV82NDH4ArEw JWI3UXVeT/ci3LQKeFGkV7miV6Ja8Y9oUcx9VMLgFEUknJ/kEl7dB/CxWTRRu25FeHtsUoHuOXt AaqiiMYFgWMB5WHg14RCarqF3Lc8sxYux6HDTyupgO21BQaodlQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.179600-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 3192F19A6E75A3C34FB4012B7D4A0023E8AEDCAE0C18BC745C8991D6863653302000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename OVL_ADAPTOR_TYPE_RDMA to OVL_ADAPTOR_TYPE_MDP_RDMA to align the naming rule of mtk_ovl_adaptor_comp_id. Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 6bf6367853fb..114eded8177e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -27,7 +27,7 @@ #define MTK_OVL_ADAPTOR_LAYER_NUM 4 enum mtk_ovl_adaptor_comp_type { - OVL_ADAPTOR_TYPE_RDMA =3D 0, + OVL_ADAPTOR_TYPE_MDP_RDMA =3D 0, OVL_ADAPTOR_TYPE_MERGE, OVL_ADAPTOR_TYPE_ETHDR, OVL_ADAPTOR_TYPE_NUM, @@ -62,20 +62,20 @@ struct mtk_disp_ovl_adaptor { }; static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] =3D { - [OVL_ADAPTOR_TYPE_RDMA] =3D "vdo1-rdma", + [OVL_ADAPTOR_TYPE_MDP_RDMA] =3D "vdo1-rdma", [OVL_ADAPTOR_TYPE_MERGE] =3D "merge", [OVL_ADAPTOR_TYPE_ETHDR] =3D "ethdr", }; static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { - [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_RDMA, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_RDMA, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_RDMA, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_RDMA, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_RDMA, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_RDMA, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_RDMA, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_RDMA, 7 }, + [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 }, + [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 }, + [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 }, + [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 }, + [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 }, + [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 }, + [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 }, + [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 }, [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, 1 }, [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, 2 }, [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, 3 }, @@ -388,7 +388,7 @@ static int ovl_adaptor_comp_get_id(struct device *dev, = struct device_node *node, static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] =3D { { .compatible =3D "mediatek,mt8195-vdo1-rdma", - .data =3D (void *)OVL_ADAPTOR_TYPE_RDMA, + .data =3D (void *)OVL_ADAPTOR_TYPE_MDP_RDMA, }, { .compatible =3D "mediatek,mt8195-disp-merge", .data =3D (void *)OVL_ADAPTOR_TYPE_MERGE, -- 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63CD9EEB580 for ; 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Mon, 11 Sep 2023 11:16:40 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 12/20] drm/mediatek: Refine device table of OVL adaptor Date: Mon, 11 Sep 2023 11:16:22 +0800 Message-ID: <20230911031630.12613-13-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Adjust indentation to align with other files - Sort device table in alphabetical order - Add sentinel to device table Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 114eded8177e..4a5fab5ea51f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -386,17 +386,10 @@ static int ovl_adaptor_comp_get_id(struct device *dev= , struct device_node *node, } static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] =3D { - { - .compatible =3D "mediatek,mt8195-vdo1-rdma", - .data =3D (void *)OVL_ADAPTOR_TYPE_MDP_RDMA, - }, { - .compatible =3D "mediatek,mt8195-disp-merge", - .data =3D (void *)OVL_ADAPTOR_TYPE_MERGE, - }, { - .compatible =3D "mediatek,mt8195-disp-ethdr", - .data =3D (void *)OVL_ADAPTOR_TYPE_ETHDR, - }, - {}, + { .compatible =3D "mediatek,mt8195-disp-ethdr", .data =3D (void *)OVL_ADA= PTOR_TYPE_ETHDR }, + { .compatible =3D "mediatek,mt8195-disp-merge", .data =3D (void *)OVL_ADA= PTOR_TYPE_MERGE }, + { .compatible =3D "mediatek,mt8195-vdo1-rdma", .data =3D (void *)OVL_ADAP= TOR_TYPE_MDP_RDMA }, + { /* sentinel */ } }; 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charset="utf-8" Sort OVL adaptor components' names in alphabetical order. Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 4a5fab5ea51f..72758e41b1e6 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -27,13 +27,14 @@ #define MTK_OVL_ADAPTOR_LAYER_NUM 4 enum mtk_ovl_adaptor_comp_type { - OVL_ADAPTOR_TYPE_MDP_RDMA =3D 0, - OVL_ADAPTOR_TYPE_MERGE, OVL_ADAPTOR_TYPE_ETHDR, + OVL_ADAPTOR_TYPE_MDP_RDMA, + OVL_ADAPTOR_TYPE_MERGE, OVL_ADAPTOR_TYPE_NUM, }; enum mtk_ovl_adaptor_comp_id { + OVL_ADAPTOR_ETHDR0, OVL_ADAPTOR_MDP_RDMA0, OVL_ADAPTOR_MDP_RDMA1, OVL_ADAPTOR_MDP_RDMA2, @@ -46,7 +47,6 @@ enum mtk_ovl_adaptor_comp_id { OVL_ADAPTOR_MERGE1, OVL_ADAPTOR_MERGE2, OVL_ADAPTOR_MERGE3, - OVL_ADAPTOR_ETHDR0, OVL_ADAPTOR_ID_MAX }; @@ -62,12 +62,13 @@ struct mtk_disp_ovl_adaptor { }; static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] =3D { + [OVL_ADAPTOR_TYPE_ETHDR] =3D "ethdr", [OVL_ADAPTOR_TYPE_MDP_RDMA] =3D "vdo1-rdma", [OVL_ADAPTOR_TYPE_MERGE] =3D "merge", - [OVL_ADAPTOR_TYPE_ETHDR] =3D "ethdr", }; static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { + [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, 0 }, [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 }, [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 }, [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 }, @@ -80,7 +81,6 @@ static const struct ovl_adaptor_comp_match comp_matches[O= VL_ADAPTOR_ID_MAX] =3D { [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, 2 }, [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, 3 }, [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, 4 }, - [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, 0 }, }; void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -314,6 +314,7 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device *d= ev) void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex) { + mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0); mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1); mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2); @@ -326,11 +327,11 @@ void mtk_ovl_adaptor_add_comp(struct device *dev, str= uct mtk_mutex *mutex) mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2); mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3); mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); } void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mut= ex) { + mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0); mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1); mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2); @@ -343,11 +344,11 @@ void mtk_ovl_adaptor_remove_comp(struct device *dev, = struct mtk_mutex *mutex) mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2); mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3); mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); } void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev,= unsigned int next) { + mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next); mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_M= ERGE1); mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_M= ERGE1); mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_M= ERGE2); @@ -355,11 +356,11 @@ void mtk_ovl_adaptor_connect(struct device *dev, stru= ct device *mmsys_dev, unsig mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHD= R_MIXER); mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHD= R_MIXER); mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHD= R_MIXER); - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next); } void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_d= ev, unsigned int next) { + mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next); mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONEN= T_MERGE1); mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONEN= T_MERGE1); mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONEN= T_MERGE2); @@ -367,7 +368,6 @@ void mtk_ovl_adaptor_disconnect(struct device *dev, str= uct device *mmsys_dev, un mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_E= THDR_MIXER); mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_E= THDR_MIXER); mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_E= THDR_MIXER); - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next); } static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node = *node, -- 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42BA8C71153 for ; Mon, 11 Sep 2023 03:17:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233265AbjIKDR3 (ORCPT ); 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Mon, 11 Sep 2023 11:16:41 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 11:16:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:40 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 14/20] drm/mediatek: Add component ID to component match structure Date: Mon, 11 Sep 2023 11:16:24 +0800 Message-ID: <20230911031630.12613-15-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add component ID to component match structure so we can configure them with a for-loop. The main reason we do such code refactoring is that there is a new hardware component called "Padding" since MT8188, while MT8195 doesn't have this module, we can't use the original logic to manage the components. While MT8195 does not define Padding in the device tree, the corresponding components will be NULL and being skipped by the functions. Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 69 ++++++++----------- 1 file changed, 30 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 72758e41b1e6..8a52d1301e04 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -52,6 +52,7 @@ enum mtk_ovl_adaptor_comp_id { struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; + enum mtk_ddp_comp_id comp_id; int alias_id; }; @@ -68,19 +69,19 @@ static const char * const private_comp_stem[OVL_ADAPTOR= _TYPE_NUM] =3D { }; static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { - [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, 0 }, - [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, 7 }, - [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, 1 }, - [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, 2 }, - [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, 3 }, - [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, 4 }, + [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MI= XER, 0 }, + [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA0, 0 }, + [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA1, 1 }, + [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA2, 2 }, + [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA3, 3 }, + [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA4, 4 }, + [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA5, 5 }, + [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA6, 6 }, + [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA7, 7 }, + [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, = 1 }, + [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2 }, + [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3 }, + [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4 }, }; void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -314,36 +315,26 @@ size_t mtk_ovl_adaptor_get_num_formats(struct device = *dev) void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex) { - mtk_mutex_add_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_add_comp(mutex, DDP_COMPONENT_MERGE4); + int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_add_comp(mutex, comp_matches[i].comp_id); + } } void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mut= ex) { - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_ETHDR_MIXER); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA0); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA4); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA5); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA6); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MDP_RDMA7); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE1); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE2); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE3); - mtk_mutex_remove_comp(mutex, DDP_COMPONENT_MERGE4); + int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { + if (!ovl_adaptor->ovl_adaptor_comp[i]) + continue; + mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id); + } } void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev,= unsigned int next) -- 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C9DDEEB57D for ; Mon, 11 Sep 2023 03:17:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233435AbjIKDRe (ORCPT ); Sun, 10 Sep 2023 23:17:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232772AbjIKDQ4 (ORCPT ); Sun, 10 Sep 2023 23:16:56 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1590111C for ; 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Mon, 11 Sep 2023 11:16:41 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 11:16:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:40 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 15/20] drm/mediatek: Manage component's clock with function pointers Date: Mon, 11 Sep 2023 11:16:25 +0800 Message-ID: <20230911031630.12613-16-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" By registering component related functions to the pointers, we can easily manage them within a for-loop and simplify the logic of clock control significantly. Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 111 +++++++----------- 1 file changed, 44 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 8a52d1301e04..84133303a6ec 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -54,6 +54,7 @@ struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; enum mtk_ddp_comp_id comp_id; int alias_id; + const struct mtk_ddp_comp_funcs *funcs; }; struct mtk_disp_ovl_adaptor { @@ -68,20 +69,35 @@ static const char * const private_comp_stem[OVL_ADAPTOR= _TYPE_NUM] =3D { [OVL_ADAPTOR_TYPE_MERGE] =3D "merge", }; +static const struct mtk_ddp_comp_funcs _ethdr =3D { + .clk_enable =3D mtk_ethdr_clk_enable, + .clk_disable =3D mtk_ethdr_clk_disable, +}; + +static const struct mtk_ddp_comp_funcs _merge =3D { + .clk_enable =3D mtk_merge_clk_enable, + .clk_disable =3D mtk_merge_clk_disable, +}; + +static const struct mtk_ddp_comp_funcs _rdma =3D { + .clk_enable =3D mtk_mdp_rdma_clk_enable, + .clk_disable =3D mtk_mdp_rdma_clk_disable, +}; + static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { - [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MI= XER, 0 }, - [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA0, 0 }, - [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA1, 1 }, - [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA2, 2 }, - [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA3, 3 }, - [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA4, 4 }, - [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA5, 5 }, - [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA6, 6 }, - [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA7, 7 }, - [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, = 1 }, - [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2 }, - [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3 }, - [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4 }, + [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MI= XER, 0, &_ethdr }, + [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA0, 0, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA1, 1, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA2, 2, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA3, 3, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA4, 4, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA5, 5, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA6, 6, &_rdma }, + [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA7, 7, &_rdma }, + [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, = 1, &_merge }, + [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2, &_merge }, + [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3, &_merge }, + [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4, &_merge }, }; void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -187,73 +203,34 @@ void mtk_ovl_adaptor_stop(struct device *dev) int mtk_ovl_adaptor_clk_enable(struct device *dev) { - struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); - struct device *comp; - int ret; int i; - - for (i =3D 0; i < OVL_ADAPTOR_MERGE0; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - ret =3D pm_runtime_get_sync(comp); - if (ret < 0) { - dev_err(dev, "Failed to enable power domain %d, err %d\n", i, ret); - goto pwr_err; - } - } + int ret; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - - if (i < OVL_ADAPTOR_MERGE0) - ret =3D mtk_mdp_rdma_clk_enable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) - ret =3D mtk_merge_clk_enable(comp); - else - ret =3D mtk_ethdr_clk_enable(comp); + dev =3D ovl_adaptor->ovl_adaptor_comp[i]; + if (!dev) + continue; + ret =3D comp_matches[i].funcs->clk_enable(dev); if (ret) { - dev_err(dev, "Failed to enable clock %d, err %d\n", i, ret); - goto clk_err; + while (--i >=3D 0) + comp_matches[i].funcs->clk_disable(dev); + return ret; } } - - return ret; - -clk_err: - while (--i >=3D 0) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - if (i < OVL_ADAPTOR_MERGE0) - mtk_mdp_rdma_clk_disable(comp); - else if (i < OVL_ADAPTOR_ETHDR0) - mtk_merge_clk_disable(comp); - else - mtk_ethdr_clk_disable(comp); - } - i =3D OVL_ADAPTOR_MERGE0; - -pwr_err: - while (--i >=3D 0) - pm_runtime_put(ovl_adaptor->ovl_adaptor_comp[i]); - - return ret; + return 0; } void mtk_ovl_adaptor_clk_disable(struct device *dev) { - struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); - struct device *comp; int i; + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { - comp =3D ovl_adaptor->ovl_adaptor_comp[i]; - - if (i < OVL_ADAPTOR_MERGE0) { - mtk_mdp_rdma_clk_disable(comp); - pm_runtime_put(comp); - } else if (i < OVL_ADAPTOR_ETHDR0) { - mtk_merge_clk_disable(comp); - } else { - mtk_ethdr_clk_disable(comp); - } + dev =3D ovl_adaptor->ovl_adaptor_comp[i]; + if (!dev) + continue; + comp_matches[i].funcs->clk_disable(dev); } } -- 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE878EE49A4 for ; Mon, 11 Sep 2023 03:17:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233357AbjIKDRP (ORCPT ); Sun, 10 Sep 2023 23:17:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232477AbjIKDQy (ORCPT ); Sun, 10 Sep 2023 23:16:54 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB623110 for ; Sun, 10 Sep 2023 20:16:49 -0700 (PDT) X-UUID: a14dbd08505111eea33bb35ae8d461a2-20230911 DKIM-Signature: v=1; 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Mon, 11 Sep 2023 11:16:42 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 11:16:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:40 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 16/20] drm/mediatek: Make sure the power-on sequence of LARB and RDMA Date: Mon, 11 Sep 2023 11:16:26 +0800 Message-ID: <20230911031630.12613-17-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since LARBs (Local ARBiter) have to be powered on before its users, to ensure the power-on sequence, we created a device link between RDMA and its LARB, and when pm_runtime_get_sync is called in RDMA, system will guarantee the LARB is powered on before the RDMA. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/medi= atek/mtk_mdp_rdma.c index c3adaeefd551..fce6fbb534b1 100644 --- a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c @@ -244,10 +244,23 @@ size_t mtk_mdp_rdma_get_num_formats(struct device *de= v) int mtk_mdp_rdma_clk_enable(struct device *dev) { + int ret; struct mtk_mdp_rdma *rdma =3D dev_get_drvdata(dev); - clk_prepare_enable(rdma->clk); - return 0; + /* + * Since LARBs (Local ARBiter) have to be powered on before its users, + * to ensure the power-on sequence, we created a device link between + * RDMA and its LARB, and when pm_runtime_get_sync is called in RDMA, + * system will make sure the LARB is powered on before the RDMA + */ + ret =3D pm_runtime_get_sync(dev); + + if (ret < 0) + dev_err(dev, "pm_runtime_get_sync failed: %d\n", ret); + else + ret =3D clk_prepare_enable(rdma->clk); + + return ret; } void mtk_mdp_rdma_clk_disable(struct device *dev) @@ -255,6 +268,9 @@ void mtk_mdp_rdma_clk_disable(struct device *dev) struct mtk_mdp_rdma *rdma =3D dev_get_drvdata(dev); clk_disable_unprepare(rdma->clk); + + /* Same reason as when enabling clock, turn the LARB off */ + pm_runtime_put(dev); } static int mtk_mdp_rdma_bind(struct device *dev, struct device *master, -- 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8A1EEEB58C for ; Mon, 11 Sep 2023 03:17:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232172AbjIKDRh (ORCPT ); Sun, 10 Sep 2023 23:17:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232801AbjIKDQ4 (ORCPT ); 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Mon, 11 Sep 2023 11:16:42 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 11:16:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:41 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 17/20] drm/mediatek: Support MT8188 Padding in display driver Date: Mon, 11 Sep 2023 11:16:27 +0800 Message-ID: <20230911031630.12613-18-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--9.388500-8.000000 X-TMASE-MatchedRID: 9nkzMtsPLI7yZ92BnYqk5lz+axQLnAVB2+EpBnZEzfWNTnqOMBIJ4WlW Rvn/M8gY+C56g4Ua7emMWZk+4DO9WLgSigd+50baiS8eKdD/7uRaNaxZBRbNWkdmDSBYfnJRRzB gyFiNMBgHnuQrI7SweSc4AVgtpRONJBVW14/3QK0D2WXLXdz+AQrefVId6fzV1yGUyFK3oV4wKY tIU69m3V+2TZ8bogGeASo1XNPhrPrB1tTdqQfkDG3NvezwBrVm+LidURF+DB3xCQaCt6X8brCza +U6obX4wBpgf0BadqINBaBCS6tQ1OaqzANVaJArZRXMZqv808+7nrAU9KQxUVFFa3XGCWSdMH1x x17eFtSugpIE2nzunoAy6p60ZV62fJ5/bZ6npdg7AFczfjr/7FcorynoL/RgvTe8xjOg64FH+qX jn9cDIpAfSfwFez3WHw/cFVUOMXU= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--9.388500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: E556F98070C384CE9E95B3626FB0FF8322F05552710EA71DE5B160F8430D49502000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Padding is a new display module on MT8188, it provides ability to add pixels to width and height of a layer with specified colors. Due to hardware design, Mixer in VDOSYS1 requires width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled, we need Padding to deal with odd width. Please notice that even if the Padding is in bypass mode, settings in register must be cleared to 0, or undefined behaviors could happen. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_padding.c | 136 ++++++++++++++++++++++++ 5 files changed, 143 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_padding.c diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/M= akefile index d4d193f60271..5e4436403b8d 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -16,7 +16,8 @@ mediatek-drm-y :=3D mtk_disp_aal.o \ mtk_dsi.o \ mtk_dpi.o \ mtk_ethdr.o \ - mtk_mdp_rdma.o + mtk_mdp_rdma.o \ + mtk_padding.o =20 obj-$(CONFIG_DRM_MEDIATEK) +=3D mediatek-drm.o =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 2254038519e1..f9fdb1268aa5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -157,4 +157,7 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk= _mdp_rdma_cfg *cfg, const u32 *mtk_mdp_rdma_get_formats(struct device *dev); size_t mtk_mdp_rdma_get_num_formats(struct device *dev); =20 +int mtk_padding_clk_enable(struct device *dev); +void mtk_padding_clk_disable(struct device *dev); +void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt); #endif diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 93552d76b6e7..cde69f39a066 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -973,6 +973,7 @@ static struct platform_driver * const mtk_drm_drivers[]= =3D { &mtk_dsi_driver, &mtk_ethdr_driver, &mtk_mdp_rdma_driver, + &mtk_padding_driver, }; =20 static int __init mtk_drm_init(void) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/media= tek/mtk_drm_drv.h index eb2fd45941f0..562f2db47add 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -64,5 +64,5 @@ extern struct platform_driver mtk_dpi_driver; extern struct platform_driver mtk_dsi_driver; extern struct platform_driver mtk_ethdr_driver; extern struct platform_driver mtk_mdp_rdma_driver; - +extern struct platform_driver mtk_padding_driver; #endif /* MTK_DRM_DRV_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_padding.c b/drivers/gpu/drm/media= tek/mtk_padding.c new file mode 100644 index 000000000000..bbb9c5e286ce --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_padding.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +/** + * struct mtk_padding - basic information of Padding + * @clk: Clock of the module + * @regs: Virtual address of the Padding for CPU to access + * @cmdq_reg: CMDQ setting of the Padding + * + * Every Padding should have different clock source, register base, and + * CMDQ settings, we stored these differences all together. + */ +struct mtk_padding { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; +}; + +int mtk_padding_clk_enable(struct device *dev) +{ + struct mtk_padding *padding =3D dev_get_drvdata(dev); + + return clk_prepare_enable(padding->clk); +} + +void mtk_padding_clk_disable(struct device *dev) +{ + struct mtk_padding *padding =3D dev_get_drvdata(dev); + + clk_disable_unprepare(padding->clk); +} + +void mtk_padding_config(struct device *dev, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_padding *padding =3D dev_get_drvdata(dev); + + /* bypass padding */ + mtk_ddp_write_mask(cmdq_pkt, GENMASK(1, 0), &padding->cmdq_reg, padding->= regs, 0, + GENMASK(1, 0)); +} + +static int mtk_padding_bind(struct device *dev, struct device *master, voi= d *data) +{ + return 0; +} + +static void mtk_padding_unbind(struct device *dev, struct device *master, = void *data) +{ +} + +static const struct component_ops mtk_padding_component_ops =3D { + .bind =3D mtk_padding_bind, + .unbind =3D mtk_padding_unbind, +}; + +static int mtk_padding_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mtk_padding *priv; + struct resource *res; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get clk\n"); + return PTR_ERR(priv->clk); + } + + priv->regs =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to do ioremap\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret =3D cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) { + dev_err(dev, "failed to get gce client reg\n"); + return ret; + } +#endif + + platform_set_drvdata(pdev, priv); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret =3D component_add(dev, &mtk_padding_component_ops); + if (ret) { + pm_runtime_disable(dev); + return dev_err_probe(dev, ret, "failed to add component\n"); + } + + return 0; +} + +static int mtk_padding_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_padding_component_ops); + return 0; +} + +static const struct of_device_id mtk_padding_driver_dt_match[] =3D { + { .compatible =3D "mediatek,mt8188-padding" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mtk_padding_driver_dt_match); + +struct platform_driver mtk_padding_driver =3D { + .probe =3D mtk_padding_probe, + .remove =3D mtk_padding_remove, + .driver =3D { + .name =3D "mediatek-padding", + .owner =3D THIS_MODULE, + .of_match_table =3D mtk_padding_driver_dt_match, + }, +}; --=20 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28475C71153 for ; Mon, 11 Sep 2023 03:17:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233333AbjIKDRL (ORCPT ); Sun, 10 Sep 2023 23:17:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232354AbjIKDQx (ORCPT ); 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Mon, 11 Sep 2023 11:16:41 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 11 Sep 2023 11:16:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 11 Sep 2023 11:16:41 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 18/20] drm/mediatek: Add Padding to OVL adaptor Date: Mon, 11 Sep 2023 11:16:28 +0800 Message-ID: <20230911031630.12613-19-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MT8188 Padding to OVL adaptor to probe the driver. Signed-off-by: Hsiao Chien Sung --- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 84133303a6ec..217c39af27bd 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -30,6 +30,7 @@ enum mtk_ovl_adaptor_comp_type { OVL_ADAPTOR_TYPE_ETHDR, OVL_ADAPTOR_TYPE_MDP_RDMA, OVL_ADAPTOR_TYPE_MERGE, + OVL_ADAPTOR_TYPE_PADDING, OVL_ADAPTOR_TYPE_NUM, }; @@ -47,6 +48,14 @@ enum mtk_ovl_adaptor_comp_id { OVL_ADAPTOR_MERGE1, OVL_ADAPTOR_MERGE2, OVL_ADAPTOR_MERGE3, + OVL_ADAPTOR_PADDING0, + OVL_ADAPTOR_PADDING1, + OVL_ADAPTOR_PADDING2, + OVL_ADAPTOR_PADDING3, + OVL_ADAPTOR_PADDING4, + OVL_ADAPTOR_PADDING5, + OVL_ADAPTOR_PADDING6, + OVL_ADAPTOR_PADDING7, OVL_ADAPTOR_ID_MAX }; @@ -67,6 +76,7 @@ static const char * const private_comp_stem[OVL_ADAPTOR_T= YPE_NUM] =3D { [OVL_ADAPTOR_TYPE_ETHDR] =3D "ethdr", [OVL_ADAPTOR_TYPE_MDP_RDMA] =3D "vdo1-rdma", [OVL_ADAPTOR_TYPE_MERGE] =3D "merge", + [OVL_ADAPTOR_TYPE_PADDING] =3D "padding", }; static const struct mtk_ddp_comp_funcs _ethdr =3D { @@ -79,6 +89,11 @@ static const struct mtk_ddp_comp_funcs _merge =3D { .clk_disable =3D mtk_merge_clk_disable, }; +static const struct mtk_ddp_comp_funcs _padding =3D { + .clk_enable =3D mtk_padding_clk_enable, + .clk_disable =3D mtk_padding_clk_disable, +}; + static const struct mtk_ddp_comp_funcs _rdma =3D { .clk_enable =3D mtk_mdp_rdma_clk_enable, .clk_disable =3D mtk_mdp_rdma_clk_disable, @@ -98,6 +113,14 @@ static const struct ovl_adaptor_comp_match comp_matches= [OVL_ADAPTOR_ID_MAX] =3D { [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2, &_merge }, [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3, &_merge }, [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4, &_merge }, + [OVL_ADAPTOR_PADDING0] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING0, 0, &_padding }, + [OVL_ADAPTOR_PADDING1] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING1, 1, &_padding }, + [OVL_ADAPTOR_PADDING2] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING2, 2, &_padding }, + [OVL_ADAPTOR_PADDING3] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING3, 3, &_padding }, + [OVL_ADAPTOR_PADDING4] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING4, 4, &_padding }, + [OVL_ADAPTOR_PADDING5] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING5, 5, &_padding }, + [OVL_ADAPTOR_PADDING6] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING6, 6, &_padding }, + [OVL_ADAPTOR_PADDING7] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING7, 7, &_padding }, }; void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -109,6 +132,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, u= nsigned int idx, struct mtk_mdp_rdma_cfg rdma_config =3D {0}; struct device *rdma_l; struct device *rdma_r; + struct device *padding_l; + struct device *padding_r; struct device *merge; struct device *ethdr; const struct drm_format_info *fmt_info =3D drm_format_info(pending->forma= t); @@ -125,6 +150,8 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, u= nsigned int idx, rdma_l =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx]; rdma_r =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx = + 1]; + padding_l =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * id= x]; + padding_r =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_PADDING0 + 2 * id= x + 1]; merge =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx]; ethdr =3D ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]; @@ -160,10 +187,15 @@ void mtk_ovl_adaptor_layer_config(struct device *dev,= unsigned int idx, rdma_config.color_encoding =3D pending->color_encoding; mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt); + if (padding_l) + mtk_padding_config(padding_l, cmdq_pkt); + if (use_dual_pipe) { rdma_config.x_left =3D l_w; rdma_config.width =3D r_w; mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt); + if (padding_r) + mtk_padding_config(padding_r, cmdq_pkt); } mtk_merge_start_cmdq(merge, cmdq_pkt); @@ -354,6 +386,7 @@ static int ovl_adaptor_comp_get_id(struct device *dev, = struct device_node *node, } static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] =3D { + { .compatible =3D "mediatek,mt8188-padding", .data =3D (void *)OVL_ADAPTO= R_TYPE_PADDING }, { .compatible =3D "mediatek,mt8195-disp-ethdr", .data =3D (void *)OVL_ADA= PTOR_TYPE_ETHDR }, { .compatible =3D "mediatek,mt8195-disp-merge", .data =3D (void *)OVL_ADA= PTOR_TYPE_MERGE }, { .compatible =3D "mediatek,mt8195-vdo1-rdma", .data =3D (void *)OVL_ADAP= TOR_TYPE_MDP_RDMA }, -- 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AB98EE49A4 for ; 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Mon, 11 Sep 2023 11:16:41 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 19/20] drm/mediatek: Support MT8188 VDOSYS1 in display driver Date: Mon, 11 Sep 2023 11:16:29 +0800 Message-ID: <20230911031630.12613-20-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - The mmsys_dev_num in MT8188 VDOSYS0 was set to 1 since VDOSYS1 was not available before. Increase it to support VDOSYS1 in display driver. - Add compatible name for MT8188 VDOSYS1 (shares the same driver data with MT8195 VDOSYS1) Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index cde69f39a066..212475436f47 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -288,6 +288,7 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_= driver_data =3D { static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data =3D { .main_path =3D mt8188_mtk_ddp_main, .main_len =3D ARRAY_SIZE(mt8188_mtk_ddp_main), + .mmsys_dev_num =3D 2, }; =20 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { @@ -328,6 +329,8 @@ static const struct of_device_id mtk_drm_of_ids[] =3D { .data =3D &mt8186_mmsys_driver_data}, { .compatible =3D "mediatek,mt8188-vdosys0", .data =3D &mt8188_vdosys0_driver_data}, + { .compatible =3D "mediatek,mt8188-vdosys1", + .data =3D &mt8195_vdosys1_driver_data}, { .compatible =3D "mediatek,mt8192-mmsys", .data =3D &mt8192_mmsys_driver_data}, { .compatible =3D "mediatek,mt8195-mmsys", --=20 2.18.0 From nobody Fri Sep 20 12:39:18 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BE3CEEB57D for ; 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Mon, 11 Sep 2023 11:16:41 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel CC: , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v6 20/20] drm/mediatek: Set DPI input to 1T2P mode Date: Mon, 11 Sep 2023 11:16:30 +0800 Message-ID: <20230911031630.12613-21-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230911031630.12613-1-shawn.sung@mediatek.com> References: <20230911031630.12613-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--6.788100-8.000000 X-TMASE-MatchedRID: PHWFXbsmkDRF/TNFimjSuEOZWaJBszmq3zhylsE9dsyOUV82NDH4AlO4 BD7nLMxnThbvLLI8RvNq7k1NHAqvK5sYdIGP6PlZjtK7dC6UBnl9LQinZ4QefCP/VFuTOXUT3n8 eBZjGmUzkwjHXXC/4IzsAVzN+Ov/stIQSbsaENgdNt2l9xnSaYRy2fvzjG4gKnxMQcCdlcTFN1W 7aDGzFOw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.788100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 7D04BE8CC1289EA185DC848879D82B244F00FB84F227E88D924EAC7D2165EF532000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DPI input is in 1T2P mode on MT8195, align the setting of MT8188 with it, otherwise the screen will glitch. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 2f931e4e2b60..c6ee21e275ba 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -963,7 +963,7 @@ static const struct mtk_dpi_conf mt8188_dpintf_conf =3D= { .output_fmts =3D mt8195_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8195_output_fmts), .pixels_per_iter =3D 4, - .input_2pixel =3D false, + .input_2pixel =3D true, .dimension_mask =3D DPINTF_HPW_MASK, .hvsize_mask =3D DPINTF_HSIZE_MASK, .channel_swap_shift =3D DPINTF_CH_SWAP, -- 2.18.0