From nobody Sun Feb 8 18:48:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C2B8EC8758 for ; Thu, 7 Sep 2023 21:00:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240542AbjIGVAk (ORCPT ); Thu, 7 Sep 2023 17:00:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230091AbjIGVAi (ORCPT ); Thu, 7 Sep 2023 17:00:38 -0400 Received: from imap4.hz.codethink.co.uk (imap4.hz.codethink.co.uk [188.40.203.114]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F2E81BCB for ; Thu, 7 Sep 2023 14:00:34 -0700 (PDT) Received: from [134.238.52.102] (helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1qeHcf-004U1Q-Gf; Thu, 07 Sep 2023 17:12:49 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1qeHcd-000HV4-2m; Thu, 07 Sep 2023 17:12:47 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha Subject: [PATCH v9 4/6] pwm: dwc: use clock rate in hz to avoid rounding issues Date: Thu, 7 Sep 2023 17:12:40 +0100 Message-Id: <20230907161242.67190-5-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230907161242.67190-1-ben.dooks@codethink.co.uk> References: <20230907161242.67190-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As noted, the clock-rate when not a nice multiple of ns is probably going to end up with inacurate calculations, as well as on a non pci system the rate may change (although we've not put a clock rate change notifier in this code yet) so we also add some quick checks of the rate when we do any calculations with it. Signed-off-by; Ben Dooks Reported-by: Uwe Kleine-K=C3=B6nig --- v9: - fixed commit spelling - changed to use codethink email instead of sifive v8: - fixup post rename - move to earlier in series --- drivers/pwm/pwm-dwc-core.c | 24 +++++++++++++++--------- drivers/pwm/pwm-dwc.h | 2 +- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c index 3fc281a78c9a..3b856685029d 100644 --- a/drivers/pwm/pwm-dwc-core.c +++ b/drivers/pwm/pwm-dwc-core.c @@ -49,13 +49,14 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dw= c, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); + tmp =3D state->duty_cycle * dwc->clk_rate; + tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low =3D tmp - 1; =20 - tmp =3D DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - dwc->clk_ns); + tmp =3D (state->period - state->duty_cycle) * dwc->clk_rate; + tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high =3D tmp - 1; @@ -121,11 +122,14 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, s= truct pwm_device *pwm, struct pwm_state *state) { struct dwc_pwm *dwc =3D to_dwc_pwm(chip); + unsigned long clk_rate; u64 duty, period; u32 ctrl, ld, ld2; =20 pm_runtime_get_sync(chip->dev); =20 + clk_rate =3D dwc->clk_rate; + ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); ld =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); ld2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); @@ -137,17 +141,19 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, s= truct pwm_device *pwm, * based on the timer load-count only. */ if (ctrl & DWC_TIM_CTRL_PWM) { - duty =3D (ld + 1) * dwc->clk_ns; - period =3D (ld2 + 1) * dwc->clk_ns; + duty =3D ld + 1; + period =3D ld2 + 1; period +=3D duty; } else { - duty =3D (ld + 1) * dwc->clk_ns; + duty =3D ld + 1; period =3D duty * 2; } =20 + duty *=3D NSEC_PER_SEC; + period *=3D NSEC_PER_SEC; + state->period =3D DIV_ROUND_CLOSEST_ULL(period, clk_rate); + state->duty_cycle =3D DIV_ROUND_CLOSEST_ULL(duty, clk_rate); state->polarity =3D PWM_POLARITY_INVERSED; - state->period =3D period; - state->duty_cycle =3D duty; =20 pm_runtime_put_sync(chip->dev); =20 @@ -168,7 +174,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; =20 - dwc->clk_ns =3D 10; + dwc->clk_rate =3D NSEC_PER_SEC / 10; dwc->chip.dev =3D dev; dwc->chip.ops =3D &dwc_pwm_ops; dwc->chip.npwm =3D DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index 64795247c54c..e0a940fd6e87 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -42,7 +42,7 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; - unsigned int clk_ns; + unsigned long clk_rate; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) --=20 2.40.1