From nobody Fri Dec 19 04:58:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29905EC8743 for ; Thu, 7 Sep 2023 16:45:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235465AbjIGQp6 (ORCPT ); Thu, 7 Sep 2023 12:45:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234303AbjIGQpx (ORCPT ); Thu, 7 Sep 2023 12:45:53 -0400 Received: from imap5.colo.codethink.co.uk (imap5.colo.codethink.co.uk [78.40.148.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3763A19A8; Thu, 7 Sep 2023 09:45:19 -0700 (PDT) Received: from [134.238.52.102] (helo=rainbowdash) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1qeHce-0052RE-DU; Thu, 07 Sep 2023 17:12:48 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1qeHcd-000HUp-2W; Thu, 07 Sep 2023 17:12:47 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha Subject: [PATCH v9 1/6] pwm: dwc: split pci out of core driver Date: Thu, 7 Sep 2023 17:12:37 +0100 Message-Id: <20230907161242.67190-2-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230907161242.67190-1-ben.dooks@codethink.co.uk> References: <20230907161242.67190-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Moving towards adding non-pci support for the driver, move the pci parts out of the core into their own module. This is partly due to the module_driver() code only being allowed once in a module and also to avoid a number of #ifdef if we build a single file in a system without pci support. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-K=C3=B6nig --- v9: - change back to codethink email from sifive v8: - add module namespace - remove compile-test for pci case, doesn't make sense - fix makefile, missed config symbol changes v7: - re-order kconfig to make dwc core be selected by PCI driver v6: - put DWC_PERIOD_NS back to avoid bisect issues v4: - removed DWC_PERIOD_NS as not needed --- drivers/pwm/Kconfig | 14 ++- drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-core.c | 176 +++++++++++++++++++++++++++++++++ drivers/pwm/pwm-dwc.c | 197 +------------------------------------ drivers/pwm/pwm-dwc.h | 60 +++++++++++ 5 files changed, 253 insertions(+), 195 deletions(-) create mode 100644 drivers/pwm/pwm-dwc-core.c create mode 100644 drivers/pwm/pwm-dwc.h diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8ebcddf91f7b..507c8b8547a5 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -186,9 +186,19 @@ config PWM_CROS_EC PWM driver for exposing a PWM attached to the ChromeOS Embedded Controller. =20 +config PWM_DWC_CORE + tristate + depends on HAS_IOMEM + help + PWM driver for Synopsys DWC PWM Controller. + + To compile this driver as a module, build the dependecies as + modules, this will be called pwm-dwc-core. + config PWM_DWC - tristate "DesignWare PWM Controller" - depends on PCI + tristate "DesignWare PWM Controller (PCI bus)" + depends on HAS_IOMEM && PCI + select PWM_DWC_CORE help PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. =20 diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c822389c2a24..c5ec9e168ee7 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLK) +=3D pwm-clk.o obj-$(CONFIG_PWM_CLPS711X) +=3D pwm-clps711x.o obj-$(CONFIG_PWM_CRC) +=3D pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) +=3D pwm-cros-ec.o +obj-$(CONFIG_PWM_DWC_CORE) +=3D pwm-dwc-core.o obj-$(CONFIG_PWM_DWC) +=3D pwm-dwc.o obj-$(CONFIG_PWM_EP93XX) +=3D pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) +=3D pwm-fsl-ftm.o diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c new file mode 100644 index 000000000000..b693cb7fa812 --- /dev/null +++ b/drivers/pwm/pwm-dwc-core.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver core + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + */ + +#define DEFAULT_SYMBOL_NAMESPACE dwc_pwm + +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) +{ + u32 reg; + + reg =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm)); + + if (enabled) + reg |=3D DWC_TIM_CTRL_EN; + else + reg &=3D ~DWC_TIM_CTRL_EN; + + dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm)); +} + +static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, + struct pwm_device *pwm, + const struct pwm_state *state) +{ + u64 tmp; + u32 ctrl; + u32 high; + u32 low; + + /* + * Calculate width of low and high period in terms of input clock + * periods and check are the result within HW limits between 1 and + * 2^32 periods. + */ + tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); + if (tmp < 1 || tmp > (1ULL << 32)) + return -ERANGE; + low =3D tmp - 1; + + tmp =3D DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, + DWC_CLK_PERIOD_NS); + if (tmp < 1 || tmp > (1ULL << 32)) + return -ERANGE; + high =3D tmp - 1; + + /* + * Specification says timer usage flow is to disable timer, then + * program it followed by enable. It also says Load Count is loaded + * into timer after it is enabled - either after a disable or + * a reset. Based on measurements it happens also without disable + * whenever Load Count is updated. But follow the specification. + */ + __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); + + /* + * Write Load Count and Load Count 2 registers. Former defines the + * width of low period and latter the width of high period in terms + * multiple of input clock periods: + * Width =3D ((Count + 1) * input clock period). + */ + dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm)); + dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm)); + + /* + * Set user-defined mode, timer reloads from Load Count registers + * when it counts down to 0. + * Set PWM mode, it makes output to toggle and width of low and high + * periods are set by Load Count registers. + */ + ctrl =3D DWC_TIM_CTRL_MODE_USER | DWC_TIM_CTRL_PWM; + dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm)); + + /* + * Enable timer. Output starts from low period. + */ + __dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled); + + return 0; +} + +static int dwc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct dwc_pwm *dwc =3D to_dwc_pwm(chip); + + if (state->polarity !=3D PWM_POLARITY_INVERSED) + return -EINVAL; + + if (state->enabled) { + if (!pwm->state.enabled) + pm_runtime_get_sync(chip->dev); + return __dwc_pwm_configure_timer(dwc, pwm, state); + } else { + if (pwm->state.enabled) { + __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); + pm_runtime_put_sync(chip->dev); + } + } + + return 0; +} + +static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct dwc_pwm *dwc =3D to_dwc_pwm(chip); + u64 duty, period; + + pm_runtime_get_sync(chip->dev); + + state->enabled =3D !!(dwc_pwm_readl(dwc, + DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + + duty =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + duty +=3D 1; + duty *=3D DWC_CLK_PERIOD_NS; + state->duty_cycle =3D duty; + + period =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); + period +=3D 1; + period *=3D DWC_CLK_PERIOD_NS; + period +=3D duty; + state->period =3D period; + + state->polarity =3D PWM_POLARITY_INVERSED; + + pm_runtime_put_sync(chip->dev); + + return 0; +} + +static const struct pwm_ops dwc_pwm_ops =3D { + .apply =3D dwc_pwm_apply, + .get_state =3D dwc_pwm_get_state, + .owner =3D THIS_MODULE, +}; + +struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +{ + struct dwc_pwm *dwc; + + dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + if (!dwc) + return NULL; + + dwc->chip.dev =3D dev; + dwc->chip.ops =3D &dwc_pwm_ops; + dwc->chip.npwm =3D DWC_TIMERS_TOTAL; + + dev_set_drvdata(dev, dwc); + return dwc; +} +EXPORT_SYMBOL_GPL(dwc_pwm_alloc); + +MODULE_AUTHOR("Felipe Balbi (Intel)"); +MODULE_AUTHOR("Jarkko Nikula "); +MODULE_AUTHOR("Raymond Tan "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 3bbb26c862c3..bd9cadb497d7 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * DesignWare PWM Controller driver + * DesignWare PWM Controller driver (PCI part) * * Copyright (C) 2018-2020 Intel Corporation * @@ -13,6 +13,8 @@ * periods are one or more input clock periods long. */ =20 +#define DEFAULT_MOUDLE_NAMESPACE dwc_pwm + #include #include #include @@ -21,198 +23,7 @@ #include #include =20 -#define DWC_TIM_LD_CNT(n) ((n) * 0x14) -#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) -#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) -#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) -#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) -#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) - -#define DWC_TIMERS_INT_STS 0xa0 -#define DWC_TIMERS_EOI 0xa4 -#define DWC_TIMERS_RAW_INT_STS 0xa8 -#define DWC_TIMERS_COMP_VERSION 0xac - -#define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 - -/* Timer Control Register */ -#define DWC_TIM_CTRL_EN BIT(0) -#define DWC_TIM_CTRL_MODE BIT(1) -#define DWC_TIM_CTRL_MODE_FREE (0 << 1) -#define DWC_TIM_CTRL_MODE_USER (1 << 1) -#define DWC_TIM_CTRL_INT_MASK BIT(2) -#define DWC_TIM_CTRL_PWM BIT(3) - -struct dwc_pwm_ctx { - u32 cnt; - u32 cnt2; - u32 ctrl; -}; - -struct dwc_pwm { - struct pwm_chip chip; - void __iomem *base; - struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; -}; -#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) - -static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) -{ - return readl(dwc->base + offset); -} - -static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offs= et) -{ - writel(value, dwc->base + offset); -} - -static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) -{ - u32 reg; - - reg =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm)); - - if (enabled) - reg |=3D DWC_TIM_CTRL_EN; - else - reg &=3D ~DWC_TIM_CTRL_EN; - - dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm)); -} - -static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, - struct pwm_device *pwm, - const struct pwm_state *state) -{ - u64 tmp; - u32 ctrl; - u32 high; - u32 low; - - /* - * Calculate width of low and high period in terms of input clock - * periods and check are the result within HW limits between 1 and - * 2^32 periods. - */ - tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); - if (tmp < 1 || tmp > (1ULL << 32)) - return -ERANGE; - low =3D tmp - 1; - - tmp =3D DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - DWC_CLK_PERIOD_NS); - if (tmp < 1 || tmp > (1ULL << 32)) - return -ERANGE; - high =3D tmp - 1; - - /* - * Specification says timer usage flow is to disable timer, then - * program it followed by enable. It also says Load Count is loaded - * into timer after it is enabled - either after a disable or - * a reset. Based on measurements it happens also without disable - * whenever Load Count is updated. But follow the specification. - */ - __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); - - /* - * Write Load Count and Load Count 2 registers. Former defines the - * width of low period and latter the width of high period in terms - * multiple of input clock periods: - * Width =3D ((Count + 1) * input clock period). - */ - dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm)); - dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm)); - - /* - * Set user-defined mode, timer reloads from Load Count registers - * when it counts down to 0. - * Set PWM mode, it makes output to toggle and width of low and high - * periods are set by Load Count registers. - */ - ctrl =3D DWC_TIM_CTRL_MODE_USER | DWC_TIM_CTRL_PWM; - dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm)); - - /* - * Enable timer. Output starts from low period. - */ - __dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled); - - return 0; -} - -static int dwc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, - const struct pwm_state *state) -{ - struct dwc_pwm *dwc =3D to_dwc_pwm(chip); - - if (state->polarity !=3D PWM_POLARITY_INVERSED) - return -EINVAL; - - if (state->enabled) { - if (!pwm->state.enabled) - pm_runtime_get_sync(chip->dev); - return __dwc_pwm_configure_timer(dwc, pwm, state); - } else { - if (pwm->state.enabled) { - __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); - pm_runtime_put_sync(chip->dev); - } - } - - return 0; -} - -static int dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, - struct pwm_state *state) -{ - struct dwc_pwm *dwc =3D to_dwc_pwm(chip); - u64 duty, period; - - pm_runtime_get_sync(chip->dev); - - state->enabled =3D !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); - - duty =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty +=3D 1; - duty *=3D DWC_CLK_PERIOD_NS; - state->duty_cycle =3D duty; - - period =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period +=3D 1; - period *=3D DWC_CLK_PERIOD_NS; - period +=3D duty; - state->period =3D period; - - state->polarity =3D PWM_POLARITY_INVERSED; - - pm_runtime_put_sync(chip->dev); - - return 0; -} - -static const struct pwm_ops dwc_pwm_ops =3D { - .apply =3D dwc_pwm_apply, - .get_state =3D dwc_pwm_get_state, - .owner =3D THIS_MODULE, -}; - -static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) -{ - struct dwc_pwm *dwc; - - dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); - if (!dwc) - return NULL; - - dwc->chip.dev =3D dev; - dwc->chip.ops =3D &dwc_pwm_ops; - dwc->chip.npwm =3D DWC_TIMERS_TOTAL; - - dev_set_drvdata(dev, dwc); - return dwc; -} +#include "pwm-dwc.h" =20 static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *= id) { diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h new file mode 100644 index 000000000000..56deab4e28ec --- /dev/null +++ b/drivers/pwm/pwm-dwc.h @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + */ + +MODULE_IMPORT_NS(dwc_pwm); + +#define DWC_TIM_LD_CNT(n) ((n) * 0x14) +#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) +#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) +#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) +#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) +#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) + +#define DWC_TIMERS_INT_STS 0xa0 +#define DWC_TIMERS_EOI 0xa4 +#define DWC_TIMERS_RAW_INT_STS 0xa8 +#define DWC_TIMERS_COMP_VERSION 0xac + +#define DWC_TIMERS_TOTAL 8 +#define DWC_CLK_PERIOD_NS 10 + +/* Timer Control Register */ +#define DWC_TIM_CTRL_EN BIT(0) +#define DWC_TIM_CTRL_MODE BIT(1) +#define DWC_TIM_CTRL_MODE_FREE (0 << 1) +#define DWC_TIM_CTRL_MODE_USER (1 << 1) +#define DWC_TIM_CTRL_INT_MASK BIT(2) +#define DWC_TIM_CTRL_PWM BIT(3) + +struct dwc_pwm_ctx { + u32 cnt; + u32 cnt2; + u32 ctrl; +}; + +struct dwc_pwm { + struct pwm_chip chip; + void __iomem *base; + struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; +}; +#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) + +static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) +{ + return readl(dwc->base + offset); +} + +static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offs= et) +{ + writel(value, dwc->base + offset); +} + +extern struct dwc_pwm *dwc_pwm_alloc(struct device *dev); --=20 2.40.1 From nobody Fri Dec 19 04:58:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68929EC8744 for ; Thu, 7 Sep 2023 16:46:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242585AbjIGQqr (ORCPT ); Thu, 7 Sep 2023 12:46:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242532AbjIGQqZ (ORCPT ); Thu, 7 Sep 2023 12:46:25 -0400 Received: from imap5.colo.codethink.co.uk (imap5.colo.codethink.co.uk [78.40.148.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EFC3211B; Thu, 7 Sep 2023 09:45:48 -0700 (PDT) Received: from [134.238.52.102] (helo=rainbowdash) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1qeHce-0052RG-DY; Thu, 07 Sep 2023 17:12:48 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1qeHcd-000HUv-2c; Thu, 07 Sep 2023 17:12:47 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha Subject: [PATCH v9 2/6] pwm: dwc: make timer clock configurable Date: Thu, 7 Sep 2023 17:12:38 +0100 Message-Id: <20230907161242.67190-3-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230907161242.67190-1-ben.dooks@codethink.co.uk> References: <20230907161242.67190-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a configurable clock base rate for the pwm as when being built for non-PCI the block may be sourced from an internal clock. Signed-off-by: Ben Dooks Reviewed-by: Uwe Kleine-K=C3=B6nig --- v9: - moved email to codethink from sifive v8: - add reviewed by, fixed issue with previous renames. v7: - remove the "struct clk *" clk field from dwc_pwm_ctx, not used here, v6: - removed DWC_CLK_PERIOD_NS as it is now not needed v4: - moved earlier before the of changes to make the of changes one patch v2: - removed the ifdef and merged the other clock patch in here --- drivers/pwm/pwm-dwc-core.c | 9 +++++---- drivers/pwm/pwm-dwc.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c index b693cb7fa812..4b4b7b9e1d82 100644 --- a/drivers/pwm/pwm-dwc-core.c +++ b/drivers/pwm/pwm-dwc-core.c @@ -49,13 +49,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dw= c, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); + tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low =3D tmp - 1; =20 tmp =3D DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - DWC_CLK_PERIOD_NS); + dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high =3D tmp - 1; @@ -130,12 +130,12 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, s= truct pwm_device *pwm, =20 duty =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); duty +=3D 1; - duty *=3D DWC_CLK_PERIOD_NS; + duty *=3D dwc->clk_ns; state->duty_cycle =3D duty; =20 period =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); period +=3D 1; - period *=3D DWC_CLK_PERIOD_NS; + period *=3D dwc->clk_ns; period +=3D duty; state->period =3D period; =20 @@ -160,6 +160,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; =20 + dwc->clk_ns =3D 10; dwc->chip.dev =3D dev; dwc->chip.ops =3D &dwc_pwm_ops; dwc->chip.npwm =3D DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index 56deab4e28ec..64795247c54c 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -24,7 +24,6 @@ MODULE_IMPORT_NS(dwc_pwm); #define DWC_TIMERS_COMP_VERSION 0xac =20 #define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 =20 /* Timer Control Register */ #define DWC_TIM_CTRL_EN BIT(0) @@ -43,6 +42,7 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; + unsigned int clk_ns; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) --=20 2.40.1 From nobody Fri Dec 19 04:58:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78555EC8758 for ; Thu, 7 Sep 2023 21:00:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239673AbjIGVAh (ORCPT ); Thu, 7 Sep 2023 17:00:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230091AbjIGVAe (ORCPT ); Thu, 7 Sep 2023 17:00:34 -0400 Received: from imap4.hz.codethink.co.uk (imap4.hz.codethink.co.uk [188.40.203.114]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50E751990 for ; Thu, 7 Sep 2023 14:00:31 -0700 (PDT) Received: from [134.238.52.102] (helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1qeHcf-004U1P-DW; Thu, 07 Sep 2023 17:12:49 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1qeHcd-000HUz-2h; Thu, 07 Sep 2023 17:12:47 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha Subject: [PATCH v9 3/6] pwm: dwc: add PWM bit unset in get_state call Date: Thu, 7 Sep 2023 17:12:39 +0100 Message-Id: <20230907161242.67190-4-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230907161242.67190-1-ben.dooks@codethink.co.uk> References: <20230907161242.67190-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks Reviewed-by: Uwe Kleine-K=C3=B6nig --- v9: - fixed multi-line comment - put authour back to codethink email from sifive v8: - fixed rename issues v4: - fixed review comment on mulit-line calculations --- drivers/pwm/pwm-dwc-core.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c index 4b4b7b9e1d82..3fc281a78c9a 100644 --- a/drivers/pwm/pwm-dwc-core.c +++ b/drivers/pwm/pwm-dwc-core.c @@ -122,24 +122,32 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, s= truct pwm_device *pwm, { struct dwc_pwm *dwc =3D to_dwc_pwm(chip); u64 duty, period; + u32 ctrl, ld, ld2; =20 pm_runtime_get_sync(chip->dev); =20 - state->enabled =3D !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); + ld =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + ld2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); =20 - duty =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty +=3D 1; - duty *=3D dwc->clk_ns; - state->duty_cycle =3D duty; + state->enabled =3D !!(ctrl & DWC_TIM_CTRL_EN); =20 - period =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period +=3D 1; - period *=3D dwc->clk_ns; - period +=3D duty; - state->period =3D period; + /* + * If we're not in PWM, technically the output is a 50-50 + * based on the timer load-count only. + */ + if (ctrl & DWC_TIM_CTRL_PWM) { + duty =3D (ld + 1) * dwc->clk_ns; + period =3D (ld2 + 1) * dwc->clk_ns; + period +=3D duty; + } else { + duty =3D (ld + 1) * dwc->clk_ns; + period =3D duty * 2; + } =20 state->polarity =3D PWM_POLARITY_INVERSED; + state->period =3D period; + state->duty_cycle =3D duty; =20 pm_runtime_put_sync(chip->dev); =20 --=20 2.40.1 From nobody Fri Dec 19 04:58:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C2B8EC8758 for ; Thu, 7 Sep 2023 21:00:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240542AbjIGVAk (ORCPT ); Thu, 7 Sep 2023 17:00:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230091AbjIGVAi (ORCPT ); Thu, 7 Sep 2023 17:00:38 -0400 Received: from imap4.hz.codethink.co.uk (imap4.hz.codethink.co.uk [188.40.203.114]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F2E81BCB for ; Thu, 7 Sep 2023 14:00:34 -0700 (PDT) Received: from [134.238.52.102] (helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1qeHcf-004U1Q-Gf; Thu, 07 Sep 2023 17:12:49 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1qeHcd-000HV4-2m; Thu, 07 Sep 2023 17:12:47 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha Subject: [PATCH v9 4/6] pwm: dwc: use clock rate in hz to avoid rounding issues Date: Thu, 7 Sep 2023 17:12:40 +0100 Message-Id: <20230907161242.67190-5-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230907161242.67190-1-ben.dooks@codethink.co.uk> References: <20230907161242.67190-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As noted, the clock-rate when not a nice multiple of ns is probably going to end up with inacurate calculations, as well as on a non pci system the rate may change (although we've not put a clock rate change notifier in this code yet) so we also add some quick checks of the rate when we do any calculations with it. Signed-off-by; Ben Dooks Reported-by: Uwe Kleine-K=C3=B6nig --- v9: - fixed commit spelling - changed to use codethink email instead of sifive v8: - fixup post rename - move to earlier in series --- drivers/pwm/pwm-dwc-core.c | 24 +++++++++++++++--------- drivers/pwm/pwm-dwc.h | 2 +- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c index 3fc281a78c9a..3b856685029d 100644 --- a/drivers/pwm/pwm-dwc-core.c +++ b/drivers/pwm/pwm-dwc-core.c @@ -49,13 +49,14 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dw= c, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); + tmp =3D state->duty_cycle * dwc->clk_rate; + tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low =3D tmp - 1; =20 - tmp =3D DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - dwc->clk_ns); + tmp =3D (state->period - state->duty_cycle) * dwc->clk_rate; + tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high =3D tmp - 1; @@ -121,11 +122,14 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, s= truct pwm_device *pwm, struct pwm_state *state) { struct dwc_pwm *dwc =3D to_dwc_pwm(chip); + unsigned long clk_rate; u64 duty, period; u32 ctrl, ld, ld2; =20 pm_runtime_get_sync(chip->dev); =20 + clk_rate =3D dwc->clk_rate; + ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); ld =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); ld2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); @@ -137,17 +141,19 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, s= truct pwm_device *pwm, * based on the timer load-count only. */ if (ctrl & DWC_TIM_CTRL_PWM) { - duty =3D (ld + 1) * dwc->clk_ns; - period =3D (ld2 + 1) * dwc->clk_ns; + duty =3D ld + 1; + period =3D ld2 + 1; period +=3D duty; } else { - duty =3D (ld + 1) * dwc->clk_ns; + duty =3D ld + 1; period =3D duty * 2; } =20 + duty *=3D NSEC_PER_SEC; + period *=3D NSEC_PER_SEC; + state->period =3D DIV_ROUND_CLOSEST_ULL(period, clk_rate); + state->duty_cycle =3D DIV_ROUND_CLOSEST_ULL(duty, clk_rate); state->polarity =3D PWM_POLARITY_INVERSED; - state->period =3D period; - state->duty_cycle =3D duty; =20 pm_runtime_put_sync(chip->dev); =20 @@ -168,7 +174,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; =20 - dwc->clk_ns =3D 10; + dwc->clk_rate =3D NSEC_PER_SEC / 10; dwc->chip.dev =3D dev; dwc->chip.ops =3D &dwc_pwm_ops; dwc->chip.npwm =3D DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index 64795247c54c..e0a940fd6e87 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -42,7 +42,7 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; - unsigned int clk_ns; + unsigned long clk_rate; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) --=20 2.40.1 From nobody Fri Dec 19 04:58:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7D18EC8758 for ; Thu, 7 Sep 2023 21:00:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240843AbjIGVAp (ORCPT ); Thu, 7 Sep 2023 17:00:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240869AbjIGVAm (ORCPT ); Thu, 7 Sep 2023 17:00:42 -0400 Received: from imap4.hz.codethink.co.uk (imap4.hz.codethink.co.uk [188.40.203.114]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C5001BE2 for ; Thu, 7 Sep 2023 14:00:37 -0700 (PDT) Received: from [134.238.52.102] (helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1qeHcf-004U1R-Ea; Thu, 07 Sep 2023 17:12:49 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1qeHcd-000HV9-2r; Thu, 07 Sep 2023 17:12:47 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha Subject: [PATCH v9 5/6] pwm: dwc: round rate divisions up Date: Thu, 7 Sep 2023 17:12:41 +0100 Message-Id: <20230907161242.67190-6-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230907161242.67190-1-ben.dooks@codethink.co.uk> References: <20230907161242.67190-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As suggested, round up the counter variables to ensure we always produce a longer period calculation. Reported-by: Uwe Kleine-K=C3=B6nig Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c index 3b856685029d..6358e3345210 100644 --- a/drivers/pwm/pwm-dwc-core.c +++ b/drivers/pwm/pwm-dwc-core.c @@ -50,13 +50,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dw= c, * 2^32 periods. */ tmp =3D state->duty_cycle * dwc->clk_rate; - tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); + tmp =3D DIV_ROUND_UP_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low =3D tmp - 1; =20 tmp =3D (state->period - state->duty_cycle) * dwc->clk_rate; - tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); + tmp =3D DIV_ROUND_UP_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high =3D tmp - 1; --=20 2.40.1 From nobody Fri Dec 19 04:58:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C9BEEC8758 for ; Thu, 7 Sep 2023 21:00:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238130AbjIGVAd (ORCPT ); Thu, 7 Sep 2023 17:00:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230091AbjIGVAc (ORCPT ); Thu, 7 Sep 2023 17:00:32 -0400 X-Greylist: delayed 8667 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Thu, 07 Sep 2023 14:00:28 PDT Received: from imap4.hz.codethink.co.uk (imap4.hz.codethink.co.uk [188.40.203.114]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 159B01BCD for ; Thu, 7 Sep 2023 14:00:27 -0700 (PDT) Received: from [134.238.52.102] (helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1qeHcf-004U1S-Fc; Thu, 07 Sep 2023 17:12:49 +0100 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1qeHcd-000HVE-2x; Thu, 07 Sep 2023 17:12:47 +0100 From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ben.dooks@codethink.co.uk, u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha Subject: [PATCH v9 6/6] pwm: dwc: add of/platform support Date: Thu, 7 Sep 2023 17:12:42 +0100 Message-Id: <20230907161242.67190-7-ben.dooks@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230907161242.67190-1-ben.dooks@codethink.co.uk> References: <20230907161242.67190-1-ben.dooks@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The dwc pwm controller can be used in non-PCI systems, so allow either platform or OF based probing. Signed-off-by: Ben Dooks --- v9: - add clk_rate_exclusive_get() to lock clock rate for now - fix email address from sifive to codethink - fix module namespace v8: - add compile test for of-case - add module namespace - move later in the series v7: - fixup kconfig from previous pcie changes v5: - fix missing " in kconfig - remove .remove method, devm already sorts this. - merge pwm-number code - split the of code out of the core - get bus clock v4: - moved the compile test code earlier - fixed review comments - used NS_PER_SEC - use devm_clk_get_enabled - ensure we get the bus clock v3: - changed compatible name --- drivers/pwm/Kconfig | 10 ++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-core.c | 6 +++ drivers/pwm/pwm-dwc-of.c | 93 ++++++++++++++++++++++++++++++++++++++ drivers/pwm/pwm-dwc.c | 1 + drivers/pwm/pwm-dwc.h | 1 + 6 files changed, 112 insertions(+) create mode 100644 drivers/pwm/pwm-dwc-of.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 507c8b8547a5..22d58cb334e7 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -205,6 +205,16 @@ config PWM_DWC To compile this driver as a module, choose M here: the module will be called pwm-dwc. =20 +config PWM_DWC_OF + tristate "DesignWare PWM Controller (OF bus)" + depends on HAS_IOMEM && (OF || COMPILE_TEST) + select PWM_DWC_CORE + help + PWM driver for Synopsys DWC PWM Controller on an OF bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-of. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c5ec9e168ee7..e3c867cb13d1 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PWM_CRC) +=3D pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) +=3D pwm-cros-ec.o obj-$(CONFIG_PWM_DWC_CORE) +=3D pwm-dwc-core.o obj-$(CONFIG_PWM_DWC) +=3D pwm-dwc.o +obj-$(CONFIG_PWM_DWC_OF) +=3D pwm-dwc-of.o obj-$(CONFIG_PWM_EP93XX) +=3D pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) +=3D pwm-fsl-ftm.o obj-$(CONFIG_PWM_HIBVT) +=3D pwm-hibvt.o diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c index 6358e3345210..8b4d96d655c7 100644 --- a/drivers/pwm/pwm-dwc-core.c +++ b/drivers/pwm/pwm-dwc-core.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include =20 @@ -44,6 +45,9 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, u32 high; u32 low; =20 + if (dwc->clk) + dwc->clk_rate =3D clk_get_rate(dwc->clk); + /* * Calculate width of low and high period in terms of input clock * periods and check are the result within HW limits between 1 and @@ -128,6 +132,8 @@ static int dwc_pwm_get_state(struct pwm_chip *chip, str= uct pwm_device *pwm, =20 pm_runtime_get_sync(chip->dev); =20 + if (dwc->clk) + dwc->clk_rate =3D clk_get_rate(dwc->clk); clk_rate =3D dwc->clk_rate; =20 ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c new file mode 100644 index 000000000000..30b860484895 --- /dev/null +++ b/drivers/pwm/pwm-dwc-of.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver OF + * + * Copyright (C) 2022 SiFive, Inc. + */ + +#define DEFAULT_MODULE_NAMESPACE dwc_pwm + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_plat_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct dwc_pwm *dwc; + struct clk *bus; + u32 nr_pwm; + int ret; + + dwc =3D dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + if (!device_property_read_u32(dev, "snps,pwm-number", &nr_pwm)) { + if (nr_pwm > DWC_TIMERS_TOTAL) + dev_err(dev, "too many PWMs (%d) specified, capping at %d\n", + nr_pwm, dwc->chip.npwm); + else + dwc->chip.npwm =3D nr_pwm; + } + + dwc->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dwc->base)) + return PTR_ERR(dwc->base); + + bus =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(bus)) + return dev_err_probe(dev, PTR_ERR(bus), + "failed to get clock\n"); + + dwc->clk =3D devm_clk_get_enabled(dev, "timer"); + if (IS_ERR(dwc->clk)) + return dev_err_probe(dev, PTR_ERR(dwc->clk), + "failed to get timer clock\n"); + + ret =3D clk_rate_exclusive_get(dwc->clk); + if (ret) + return dev_err_probe(dev, ret, + "clk_rate_exclusive_get() failed\n"); + + dwc->clk_rate =3D clk_get_rate(dwc->clk); + return devm_pwmchip_add(dev, &dwc->chip); +} + +static int dwc_pwm_plat_remove(struct platform_device *pdev) +{ + struct dwc_pwm *dwc =3D dev_get_drvdata(&pdev->dev); + + clk_rate_exclusive_put(dwc->clk); + return 0; +} + +static const struct of_device_id dwc_pwm_dt_ids[] =3D { + { .compatible =3D "snps,dw-apb-timers-pwm2" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc_pwm_dt_ids); + +static struct platform_driver dwc_pwm_plat_driver =3D { + .driver =3D { + .name =3D "dwc-pwm", + .of_match_table =3D dwc_pwm_dt_ids, + }, + .probe =3D dwc_pwm_plat_probe, + .remove =3D dwc_pwm_plat_remove, +}; + +module_platform_driver(dwc_pwm_plat_driver); + +MODULE_ALIAS("platform:dwc-pwm-of"); +MODULE_AUTHOR("Ben Dooks "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index bd9cadb497d7..7c32bd06ed33 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include =20 diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index e0a940fd6e87..18e98c2c07d7 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -42,6 +42,7 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; + struct clk *clk; unsigned long clk_rate; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; --=20 2.40.1