From nobody Fri Dec 19 11:31:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67D88EB8FB7 for ; Wed, 6 Sep 2023 11:25:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233670AbjIFLZE (ORCPT ); Wed, 6 Sep 2023 07:25:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239485AbjIFLY4 (ORCPT ); Wed, 6 Sep 2023 07:24:56 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF934E45; Wed, 6 Sep 2023 04:24:46 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 386BOfSv108071; Wed, 6 Sep 2023 06:24:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1693999481; bh=oh4VxtaVswsDjOouTdD+1CGQdGng1xuA9Igp4FLFmok=; h=From:To:Subject:Date:In-Reply-To:References; b=x4safwWN/56tmgBuUKn7NLDNzcX1etXZP2UBN5PytHkEVU9zileKMXOCfxCQgdIZo T2wQ5q1AB/MIgWEONbnO1UJdlLvzM0iw+wF7tgHhKdd7Lfqi4Nd1bw3FpR9sMUf7fd OsImDkWujFlMzrmR0wmMWXqdpC2piJU/herzA5RA= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 386BOfk9004354 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 6 Sep 2023 06:24:41 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 6 Sep 2023 06:24:41 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 6 Sep 2023 06:24:41 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 386BON7t099810; Wed, 6 Sep 2023 06:24:37 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Hari Nagalla , Udit Kumar Subject: [PATCH v4 4/9] arm64: dts : ti: k3-j721s2-som-p0: Add DDR carveout memory nodes for R5F Date: Wed, 6 Sep 2023 16:54:17 +0530 Message-ID: <20230906112422.2846151-5-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230906112422.2846151-1-a-nandan@ti.com> References: <20230906112422.2846151-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Two carveout reserved memory nodes each have been added for each of the R5F remote processor device within both the MCU and MAIN domains for the TI J721S2 EVM boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables either to allocate the memory for firmware memory segments. Note that the R5F1 carveouts are needed only if the R5F cluster is running in Split (non-LockStep) mode. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Hari Nagalla Signed-off-by: Apurva Nandan Reviewed-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 156 +++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index a4006f328027..970340ff2c0a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -29,6 +29,84 @@ secure_ddr: optee@9e800000 { alignment =3D <0x1000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a8000000 { + reg =3D <0x00 0xa8000000 0x00 0x01c00000>; + alignment =3D <0x1000>; + no-map; + }; }; =20 mux0: mux-controller { @@ -151,3 +229,81 @@ flash@0 { cdns,read-delay =3D <4>; }; }; + +&mailbox0_cluster0 { + status =3D "okay"; + interrupts =3D <436>; + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + interrupts =3D <432>; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + interrupts =3D <428>; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes =3D <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; + memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes =3D <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; + memory-region =3D <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes =3D <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; + memory-region =3D <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes =3D <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; + memory-region =3D <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; --=20 2.34.1