From nobody Thu Sep 11 16:57:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40925EB8FB5 for ; Wed, 6 Sep 2023 06:51:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241952AbjIFGv6 (ORCPT ); Wed, 6 Sep 2023 02:51:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239356AbjIFGvu (ORCPT ); Wed, 6 Sep 2023 02:51:50 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DDFAE45 for ; Tue, 5 Sep 2023 23:51:40 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id BF95C2C95; Wed, 6 Sep 2023 08:50:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1693983010; bh=2Z7qzyFxaoh4YnDIEa4VW1vDgXw1X//pkJQARYbq5dI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=wSUURFlmw/3+m2cyo8MGxyrkHMQePN2BRTZjm+edaEO1hfRPOQSKl+QEoJa6twlEn DGGMVW+P2XCZ8lMGOnRAhl+ghYnUQknngyJ8ADdIUXYRqLBFjVjyycMD7IrGMQje2T Jmnkk9BoZimWZFS6tvL533l/1qmCvOFZCk21GGOU= From: Tomi Valkeinen Date: Wed, 06 Sep 2023 09:50:57 +0300 Subject: [PATCH v4 10/12] drm/bridge: tc358768: Clean up clock period code MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-10-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6683; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=2Z7qzyFxaoh4YnDIEa4VW1vDgXw1X//pkJQARYbq5dI=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFrrcc2Vpe08+mRAIoe6WqypBDurOxmD+JQq FzkISQJEmmJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghawAKCRD6PaqMvJYe 9RKND/wLaBu8v0eT2tYwsTlUEivxqdsiobhWTRtXlHVv9t7z9kid6SRq9bQN0FHWpVuigbaktZl H6PLuaJWtk2Awbm5X0Po+VppJs00G8RO2jUB5CV1iM/T5gkSoI+vW7L/Y4j2bYtJDco6AVpqDu8 zoGQ0b+q98lfwQQoNQrSOp6mH/J1EPd/2ClBPtmOy97TJP1q5GEP1YotN/rautxjWrQPjT4odt3 VNBhVBri316K6VxW39+xgOv++KvT4U26dZd6TKDL7QHhQF40m9fVr+Qy+Ujs0dY8JaFxI4Foish vCl9LDfFyi5LRDPxVxv8biFqZUif9HKmwFhZyT7hDcyK8NDhbBFeklc6xG6lrgPucY8qPHXC+a2 syHHHAJIUf46Mt0qBQtcB6cpI6ZMr9+roe8azsc7DF8aZ6uYBja3n4tmwrkQOUHIyKPU1ddRilE 45NfPBX3E1IvSNeKu9BJ88Oso7cF8PCQ338m0KyQT7EotR5uoNx/sWjrFUvrknEEpx0UZOf7wwq MBX88R/zb886wy83Fm7oTI5WCKsxvdzbdzy1AUI5CkulfUZGxTfP0EHqI1l5oyawt+HIcbS4NIg m3b8KliQHi1RGAMNaqIT6f8LBV+tMJVPnEa3P7zJGimTRip+Dex542hxTFaGTq+SSdPJSOrshyY t7gWafM/Y9MyTXw== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The driver defines TC358768_PRECISION as 1000, and uses "nsk" to refer to clock periods. The original author does not remember where all this came from. Effectively the driver is using picoseconds as the unit for clock periods, yet referring to them by "nsk". Clean this up by just saying the periods are in picoseconds. Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 60 +++++++++++++++++++----------------= ---- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 0f117d673b14..9ce8d120b50c 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #include #include @@ -627,15 +628,14 @@ static int tc358768_setup_pll(struct tc358768_priv *p= riv, return tc358768_clear_error(priv); } =20 -#define TC358768_PRECISION 1000 -static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk) +static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) { - return (ns * TC358768_PRECISION + period_nsk) / period_nsk; + return (ns * 1000 + period_ps) / period_ps; } =20 -static u32 tc358768_to_ns(u32 nsk) +static u32 tc358768_ps_to_ns(u32 ps) { - return (nsk / TC358768_PRECISION); + return ps / 1000; } =20 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) @@ -646,7 +646,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) u32 val, val2, lptxcnt, hact, data_type; s32 raw_val; const struct drm_display_mode *mode; - u32 hsbyteclk_nsk, dsiclk_nsk, ui_nsk; + u32 hsbyteclk_ps, dsiclk_ps, ui_ps; u32 dsiclk, hsbyteclk, video_start; const u32 internal_delay =3D 40; int ret, i; @@ -730,67 +730,65 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); =20 /* DSI Timings */ - hsbyteclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, - hsbyteclk); - dsiclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); - ui_nsk =3D dsiclk_nsk / 2; - dev_dbg(dev, "dsiclk_nsk: %u\n", dsiclk_nsk); - dev_dbg(dev, "ui_nsk: %u\n", ui_nsk); - dev_dbg(dev, "hsbyteclk_nsk: %u\n", hsbyteclk_nsk); + hsbyteclk_ps =3D (u32)div_u64(PICO, hsbyteclk); + dsiclk_ps =3D (u32)div_u64(PICO, dsiclk); + ui_ps =3D dsiclk_ps / 2; + dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps, + ui_ps, hsbyteclk_ps); =20 /* LP11 > 100us for D-PHY Rx Init */ - val =3D tc358768_ns_to_cnt(100 * 1000, hsbyteclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1; dev_dbg(dev, "LINEINITCNT: %u\n", val); tc358768_write(priv, TC358768_LINEINITCNT, val); =20 /* LPTimeCnt > 50ns */ - val =3D tc358768_ns_to_cnt(50, hsbyteclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1; lptxcnt =3D val; dev_dbg(dev, "LPTXTIMECNT: %u\n", val); tc358768_write(priv, TC358768_LPTXTIMECNT, val); =20 /* 38ns < TCLK_PREPARE < 95ns */ - val =3D tc358768_ns_to_cnt(65, hsbyteclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1; dev_dbg(dev, "TCLK_PREPARECNT %u\n", val); /* TCLK_PREPARE + TCLK_ZERO > 300ns */ - val2 =3D tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), - hsbyteclk_nsk) - 2; + val2 =3D tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps), + hsbyteclk_ps) - 2; dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); =20 /* TCLK_TRAIL > 60ns AND TEOT <=3D 105 ns + 12*UI */ - raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), hsbyteclk= _nsk) - 5; + raw_val =3D tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbytec= lk_ps) - 5; val =3D clamp(raw_val, 0, 127); dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); =20 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ - val =3D 50 + tc358768_to_ns(4 * ui_nsk); - val =3D tc358768_ns_to_cnt(val, hsbyteclk_nsk) - 1; + val =3D 50 + tc358768_ps_to_ns(4 * ui_ps); + val =3D tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1; dev_dbg(dev, "THS_PREPARECNT %u\n", val); /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ - raw_val =3D tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), hsbytecl= k_nsk) - 10; + raw_val =3D tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyte= clk_ps) - 10; val2 =3D clamp(raw_val, 0, 127); dev_dbg(dev, "THS_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_THS_HEADERCNT, val); =20 /* TWAKEUP > 1ms in lptxcnt steps */ - val =3D tc358768_ns_to_cnt(1020000, hsbyteclk_nsk); + val =3D tc358768_ns_to_cnt(1020000, hsbyteclk_ps); val =3D val / (lptxcnt + 1) - 1; dev_dbg(dev, "TWAKEUP: %u\n", val); tc358768_write(priv, TC358768_TWAKEUP, val); =20 /* TCLK_POSTCNT > 60ns + 52*UI */ - val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), - hsbyteclk_nsk) - 3; + val =3D tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps), + hsbyteclk_ps) - 3; dev_dbg(dev, "TCLK_POSTCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_POSTCNT, val); =20 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ - raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk), - hsbyteclk_nsk) - 4; + raw_val =3D tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps), + hsbyteclk_ps) - 4; val =3D clamp(raw_val, 0, 15); dev_dbg(dev, "THS_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_THS_TRAILCNT, val); @@ -804,11 +802,11 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); =20 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ - val =3D tc358768_to_ns((lptxcnt + 1) * hsbyteclk_nsk * 4); - val =3D tc358768_ns_to_cnt(val, hsbyteclk_nsk) / 4 - 1; + val =3D tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4); + val =3D tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1; dev_dbg(dev, "TXTAGOCNT: %u\n", val); - val2 =3D tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * hsbyteclk_nsk), - hsbyteclk_nsk) - 2; + val2 =3D tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_p= s), + hsbyteclk_ps) - 2; dev_dbg(dev, "RXTASURECNT: %u\n", val2); val =3D val << 16 | val2; tc358768_write(priv, TC358768_BTACNTRL1, val); --=20 2.34.1