From nobody Thu Sep 11 16:57:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1ACCBEB8FAD for ; Wed, 6 Sep 2023 06:51:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239813AbjIFGvk (ORCPT ); Wed, 6 Sep 2023 02:51:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233602AbjIFGvd (ORCPT ); Wed, 6 Sep 2023 02:51:33 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91730E43 for ; Tue, 5 Sep 2023 23:51:29 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 159893F1; Wed, 6 Sep 2023 08:49:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1693983000; bh=9+YwYctXLvEJs60zHSY6wyocIempjTo8N/jz3tZYYWs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CxVNxPU10s7DOQfefseCeLnJm0SCXvAjr3ovcET/0Zh2SIq6xdpO17VynY9LdDbCu W2rK2DwkCwffnVhnlp0L6sAUoXLrY5utWGBd5mNxeOmdeQmOODjErufYsH8QwoCPkJ 3d1ihI/TdxyViHY+dSKOSluLfLstYNbombmvfPKM= From: Tomi Valkeinen Date: Wed, 06 Sep 2023 09:50:48 +0300 Subject: [PATCH v4 01/12] drm/tegra: rgb: Parameterize V- and H-sync polarities MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-1-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Thierry Reding , Thierry Reding , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2023; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=5+8Qt0dRuDZPu87i9IUGZHmIGywuwwho4mCUeHWUimE=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFo42NyY3wZOfzyAaJpXzsTa8M/eIixjIMdf P0mGzr/tDeJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghaAAKCRD6PaqMvJYe 9eGcD/98GTtyDMsinnUuVZ0ttkVS66umqHonmBjmpb9xvv2Ssu5eGmbc5OCNcrkvNqeS/+M16Cp fRwUjK3o1H6oKYsEJ6Z7J2/d1CYd1t0wZTDdRIPylE6zWRhT3oOOsbcANVH1k3xg+0gVu7Pla+c 5tZzEFHKn9zRGMfpdZ8YVohQEU6VyMA5N9CNfZDl5vsGcz4a7HvXRdvtRvsKyrHI4xJv19c8WvV B9bxI9tcFl2/xJbriJIIdnt3oeIildyiG4IV+LOM1docg0EvykYFVMUYVfG51pDGTjzxPfF0M6z KQkJulnX9qbW7Qpi/NQzMugLvO9aqSX4sCCkghwjvIdb/pUQbDPuCfL4IVYbNS3FjhrM9U91Lqm 4ZoXeK/bXkOKKrTVTxdNWRKxGVJf6zNrKXDY3lC3y6yjRxa0343Z+GbiqlDAPoEav4lvfksmPd0 FerZv0sWtjQENxJHB3VNGfngtNzGyG/g/8Vx4mXEI67Ai6cfXpnNyvK34gTETP4A5Rwl549MVdU tZNpUi2RQeBnN/osasFp+UZwDjNYjnvK9YOfMMgdfPbBz2fJnVoYz43H8qRbehJGKgSyEWw60yj cbtTG3zGIubB2LzUDFI/TpgW9k2pMU/tYikmalRft/biRwJFZlt4Sg6r5P06qpfIqc/MPOnRzor jMcK1CbHPBt/8mQ== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thierry Reding The polarities of the V- and H-sync signals are encoded as flags in the display mode, so use the existing information to setup the signals for the RGB interface. Signed-off-by: Thierry Reding Cc: Thierry Reding [tomi.valkeinen@ideasonboard.com: default to positive sync] Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/tegra/rgb.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c index 79566c9ea8ff..fc66bbd913b2 100644 --- a/drivers/gpu/drm/tegra/rgb.c +++ b/drivers/gpu/drm/tegra/rgb.c @@ -99,6 +99,7 @@ static void tegra_rgb_encoder_disable(struct drm_encoder = *encoder) =20 static void tegra_rgb_encoder_enable(struct drm_encoder *encoder) { + struct drm_display_mode *mode =3D &encoder->crtc->state->adjusted_mode; struct tegra_output *output =3D encoder_to_output(encoder); struct tegra_rgb *rgb =3D to_rgb(output); u32 value; @@ -108,10 +109,19 @@ static void tegra_rgb_encoder_enable(struct drm_encod= er *encoder) value =3D DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); =20 - /* XXX: parameterize? */ + /* configure H- and V-sync signal polarities */ value =3D tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); - value &=3D ~LVS_OUTPUT_POLARITY_LOW; - value &=3D ~LHS_OUTPUT_POLARITY_LOW; + + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + value |=3D LHS_OUTPUT_POLARITY_LOW; + else + value &=3D ~LHS_OUTPUT_POLARITY_LOW; + + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + value |=3D LVS_OUTPUT_POLARITY_LOW; + else + value &=3D ~LVS_OUTPUT_POLARITY_LOW; + tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); =20 /* XXX: parameterize? */ --=20 2.34.1