From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1ACCBEB8FAD for ; Wed, 6 Sep 2023 06:51:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239813AbjIFGvk (ORCPT ); Wed, 6 Sep 2023 02:51:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233602AbjIFGvd (ORCPT ); Wed, 6 Sep 2023 02:51:33 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91730E43 for ; Tue, 5 Sep 2023 23:51:29 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 159893F1; Wed, 6 Sep 2023 08:49:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1693983000; bh=9+YwYctXLvEJs60zHSY6wyocIempjTo8N/jz3tZYYWs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CxVNxPU10s7DOQfefseCeLnJm0SCXvAjr3ovcET/0Zh2SIq6xdpO17VynY9LdDbCu W2rK2DwkCwffnVhnlp0L6sAUoXLrY5utWGBd5mNxeOmdeQmOODjErufYsH8QwoCPkJ 3d1ihI/TdxyViHY+dSKOSluLfLstYNbombmvfPKM= From: Tomi Valkeinen Date: Wed, 06 Sep 2023 09:50:48 +0300 Subject: [PATCH v4 01/12] drm/tegra: rgb: Parameterize V- and H-sync polarities MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-1-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Thierry Reding , Thierry Reding , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2023; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=5+8Qt0dRuDZPu87i9IUGZHmIGywuwwho4mCUeHWUimE=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFo42NyY3wZOfzyAaJpXzsTa8M/eIixjIMdf P0mGzr/tDeJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghaAAKCRD6PaqMvJYe 9eGcD/98GTtyDMsinnUuVZ0ttkVS66umqHonmBjmpb9xvv2Ssu5eGmbc5OCNcrkvNqeS/+M16Cp fRwUjK3o1H6oKYsEJ6Z7J2/d1CYd1t0wZTDdRIPylE6zWRhT3oOOsbcANVH1k3xg+0gVu7Pla+c 5tZzEFHKn9zRGMfpdZ8YVohQEU6VyMA5N9CNfZDl5vsGcz4a7HvXRdvtRvsKyrHI4xJv19c8WvV B9bxI9tcFl2/xJbriJIIdnt3oeIildyiG4IV+LOM1docg0EvykYFVMUYVfG51pDGTjzxPfF0M6z KQkJulnX9qbW7Qpi/NQzMugLvO9aqSX4sCCkghwjvIdb/pUQbDPuCfL4IVYbNS3FjhrM9U91Lqm 4ZoXeK/bXkOKKrTVTxdNWRKxGVJf6zNrKXDY3lC3y6yjRxa0343Z+GbiqlDAPoEav4lvfksmPd0 FerZv0sWtjQENxJHB3VNGfngtNzGyG/g/8Vx4mXEI67Ai6cfXpnNyvK34gTETP4A5Rwl549MVdU tZNpUi2RQeBnN/osasFp+UZwDjNYjnvK9YOfMMgdfPbBz2fJnVoYz43H8qRbehJGKgSyEWw60yj cbtTG3zGIubB2LzUDFI/TpgW9k2pMU/tYikmalRft/biRwJFZlt4Sg6r5P06qpfIqc/MPOnRzor jMcK1CbHPBt/8mQ== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thierry Reding The polarities of the V- and H-sync signals are encoded as flags in the display mode, so use the existing information to setup the signals for the RGB interface. Signed-off-by: Thierry Reding Cc: Thierry Reding [tomi.valkeinen@ideasonboard.com: default to positive sync] Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/tegra/rgb.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c index 79566c9ea8ff..fc66bbd913b2 100644 --- a/drivers/gpu/drm/tegra/rgb.c +++ b/drivers/gpu/drm/tegra/rgb.c @@ -99,6 +99,7 @@ static void tegra_rgb_encoder_disable(struct drm_encoder = *encoder) =20 static void tegra_rgb_encoder_enable(struct drm_encoder *encoder) { + struct drm_display_mode *mode =3D &encoder->crtc->state->adjusted_mode; struct tegra_output *output =3D encoder_to_output(encoder); struct tegra_rgb *rgb =3D to_rgb(output); u32 value; @@ -108,10 +109,19 @@ static void tegra_rgb_encoder_enable(struct drm_encod= er *encoder) value =3D DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); =20 - /* XXX: parameterize? */ + /* configure H- and V-sync signal polarities */ value =3D tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); - value &=3D ~LVS_OUTPUT_POLARITY_LOW; - value &=3D ~LHS_OUTPUT_POLARITY_LOW; + + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + value |=3D LHS_OUTPUT_POLARITY_LOW; + else + value &=3D ~LHS_OUTPUT_POLARITY_LOW; + + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + value |=3D LVS_OUTPUT_POLARITY_LOW; + else + value &=3D ~LVS_OUTPUT_POLARITY_LOW; + tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); =20 /* XXX: parameterize? */ --=20 2.34.1 From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AFC3EB8FAD for ; Wed, 6 Sep 2023 06:51:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238122AbjIFGvi (ORCPT ); Wed, 6 Sep 2023 02:51:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233907AbjIFGvd (ORCPT ); Wed, 6 Sep 2023 02:51:33 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80FE5CC3 for ; Tue, 5 Sep 2023 23:51:30 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 5FBEAAF2; Wed, 6 Sep 2023 08:50:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1693983001; bh=qS07ZSZddPWPdiZH9fcpYilEFQ7vrO8rgSwkUV6v1C4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=BRHm+MzZM8dWxp6Kt9hY+Wal+sIydjNzQNiOBW7kbZj0axTIPQyL8VnDx2jDlTdKE +/55cDkb4BuM/0085HdPw7K1dRGghtLrLfQT+Bnx35olozoiFRvSf26reiHIm/rozW FlYYMWxbZEsI1xNhJQPPapU27ZqU3hH1Jsh6+C10= From: Tomi Valkeinen Date: Wed, 06 Sep 2023 09:50:49 +0300 Subject: [PATCH v4 02/12] drm/bridge: tc358768: Fix use of uninitialized variable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-2-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1089; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=qS07ZSZddPWPdiZH9fcpYilEFQ7vrO8rgSwkUV6v1C4=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFoTfjmUZzbLnnjzjkFwA1cnTmgbRcNHOwM6 Uu3TcmQkAyJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghaAAKCRD6PaqMvJYe 9T1SD/9YrG8U5MqiLWkIIq9qTEm1e7ERrvN+fj2RT0jmPHZ3lkkEXiN4OkkQC3AaS06iav8ZlKk GIfrAbTnQHxxMIxCmwUfy4mhrgXxKGEADI4Q8UXvQFVMyJkZSsBXPmMo2mQNXYU+rBKzJB0h5it t64fqXlCYPA5KCamfmxVzPmRGVbkKIBdS7c0cejGrsygK59H3B4toUDTZGHQRbHXavdaZnNk0Jk /hoTSrxn1HAQ/q+3rvvL2dJVlZtkmPycSjPRpHJhLfBOqNAnWM5d8Vdr7ZYLGQ6XJeR6BpK3wYt 7IFrAfXYduTM+BXzbjAgUrydOFW3oNIEp9p1luz9si6TlldEWWSP9BYK/GYgxbZVHf3YHj0+7zV gOjwUYBitNNlWtgVLMLGG3jZi47DO7FB6Elt6PvK7QWon60gS0lVvqo342ErFptg5PW+NLQoDCj u3DNqbI5UnHMRWMAvTUaczINGq6kqJ3SOkPNf6BqaxyRibWHCjGWoPNk8z/XjkfCPjQAs5pdXUw A2GENeX+WkBxdKl0OkIgtpO7159bFYDPoTPJY7xY48ALs0A4u/g3FAAbCVJ+TauCke/ffvHp4+6 dgXBGvn06Ab+o/TzmesHcK1VvnPxXarLMVNo6JLFw1J6EfrTTTWfplH9PyRMysGju2bS0ODMcNB Fy/hee+vUbChLZg== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org smatch reports: drivers/gpu/drm/bridge/tc358768.c:223 tc358768_update_bits() error: uniniti= alized symbol 'orig'. Fix this by bailing out from tc358768_update_bits() if the tc358768_read() produces an error. Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 819a4b6ec2a0..bc97a837955b 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -216,6 +216,10 @@ static void tc358768_update_bits(struct tc358768_priv = *priv, u32 reg, u32 mask, u32 tmp, orig; =20 tc358768_read(priv, reg, &orig); + + if (priv->error) + return; + tmp =3D orig & ~mask; tmp |=3D val & mask; if (tmp !=3D orig) --=20 2.34.1 From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B2A1EB8FB5 for ; Wed, 6 Sep 2023 06:51:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239779AbjIFGvn (ORCPT ); Wed, 6 Sep 2023 02:51:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237509AbjIFGvf (ORCPT ); Wed, 6 Sep 2023 02:51:35 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66AE2CF7 for ; Tue, 5 Sep 2023 23:51:32 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 89632DE2; Wed, 6 Sep 2023 08:50:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1693983002; bh=0xduDbqnx0tQ7Ml5WdtnYLM59pTP/iuxx2arAhXTDzM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nQTQh3KzO7HOwu2N4d3HjQZ3skRySbR4G/SwW++A/hdTM1Kn5uzLJPXGMZrKR6F7o IET6THfR+JnCLYjBLJuRCNFd+i0jOi1BIyWmtwfN4NoEGf4d/YxKlo+EPOuXo3GzjS 76YlRRc/ZY5XmnYayfmJDWAZrYDrWIRG1ZPZj+SI= From: Tomi Valkeinen Date: Wed, 06 Sep 2023 09:50:50 +0300 Subject: [PATCH v4 03/12] drm/bridge: tc358768: Default to positive h/v syncs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-3-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1765; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=0xduDbqnx0tQ7Ml5WdtnYLM59pTP/iuxx2arAhXTDzM=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFokCXbfJdHZDvl9tf6vIEwA2FzslAGoBKPp Oc1K6xGmLaJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghaAAKCRD6PaqMvJYe 9T5/EACdhK6JQxfvpEuxJvCJUGMLGH0HmTkskjXKOHSu8GP+jWWaX6Wej7OL3lseP+mgwsZ1rdF czvSpl6T/wz4jsi33q/DulRFdRhRBoWZC9aHb04aVly0Bw56yacSLTopc5IxhAg3WRELRIp/cG9 d3DUSZqmM/mUK06NA3NJBA3DtTpjP1/YLTx8mJZSayb8PO+4twOup9j0KcLMnxgquPQazCZ6+qU uXbkVKsbV63W9bN90wKsi41j4GodGZBFKo99CPkNrnjcdmd3RZlGD/Pb69dHxiomrvqusgXgeXG smef56FS8G64Wj1pkiuKtGMyAD44dXH3u9tsR6hc6egs0DSX6pTmbp9U/XwLMH874UIaDLFxFAe FPII5ZCB6Xi6CVIdbzkQU74vRa1g8YHmWihp10IXFOAbZhPCvb4JMHBsSc9czzaDnTfEO67c7QY vM1kBkoooBGaLhrhMUpX2XWyud3zr0lH2ozTR2s0lVwYhwuZ0ACVT0ud83MUsu49zN4LDsHFnBO NA2qzL/2UiE3vBNIwlcATcptVccoquc1hsicBIFlkC55Afxag8b4rhF3y3/ekmsLRIq9OTjVaHC zTobQgqB4s6kTNfi4xxRU0cXg/kCilnvcZ8hNNKok3mRG2DdFLOD+CTKHSePuWA0ildpvr+pueM t2NpBxft2oi3W5Q== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As the TC358768 is a DPI to DSI bridge, the DSI side does not need to define h/v sync polarities. This means that sometimes we have a mode without defined sync polarities, which does not work on the DPI side. Add a mode_fixup hook to default to positive sync polarities. Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index bc97a837955b..963ac550509b 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -963,9 +963,27 @@ tc358768_atomic_get_input_bus_fmts(struct drm_bridge *= bridge, return input_fmts; } =20 +static bool tc358768_mode_fixup(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + /* Default to positive sync */ + + if (!(adjusted_mode->flags & + (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) + adjusted_mode->flags |=3D DRM_MODE_FLAG_PHSYNC; + + if (!(adjusted_mode->flags & + (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) + adjusted_mode->flags |=3D DRM_MODE_FLAG_PVSYNC; + + return true; +} + static const struct drm_bridge_funcs tc358768_bridge_funcs =3D { .attach =3D tc358768_bridge_attach, .mode_valid =3D tc358768_bridge_mode_valid, + .mode_fixup =3D tc358768_mode_fixup, .pre_enable =3D tc358768_bridge_pre_enable, .enable =3D tc358768_bridge_enable, .disable =3D tc358768_bridge_disable, --=20 2.34.1 From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95091EB8FAD for ; Wed, 6 Sep 2023 06:51:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241861AbjIFGvr (ORCPT ); Wed, 6 Sep 2023 02:51:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237542AbjIFGvf (ORCPT ); Wed, 6 Sep 2023 02:51:35 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63C1FCC3 for ; Tue, 5 Sep 2023 23:51:32 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id B5C7C10FC; Wed, 6 Sep 2023 08:50:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1693983003; bh=eXYrSM7ApA2MbVOUtXFJ2obroG8H/iokUFgcNEvT5zg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=rJuCV/RxcYAYic9CyTl6ELDJNb2jJGrhKvWr4FiZabIIj5TC2NiePMxCOZSkoyyBi TQL6146GzsgPbCKhVkIgu0luuWEnia6jaj8pQpFr0AQX8aYIVT8oLX2NgJpCWdK6xz lfoubA4LJndpeglekfgADQGFCyRNMdfLxU79rIsg= From: Tomi Valkeinen Date: Wed, 06 Sep 2023 09:50:51 +0300 Subject: [PATCH v4 04/12] drm/bridge: tc358768: Fix bit updates MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-4-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2146; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=eXYrSM7ApA2MbVOUtXFJ2obroG8H/iokUFgcNEvT5zg=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFpVVmAbU8LCF1vT/Tlh+9yQWh9BrxwgFrl2 ZRjo+V4nZSJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghaQAKCRD6PaqMvJYe 9Z8YEACpJPXt7noW0NY1sBaNG85kH6iMKb7sEOfxUuRnD4Y3b4KHDkC/DKmUYyL8PMuJvu2gVBz 3cG6zO/A0hPAAhYmWoG+gmc4QwXvFdEi9Q9VwD8Z+pqYupzadMI5lqcqLsWv/ZT7NUusDfhtkNg wAJee2fMjQ2XISA5ZG0q2F3gGIlrO/mgMoQGJN09CV4ZV5K7/kUHdFDFNJaa7SHAm2Ps+4yzfAD wwuNAahNqqLReI5KgmZHRTaK74q3Re/LflJLXLOoaPTImoUxTMat+74MDoyUaueA8ZwPPT7YsFC 9tqLv+tZHLRr3EvEMV3NOyUD8x7L82VXdBZ0agMKNjB8N+zLJlxNtazNO2BT3wLdHjigeQIv+ue FxAihvdDtjwJ83rscXJbkIieAvFMIuRVdr8jDQ7A7rz0We0QO/vnyCCY7oxAc7E/PMraO0ayZF4 aclez97YOJmSIcqQqpNMbULj+uy8adGQCfpVawuUFNfwcjdW+JC3Pz9GSg5hoB8KCbDxIPdpHmH /LiYUOvgz2NYY9WKUcuflVdvuaIc7lci7WHqYgmC+QZQc/S9Zz44toH1SRoCfsBflsCjUWUGn3h Alo/9T/dpxO+jd9HgIsoZpSdHRRxQgftBBquYjXG+fn+2Zt6WkzUaW1jCxzUQLr+pA0ApV3Jqlj dn0mbpyWdwy3NnQ== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The driver has a few places where it does: if (thing_is_enabled_in_config) update_thing_bit_in_hw() This means that if the thing is _not_ enabled, the bit never gets cleared. This affects the h/vsyncs and continuous DSI clock bits. Fix the driver to always update the bit. Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 963ac550509b..99992af23f1e 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -794,8 +794,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) val |=3D BIT(i + 1); tc358768_write(priv, TC358768_HSTXVREGEN, val); =20 - if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) - tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); + tc358768_write(priv, TC358768_TXOPTIONCNTRL, + (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); =20 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ val =3D tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); @@ -861,11 +861,12 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) tc358768_write(priv, TC358768_DSI_HACT, hact); =20 /* VSYNC polarity */ - if (!(mode->flags & DRM_MODE_FLAG_NVSYNC)) - tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5)); + tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), + (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0); + /* HSYNC polarity */ - if (mode->flags & DRM_MODE_FLAG_PHSYNC) - tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0)); + tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), + (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0); =20 /* Start DSI Tx */ tc358768_write(priv, TC358768_DSI_START, 0x1); --=20 2.34.1 From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 553E6EB8FAD for ; Wed, 6 Sep 2023 06:51:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242011AbjIFGvt (ORCPT ); Wed, 6 Sep 2023 02:51:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232476AbjIFGvi (ORCPT ); Wed, 6 Sep 2023 02:51:38 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 657A2CFD for ; Tue, 5 Sep 2023 23:51:34 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id E027B1536; Wed, 6 Sep 2023 08:50:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1693983004; bh=gVqp/W0PhAL3EfV0HWVnGx4la8fAeaMt695Id26ctC0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZqWL8vcWUJ54WZyBnEOpvlsnUT9NYMiKpxMKcn2fRw+cRe452ESJg0oDFj6Q8T8lQ 1UZ8maNKagsPaPkCtBi9IWzkhX6fpBHcNPRRGb0SlpSdtHMkLxLnTBzMe1hHJ4pixO SrtmD5DCL4rFScikjWUbDlXQ89oAaJtTdAJJRnqI= From: Tomi Valkeinen Date: Wed, 06 Sep 2023 09:50:52 +0300 Subject: [PATCH v4 05/12] drm/bridge: tc358768: Cleanup PLL calculations MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-5-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2667; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=gVqp/W0PhAL3EfV0HWVnGx4la8fAeaMt695Id26ctC0=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFpw0pd36D5QvJBKTIrRBV5DNBSNUhtjPX4A 5Ra+O/VzDWJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghaQAKCRD6PaqMvJYe 9cpuD/4jv7eE215j4bbCAgkKOSK3MWMPvLJLxRjm8grHLGJ802Am7k9IuOAzjlT5i9w/AKcnLBT TuKpbOxEq3yGUlsnSQcBrU7VHZ58/ms6+pprEtCulfsJJwjyXQw1iF7+73zM2ZUGiKKxJ6TgxYX lBykvraNR0RPlx6niNhxpwF+TS/w7rStyPDmxFj4wDKqW5CCqUq3KrmvRmlDyCHGoE49xToZI6Q 1kBi4bHY9IsZhlXdlfvPDRQ+aWA3CNqlrqfa26O2lcmbmzPNQp8cJJiDKRvfkhtcVZ6ZyP9gw7x 5Axu5xI9Xt4jMLQ4fMZKIfNATLa/2OVl8gePkMjCi4cD//Mit+Ecwadb8llgyX0L7yfDmXOze+i mgbGrPuxhFmMLgE9DgiTDVwfQVc6+ttk07FWg1AhQ8SI/9U0J+MSRMbUtCW3OcYg10RmfH62Pwf HSbf/c4vBpB9Td5BvcAnVmfQlFfpseM93uq68pzhg0Pe+3MlsNN1fowoxfHs1NWAvIbSfbBF1iN /9G8HuDPrEv3kw2rwyOGHVHwmnKSjgwIQazA5zDozfpbW9r9+C4cVkZ9+gJJA1VVtU9p/XHzI8c nZa/CaK8mxeCJJgU5wym3mRmkPrrB3meyQJFdcKlzvjH2OwJGGTM9KATuIogQS7Pu2Q/eHS/P+b dy5rZI1WltfStSg== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As is quite common, some of TC358768's PLL register fields are to be programmed with (value - 1). Specifically, the FBD and PRD, multiplier and divider, are such fields. However, what the driver currently does is that it considers that the formula used for PLL rate calculation is: RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] where FBD and PRD are values directly from the registers, while a more sensible way to look at it is: RefClk * FBD / PRD * (1 / (2^FRS)) and when the FBD and PRD values are written to the registers, they will be subtracted by one. Change the driver accordingly, as it simplifies the PLL code. Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 99992af23f1e..a465674f1e2e 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -316,7 +316,7 @@ static int tc358768_calc_pll(struct tc358768_priv *priv, =20 target_pll =3D tc358768_pclk_to_pll(priv, mode->clock * 1000); =20 - /* pll_clk =3D RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */ + /* pll_clk =3D RefClk * FBD / PRD * (1 / (2^FRS)) */ =20 for (i =3D 0; i < ARRAY_SIZE(frs_limits); i++) if (target_pll >=3D frs_limits[i]) @@ -336,19 +336,19 @@ static int tc358768_calc_pll(struct tc358768_priv *pr= iv, best_prd =3D 0; best_fbd =3D 0; =20 - for (prd =3D 0; prd < 16; ++prd) { - u32 divisor =3D (prd + 1) * (1 << frs); + for (prd =3D 1; prd <=3D 16; ++prd) { + u32 divisor =3D prd * (1 << frs); u32 fbd; =20 - for (fbd =3D 0; fbd < 512; ++fbd) { + for (fbd =3D 1; fbd <=3D 512; ++fbd) { u32 pll, diff, pll_in; =20 - pll =3D (u32)div_u64((u64)refclk * (fbd + 1), divisor); + pll =3D (u32)div_u64((u64)refclk * fbd, divisor); =20 if (pll >=3D max_pll || pll < min_pll) continue; =20 - pll_in =3D (u32)div_u64((u64)refclk, prd + 1); + pll_in =3D (u32)div_u64((u64)refclk, prd); if (pll_in < 4000000) continue; =20 @@ -611,7 +611,7 @@ static int tc358768_setup_pll(struct tc358768_priv *pri= v, mode->clock * 1000); =20 /* PRD[15:12] FBD[8:0] */ - tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd); + tc358768_write(priv, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1)); =20 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ tc358768_write(priv, TC358768_PLLCTL1, --=20 2.34.1 From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29CF6EB8FAD for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-6-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4918; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=0EfCziQEtPenXwyT1aCWHhnZx/9dexcT0cb02lmSlQ8=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFpdH13kZ3Wf268UMnIvO0bawwfhCfufAhBD vsl4N4ZIP2JAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghaQAKCRD6PaqMvJYe 9SN7EACdAE5aR2Auv41Qn6lTE5jPJYA8cPXorWaA0rjhXibrJNsEger62b/PA7lOYacpOmBHhBA SdR3wjZx4vuE19TCMRQ+XD4HWFDoqfCKMQ1dFiDxTu67dx2B3iwcKH+zCu3KGIYW6CaUHhSj/Ck THwyAkXjgvo2p84Yt1ioJP/cRgZkYq7sNWVPTh2iqHMwM63Pu7m/fOQQ9RpQK7nMY+bt7lz73Ux 2p73lBVin45wgmsMYInFok1SbGS3PN9vESs9+EtVBvG7WsiGVi0y+Wdqxfk2FJx2ll7OHF8DOE5 +pB/+B+oizIEwk9OwV+TmR3dm2X29v2LN71DT3IFdTb2gFYD5CKnuZzno9rdlJ+VM3qkRvc/+pS STt9qG+iq2SOHoEZg0s7Ib5uSJB0JWEeVMe/zvzW9uhJtrFrElwwdZvcDAP4CbrQPOzxOMHwE3J VgKAMj+SKT8yEHpN9j0FqZ5lQvFAapBSoWgMgFiGvVfqrk8Zg+0/3GEepH0GrpX9tNlUgLd/i7i /vzLDzQk9qTOqDmFQWeHZM3BcIjpw1EhGARC3e/F8w3ySeHoLCK8OUxdyN6OAEhNQ8Og+OVP//h lKeLekUdFHyG9N9EXCArCPhtlPNdeJw2CKwxhRL1IEFiwoH37dvEI42NRmcpl7tU5eUjP3Hwock +8WbGMKGfvVcffQ== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The TC358768 documentation uses HFP, HBP, etc. values to deal with the video mode, while the driver currently uses the DRM display mode (htotal, hsync_start, etc). Change the driver to convert the DRM display mode to struct videomode, which then allows us to use the same units the documentation uses. This makes it much easier to work on the code when using the TC358768 documentation as a reference. Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 45 +++++++++++++++++++++--------------= ---- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index a465674f1e2e..b98c517c4726 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -650,6 +650,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) u32 dsiclk, dsibclk, video_start; const u32 internal_delay =3D 40; int ret, i; + struct videomode vm; =20 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling bac= k to continuous\n"); @@ -673,6 +674,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) return; } =20 + drm_display_mode_to_videomode(mode, &vm); + dsiclk =3D priv->dsiclk; dsibclk =3D dsiclk / 4; =20 @@ -681,28 +684,28 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) switch (dsi_dev->format) { case MIPI_DSI_FMT_RGB888: val |=3D (0x3 << 4); - hact =3D mode->hdisplay * 3; - video_start =3D (mode->htotal - mode->hsync_start) * 3; + hact =3D vm.hactive * 3; + video_start =3D (vm.hsync_len + vm.hback_porch) * 3; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_24; break; case MIPI_DSI_FMT_RGB666: val |=3D (0x4 << 4); - hact =3D mode->hdisplay * 3; - video_start =3D (mode->htotal - mode->hsync_start) * 3; + hact =3D vm.hactive * 3; + video_start =3D (vm.hsync_len + vm.hback_porch) * 3; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_18; break; =20 case MIPI_DSI_FMT_RGB666_PACKED: val |=3D (0x4 << 4) | BIT(3); - hact =3D mode->hdisplay * 18 / 8; - video_start =3D (mode->htotal - mode->hsync_start) * 18 / 8; + hact =3D vm.hactive * 18 / 8; + video_start =3D (vm.hsync_len + vm.hback_porch) * 18 / 8; data_type =3D MIPI_DSI_PIXEL_STREAM_3BYTE_18; break; =20 case MIPI_DSI_FMT_RGB565: val |=3D (0x5 << 4); - hact =3D mode->hdisplay * 2; - video_start =3D (mode->htotal - mode->hsync_start) * 2; + hact =3D vm.hactive * 2; + video_start =3D (vm.hsync_len + vm.hback_porch) * 2; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: @@ -814,43 +817,43 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) tc358768_write(priv, TC358768_DSI_EVENT, 0); =20 /* vact */ - tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); + tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); =20 /* vsw */ - tc358768_write(priv, TC358768_DSI_VSW, - mode->vsync_end - mode->vsync_start); + tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len); + /* vbp */ - tc358768_write(priv, TC358768_DSI_VBPR, - mode->vtotal - mode->vsync_end); + tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch); =20 /* hsw * byteclk * ndl / pclk */ - val =3D (u32)div_u64((mode->hsync_end - mode->hsync_start) * + val =3D (u32)div_u64(vm.hsync_len * ((u64)priv->dsiclk / 4) * priv->dsi_lanes, - mode->clock * 1000); + vm.pixelclock); tc358768_write(priv, TC358768_DSI_HSW, val); =20 /* hbp * byteclk * ndl / pclk */ - val =3D (u32)div_u64((mode->htotal - mode->hsync_end) * + val =3D (u32)div_u64(vm.hback_porch * ((u64)priv->dsiclk / 4) * priv->dsi_lanes, - mode->clock * 1000); + vm.pixelclock); tc358768_write(priv, TC358768_DSI_HBPR, val); } else { /* Set event mode */ tc358768_write(priv, TC358768_DSI_EVENT, 1); =20 /* vact */ - tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay); + tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); =20 /* vsw (+ vbp) */ tc358768_write(priv, TC358768_DSI_VSW, - mode->vtotal - mode->vsync_start); + vm.vsync_len + vm.vback_porch); + /* vbp (not used in event mode) */ tc358768_write(priv, TC358768_DSI_VBPR, 0); =20 /* (hsw + hbp) * byteclk * ndl / pclk */ - val =3D (u32)div_u64((mode->htotal - mode->hsync_start) * + val =3D (u32)div_u64((vm.hsync_len + vm.hback_porch) * ((u64)priv->dsiclk / 4) * priv->dsi_lanes, - mode->clock * 1000); + vm.pixelclock); tc358768_write(priv, TC358768_DSI_HSW, val); =20 /* hbp (not used in event mode) */ --=20 2.34.1 From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE370EB8FB6 for ; Wed, 6 Sep 2023 06:51:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242024AbjIFGvy (ORCPT ); Wed, 6 Sep 2023 02:51:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240833AbjIFGvm (ORCPT ); Wed, 6 Sep 2023 02:51:42 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCABECFD for ; Tue, 5 Sep 2023 23:51:36 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 3FC082B5A; Wed, 6 Sep 2023 08:50:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1693983007; bh=Dz3jE5ysfp7p2mTHlnxNnqe7wV8qRrykUPtk9tHtsyI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=V+RAVyc530ikG8dJawk7Wuh5fHKP+UOBaDj+S9m+u91yii3N7xVjqSnr4TQ1/pUOc xxTA3TgxJG9/DVdI7TrEWLvR+Eh9ylRZSXd/QhUcRQ4l3EtQDibwm6um0G9Fq1o+TH B0OsFtw+Rbrl9V7XNP3zTsEoaJAeobeRrRKOjC2g= From: Tomi Valkeinen Date: Wed, 06 Sep 2023 09:50:54 +0300 Subject: [PATCH v4 07/12] drm/bridge: tc358768: Print logical values, not raw register values MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-7-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The driver debug prints DSI related timings as raw register values in hex. It is much more useful to see the "logical" value of the timing, not the register value. Change the prints to print the values separately, in case a single register contains multiple values, and use %u to have it in a more human consumable form. Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index b98c517c4726..88060f961064 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -739,57 +739,59 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) =20 /* LP11 > 100us for D-PHY Rx Init */ val =3D tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1; - dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val); + dev_dbg(priv->dev, "LINEINITCNT: %u\n", val); tc358768_write(priv, TC358768_LINEINITCNT, val); =20 /* LPTimeCnt > 50ns */ val =3D tc358768_ns_to_cnt(50, dsibclk_nsk) - 1; lptxcnt =3D val; - dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val); + dev_dbg(priv->dev, "LPTXTIMECNT: %u\n", val); tc358768_write(priv, TC358768_LPTXTIMECNT, val); =20 /* 38ns < TCLK_PREPARE < 95ns */ val =3D tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; + dev_dbg(priv->dev, "TCLK_PREPARECNT %u\n", val); /* TCLK_PREPARE + TCLK_ZERO > 300ns */ val2 =3D tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 2; + dev_dbg(priv->dev, "TCLK_ZEROCNT %u\n", val2); val |=3D val2 << 8; - dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val); tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); =20 /* TCLK_TRAIL > 60ns AND TEOT <=3D 105 ns + 12*UI */ raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_n= sk) - 5; val =3D clamp(raw_val, 0, 127); - dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val); + dev_dbg(priv->dev, "TCLK_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); =20 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ val =3D 50 + tc358768_to_ns(4 * ui_nsk); val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; + dev_dbg(priv->dev, "THS_PREPARECNT %u\n", val); /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ raw_val =3D tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_= nsk) - 10; val2 =3D clamp(raw_val, 0, 127); + dev_dbg(priv->dev, "THS_ZEROCNT %u\n", val2); val |=3D val2 << 8; - dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val); tc358768_write(priv, TC358768_THS_HEADERCNT, val); =20 /* TWAKEUP > 1ms in lptxcnt steps */ val =3D tc358768_ns_to_cnt(1020000, dsibclk_nsk); val =3D val / (lptxcnt + 1) - 1; - dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val); + dev_dbg(priv->dev, "TWAKEUP: %u\n", val); tc358768_write(priv, TC358768_TWAKEUP, val); =20 /* TCLK_POSTCNT > 60ns + 52*UI */ val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), dsibclk_nsk) - 3; - dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val); + dev_dbg(priv->dev, "TCLK_POSTCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_POSTCNT, val); =20 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk), dsibclk_nsk) - 4; val =3D clamp(raw_val, 0, 15); - dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val); + dev_dbg(priv->dev, "THS_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_THS_TRAILCNT, val); =20 val =3D BIT(0); @@ -803,10 +805,11 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ val =3D tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1; + dev_dbg(priv->dev, "TXTAGOCNT: %u\n", val); val2 =3D tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), dsibclk_nsk) - 2; + dev_dbg(priv->dev, "RXTASURECNT: %u\n", val2); val =3D val << 16 | val2; - dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val); tc358768_write(priv, TC358768_BTACNTRL1, val); =20 /* START[0] */ --=20 2.34.1 From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D1B6EB8FAD for ; Wed, 6 Sep 2023 06:51:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242113AbjIFGv4 (ORCPT ); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-8-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6394; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=BZhH2prSMBsuMuhtlgAO2GJaFKdsRw78WZq1/MpLDSI=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFqOQvVp4pkwmdReSPwf5xFR7U42Jh+aQJ1N 3HxtjN3mjyJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghagAKCRD6PaqMvJYe 9dZWD/0edVKDaekBK/4Adlr9B3KBh6MjmXq3rV847JN2uNBoAgIsxlwrbYdCJnHIjFWoWDElkb9 JWXblYKAjjCbTbQejRkUjVgZcGqto25WAuxf1+pH21JDVlRw9hMPVISSWwV6KE6JSzwpdm3wFTo aL0rfypPkOg0mTIC+PqKFlJgoxoYjBJiCixfUWI/KPGVNzZdhkAlqQR6yUNHLo05Q7ZjPO7CS2S wdnhOeIFr6/xplNbw+CnQX7N2x2teVnhdopzqtlFmw0QoW+No7Ooag0iG+tD7ktlUIoj8wVdSaI u8boZ5JvsmP4+xNwxdrn5zAym+gct2JJfvjWCZHdjgvC94mc0WbxHCSiEy2D04xhcTsmfp5gknM zwIhHlIfMO4xnVydj/liNlVc7rqGCN/iFnqSPoPlO8LJSH/2WKg8VcZ9bh6BmZN3C3eR6ldFHW7 DHgMk0fdMyh7VBeQ9evr1kjXEVpUoZkeOCiRwIgFVwWvAWtogdU/8qXzMI4cRKi4kD/K5aKSQKP rAufYZhfav8qf+muIbZyghaJkkYTOb41YYh1pzfRb1rh6bcWDcxfMkO3GIgHgsDHOHcsl864mnw VurpAoJHBEnjm+yrXNrESaITXxbV8+kHMDbas37Caj7pNq26PNylBFz+5r6BZzIJqhhvRNOLZh2 aI0brioEabPrV8A== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Simplify the code by capturing the priv->dev value to dev variable, and use it. Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 41 ++++++++++++++++++++---------------= ---- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 88060f961064..6297d28250e9 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -651,9 +651,10 @@ static void tc358768_bridge_pre_enable(struct drm_brid= ge *bridge) const u32 internal_delay =3D 40; int ret, i; struct videomode vm; + struct device *dev =3D priv->dev; =20 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { - dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling bac= k to continuous\n"); + dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to c= ontinuous\n"); mode_flags &=3D ~MIPI_DSI_CLOCK_NON_CONTINUOUS; } =20 @@ -661,7 +662,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) =20 ret =3D tc358768_sw_reset(priv); if (ret) { - dev_err(priv->dev, "Software reset failed: %d\n", ret); + dev_err(dev, "Software reset failed: %d\n", ret); tc358768_hw_disable(priv); return; } @@ -669,7 +670,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) mode =3D &bridge->encoder->crtc->state->adjusted_mode; ret =3D tc358768_setup_pll(priv, mode); if (ret) { - dev_err(priv->dev, "PLL setup failed: %d\n", ret); + dev_err(dev, "PLL setup failed: %d\n", ret); tc358768_hw_disable(priv); return; } @@ -709,7 +710,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: - dev_err(priv->dev, "Invalid data format (%u)\n", + dev_err(dev, "Invalid data format (%u)\n", dsi_dev->format); tc358768_hw_disable(priv); return; @@ -733,65 +734,65 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) dsibclk); dsiclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); ui_nsk =3D dsiclk_nsk / 2; - dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk); - dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk); - dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk); + dev_dbg(dev, "dsiclk_nsk: %u\n", dsiclk_nsk); + dev_dbg(dev, "ui_nsk: %u\n", ui_nsk); + dev_dbg(dev, "dsibclk_nsk: %u\n", dsibclk_nsk); =20 /* LP11 > 100us for D-PHY Rx Init */ val =3D tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1; - dev_dbg(priv->dev, "LINEINITCNT: %u\n", val); + dev_dbg(dev, "LINEINITCNT: %u\n", val); tc358768_write(priv, TC358768_LINEINITCNT, val); =20 /* LPTimeCnt > 50ns */ val =3D tc358768_ns_to_cnt(50, dsibclk_nsk) - 1; lptxcnt =3D val; - dev_dbg(priv->dev, "LPTXTIMECNT: %u\n", val); + dev_dbg(dev, "LPTXTIMECNT: %u\n", val); tc358768_write(priv, TC358768_LPTXTIMECNT, val); =20 /* 38ns < TCLK_PREPARE < 95ns */ val =3D tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; - dev_dbg(priv->dev, "TCLK_PREPARECNT %u\n", val); + dev_dbg(dev, "TCLK_PREPARECNT %u\n", val); /* TCLK_PREPARE + TCLK_ZERO > 300ns */ val2 =3D tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 2; - dev_dbg(priv->dev, "TCLK_ZEROCNT %u\n", val2); + dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); =20 /* TCLK_TRAIL > 60ns AND TEOT <=3D 105 ns + 12*UI */ raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_n= sk) - 5; val =3D clamp(raw_val, 0, 127); - dev_dbg(priv->dev, "TCLK_TRAILCNT: %u\n", val); + dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); =20 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ val =3D 50 + tc358768_to_ns(4 * ui_nsk); val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; - dev_dbg(priv->dev, "THS_PREPARECNT %u\n", val); + dev_dbg(dev, "THS_PREPARECNT %u\n", val); /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ raw_val =3D tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_= nsk) - 10; val2 =3D clamp(raw_val, 0, 127); - dev_dbg(priv->dev, "THS_ZEROCNT %u\n", val2); + dev_dbg(dev, "THS_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_THS_HEADERCNT, val); =20 /* TWAKEUP > 1ms in lptxcnt steps */ val =3D tc358768_ns_to_cnt(1020000, dsibclk_nsk); val =3D val / (lptxcnt + 1) - 1; - dev_dbg(priv->dev, "TWAKEUP: %u\n", val); + dev_dbg(dev, "TWAKEUP: %u\n", val); tc358768_write(priv, TC358768_TWAKEUP, val); =20 /* TCLK_POSTCNT > 60ns + 52*UI */ val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), dsibclk_nsk) - 3; - dev_dbg(priv->dev, "TCLK_POSTCNT: %u\n", val); + dev_dbg(dev, "TCLK_POSTCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_POSTCNT, val); =20 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk), dsibclk_nsk) - 4; val =3D clamp(raw_val, 0, 15); - dev_dbg(priv->dev, "THS_TRAILCNT: %u\n", val); + dev_dbg(dev, "THS_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_THS_TRAILCNT, val); =20 val =3D BIT(0); @@ -805,10 +806,10 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ val =3D tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1; - dev_dbg(priv->dev, "TXTAGOCNT: %u\n", val); + dev_dbg(dev, "TXTAGOCNT: %u\n", val); val2 =3D tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), dsibclk_nsk) - 2; - dev_dbg(priv->dev, "RXTASURECNT: %u\n", val2); + dev_dbg(dev, "RXTASURECNT: %u\n", val2); val =3D val << 16 | val2; tc358768_write(priv, TC358768_BTACNTRL1, val); =20 @@ -902,7 +903,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) =20 ret =3D tc358768_clear_error(priv); if (ret) { - dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret); + dev_err(dev, "Bridge pre_enable failed: %d\n", ret); tc358768_bridge_disable(bridge); tc358768_bridge_post_disable(bridge); } --=20 2.34.1 From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D472EEB8FAD for ; Wed, 6 Sep 2023 06:51:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231573AbjIFGwB (ORCPT ); Wed, 6 Sep 2023 02:52:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242048AbjIFGvu (ORCPT ); Wed, 6 Sep 2023 02:51:50 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 262AFCFA for ; Tue, 5 Sep 2023 23:51:40 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 98809283; Wed, 6 Sep 2023 08:50:08 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1693983009; bh=iIhP4OBd9bTNKWQ7Dv6rkC8lGjA6raktXGPsD/PxquE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=AaHhNA2MFB8chTBqZ/MnO3nObqRLG5/pkmEkHtxuJZMPQzBy12+NgGTVtfXOzIQyp oMQfPBsXhhs46zL5xSYhV9FoX43jW2Owtkahp/YkeAWLs9w5RE1qynoXGcQtP/76Cq mydsVOEgCsD3qB0QqrrNju0uX6S+pOO37yHjItd0= From: Tomi Valkeinen Date: Wed, 06 Sep 2023 09:50:56 +0300 Subject: [PATCH v4 09/12] drm/bridge: tc358768: Rename dsibclk to hsbyteclk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-9-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7486; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=iIhP4OBd9bTNKWQ7Dv6rkC8lGjA6raktXGPsD/PxquE=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFqfJnega8N2KRKSnfKc3mz6yPI/osW0mTfR hP27lc1M4OJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghagAKCRD6PaqMvJYe 9bLTD/4n8VKZ1bs5nqxwDQ+I+inBVLKBrYZY0HA8RrVBSJXt5qLNYScnuKmo/db5AboqeXeeAwS YNkCBIJth/iQstGYm5BQGCTSvHDjS/VQKwnzMMhfDiPjCdewEvv+Kq55GehsHu7TAMHTm8hgGtA 4o8ge4a2DOYQwhGAvJbr8B/dsiZIPI8xTNcsWTW77uuW47iHUuoU740E4wVYoQvdzt+JpGULJD4 fIJR7DvU9NBcZ8EX7D2p1cvWHL8PPCEhT9JAAN5SRz32VxUcH4a5S2sKcZRAhXie378kjN9Hpt4 xVaMm2O6faOXwkgV5GP71VVkG2mJbSgkOz+0jon12yDJIfwQqVnvsUz2a9pAmQ3OlAHWZxHC1Jk Ves+7fTaQYJlt4GI5jRuGeyhwWpwCF9We6/XPnb+D+5vbbRBFR/PVAPIFNiDBDhtdJyWYJemv+l GKowzWKJRRDpuVIPdRfRK13AYITDL6K8BG4xNjY4cSKU6IMVf83xFh2rdFJ061Z+5FyoQS0AnlT 16l+Q6B+ndTDAe2cCgrQdpimQqNYNArlZSxDzj4Oqx2eYn+8AFIIuYJcyAgGc/b4yy/MBm2RE/N OndrRyzcgrMHiozu3RH+MJQm0wDVK19lqklF3whgX7a/l6pAS8yTkM1QobkP3Kqcclv4UgQDNmH NZwRrPbtu7kDcpw== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Toshiba documentation talks about HSByteClk when referring to the DSI HS byte clock, whereas the driver uses 'dsibclk' name. Also, in a few places the driver calculates the byte clock from the DSI clock, even if the byte clock is already available in a variable. To align the driver with the documentation, change the 'dsibclk' variable to 'hsbyteclk'. This also make it easier to visually separate 'dsibclk' and 'dsiclk' variables. Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 48 +++++++++++++++++++----------------= ---- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 6297d28250e9..0f117d673b14 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -604,7 +604,7 @@ static int tc358768_setup_pll(struct tc358768_priv *pri= v, =20 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n", clk_get_rate(priv->refclk), fbd, prd, frs); - dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n", + dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n", priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n", tc358768_pll_to_pclk(priv, priv->dsiclk * 2), @@ -646,8 +646,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) u32 val, val2, lptxcnt, hact, data_type; s32 raw_val; const struct drm_display_mode *mode; - u32 dsibclk_nsk, dsiclk_nsk, ui_nsk; - u32 dsiclk, dsibclk, video_start; + u32 hsbyteclk_nsk, dsiclk_nsk, ui_nsk; + u32 dsiclk, hsbyteclk, video_start; const u32 internal_delay =3D 40; int ret, i; struct videomode vm; @@ -678,7 +678,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) drm_display_mode_to_videomode(mode, &vm); =20 dsiclk =3D priv->dsiclk; - dsibclk =3D dsiclk / 4; + hsbyteclk =3D dsiclk / 4; =20 /* Data Format Control Register */ val =3D BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ @@ -730,67 +730,67 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); =20 /* DSI Timings */ - dsibclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, - dsibclk); + hsbyteclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, + hsbyteclk); dsiclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); ui_nsk =3D dsiclk_nsk / 2; dev_dbg(dev, "dsiclk_nsk: %u\n", dsiclk_nsk); dev_dbg(dev, "ui_nsk: %u\n", ui_nsk); - dev_dbg(dev, "dsibclk_nsk: %u\n", dsibclk_nsk); + dev_dbg(dev, "hsbyteclk_nsk: %u\n", hsbyteclk_nsk); =20 /* LP11 > 100us for D-PHY Rx Init */ - val =3D tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(100 * 1000, hsbyteclk_nsk) - 1; dev_dbg(dev, "LINEINITCNT: %u\n", val); tc358768_write(priv, TC358768_LINEINITCNT, val); =20 /* LPTimeCnt > 50ns */ - val =3D tc358768_ns_to_cnt(50, dsibclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(50, hsbyteclk_nsk) - 1; lptxcnt =3D val; dev_dbg(dev, "LPTXTIMECNT: %u\n", val); tc358768_write(priv, TC358768_LPTXTIMECNT, val); =20 /* 38ns < TCLK_PREPARE < 95ns */ - val =3D tc358768_ns_to_cnt(65, dsibclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(65, hsbyteclk_nsk) - 1; dev_dbg(dev, "TCLK_PREPARECNT %u\n", val); /* TCLK_PREPARE + TCLK_ZERO > 300ns */ val2 =3D tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), - dsibclk_nsk) - 2; + hsbyteclk_nsk) - 2; dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); =20 /* TCLK_TRAIL > 60ns AND TEOT <=3D 105 ns + 12*UI */ - raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_n= sk) - 5; + raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), hsbyteclk= _nsk) - 5; val =3D clamp(raw_val, 0, 127); dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); =20 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ val =3D 50 + tc358768_to_ns(4 * ui_nsk); - val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(val, hsbyteclk_nsk) - 1; dev_dbg(dev, "THS_PREPARECNT %u\n", val); /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ - raw_val =3D tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_= nsk) - 10; + raw_val =3D tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), hsbytecl= k_nsk) - 10; val2 =3D clamp(raw_val, 0, 127); dev_dbg(dev, "THS_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_THS_HEADERCNT, val); =20 /* TWAKEUP > 1ms in lptxcnt steps */ - val =3D tc358768_ns_to_cnt(1020000, dsibclk_nsk); + val =3D tc358768_ns_to_cnt(1020000, hsbyteclk_nsk); val =3D val / (lptxcnt + 1) - 1; dev_dbg(dev, "TWAKEUP: %u\n", val); tc358768_write(priv, TC358768_TWAKEUP, val); =20 /* TCLK_POSTCNT > 60ns + 52*UI */ val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), - dsibclk_nsk) - 3; + hsbyteclk_nsk) - 3; dev_dbg(dev, "TCLK_POSTCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_POSTCNT, val); =20 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk), - dsibclk_nsk) - 4; + hsbyteclk_nsk) - 4; val =3D clamp(raw_val, 0, 15); dev_dbg(dev, "THS_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_THS_TRAILCNT, val); @@ -804,11 +804,11 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); =20 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ - val =3D tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); - val =3D tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1; + val =3D tc358768_to_ns((lptxcnt + 1) * hsbyteclk_nsk * 4); + val =3D tc358768_ns_to_cnt(val, hsbyteclk_nsk) / 4 - 1; dev_dbg(dev, "TXTAGOCNT: %u\n", val); - val2 =3D tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk), - dsibclk_nsk) - 2; + val2 =3D tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * hsbyteclk_nsk), + hsbyteclk_nsk) - 2; dev_dbg(dev, "RXTASURECNT: %u\n", val2); val =3D val << 16 | val2; tc358768_write(priv, TC358768_BTACNTRL1, val); @@ -831,13 +831,13 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) =20 /* hsw * byteclk * ndl / pclk */ val =3D (u32)div_u64(vm.hsync_len * - ((u64)priv->dsiclk / 4) * priv->dsi_lanes, + (u64)hsbyteclk * priv->dsi_lanes, vm.pixelclock); tc358768_write(priv, TC358768_DSI_HSW, val); =20 /* hbp * byteclk * ndl / pclk */ val =3D (u32)div_u64(vm.hback_porch * - ((u64)priv->dsiclk / 4) * priv->dsi_lanes, + (u64)hsbyteclk * priv->dsi_lanes, vm.pixelclock); tc358768_write(priv, TC358768_DSI_HBPR, val); } else { @@ -856,7 +856,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) =20 /* (hsw + hbp) * byteclk * ndl / pclk */ val =3D (u32)div_u64((vm.hsync_len + vm.hback_porch) * - ((u64)priv->dsiclk / 4) * priv->dsi_lanes, + (u64)hsbyteclk * priv->dsi_lanes, vm.pixelclock); tc358768_write(priv, TC358768_DSI_HSW, val); =20 --=20 2.34.1 From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40925EB8FB5 for ; Wed, 6 Sep 2023 06:51:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241952AbjIFGv6 (ORCPT ); Wed, 6 Sep 2023 02:51:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239356AbjIFGvu (ORCPT ); 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a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The driver defines TC358768_PRECISION as 1000, and uses "nsk" to refer to clock periods. The original author does not remember where all this came from. Effectively the driver is using picoseconds as the unit for clock periods, yet referring to them by "nsk". Clean this up by just saying the periods are in picoseconds. Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 60 +++++++++++++++++++----------------= ---- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 0f117d673b14..9ce8d120b50c 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #include #include @@ -627,15 +628,14 @@ static int tc358768_setup_pll(struct tc358768_priv *p= riv, return tc358768_clear_error(priv); } =20 -#define TC358768_PRECISION 1000 -static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk) +static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) { - return (ns * TC358768_PRECISION + period_nsk) / period_nsk; + return (ns * 1000 + period_ps) / period_ps; } =20 -static u32 tc358768_to_ns(u32 nsk) +static u32 tc358768_ps_to_ns(u32 ps) { - return (nsk / TC358768_PRECISION); + return ps / 1000; } =20 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) @@ -646,7 +646,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridg= e *bridge) u32 val, val2, lptxcnt, hact, data_type; s32 raw_val; const struct drm_display_mode *mode; - u32 hsbyteclk_nsk, dsiclk_nsk, ui_nsk; + u32 hsbyteclk_ps, dsiclk_ps, ui_ps; u32 dsiclk, hsbyteclk, video_start; const u32 internal_delay =3D 40; int ret, i; @@ -730,67 +730,65 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); =20 /* DSI Timings */ - hsbyteclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, - hsbyteclk); - dsiclk_nsk =3D (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk); - ui_nsk =3D dsiclk_nsk / 2; - dev_dbg(dev, "dsiclk_nsk: %u\n", dsiclk_nsk); - dev_dbg(dev, "ui_nsk: %u\n", ui_nsk); - dev_dbg(dev, "hsbyteclk_nsk: %u\n", hsbyteclk_nsk); + hsbyteclk_ps =3D (u32)div_u64(PICO, hsbyteclk); + dsiclk_ps =3D (u32)div_u64(PICO, dsiclk); + ui_ps =3D dsiclk_ps / 2; + dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps, + ui_ps, hsbyteclk_ps); =20 /* LP11 > 100us for D-PHY Rx Init */ - val =3D tc358768_ns_to_cnt(100 * 1000, hsbyteclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1; dev_dbg(dev, "LINEINITCNT: %u\n", val); tc358768_write(priv, TC358768_LINEINITCNT, val); =20 /* LPTimeCnt > 50ns */ - val =3D tc358768_ns_to_cnt(50, hsbyteclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1; lptxcnt =3D val; dev_dbg(dev, "LPTXTIMECNT: %u\n", val); tc358768_write(priv, TC358768_LPTXTIMECNT, val); =20 /* 38ns < TCLK_PREPARE < 95ns */ - val =3D tc358768_ns_to_cnt(65, hsbyteclk_nsk) - 1; + val =3D tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1; dev_dbg(dev, "TCLK_PREPARECNT %u\n", val); /* TCLK_PREPARE + TCLK_ZERO > 300ns */ - val2 =3D tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk), - hsbyteclk_nsk) - 2; + val2 =3D tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps), + hsbyteclk_ps) - 2; dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); =20 /* TCLK_TRAIL > 60ns AND TEOT <=3D 105 ns + 12*UI */ - raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), hsbyteclk= _nsk) - 5; + raw_val =3D tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbytec= lk_ps) - 5; val =3D clamp(raw_val, 0, 127); dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); =20 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ - val =3D 50 + tc358768_to_ns(4 * ui_nsk); - val =3D tc358768_ns_to_cnt(val, hsbyteclk_nsk) - 1; + val =3D 50 + tc358768_ps_to_ns(4 * ui_ps); + val =3D tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1; dev_dbg(dev, "THS_PREPARECNT %u\n", val); /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ - raw_val =3D tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), hsbytecl= k_nsk) - 10; + raw_val =3D tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyte= clk_ps) - 10; val2 =3D clamp(raw_val, 0, 127); dev_dbg(dev, "THS_ZEROCNT %u\n", val2); val |=3D val2 << 8; tc358768_write(priv, TC358768_THS_HEADERCNT, val); =20 /* TWAKEUP > 1ms in lptxcnt steps */ - val =3D tc358768_ns_to_cnt(1020000, hsbyteclk_nsk); + val =3D tc358768_ns_to_cnt(1020000, hsbyteclk_ps); val =3D val / (lptxcnt + 1) - 1; dev_dbg(dev, "TWAKEUP: %u\n", val); tc358768_write(priv, TC358768_TWAKEUP, val); =20 /* TCLK_POSTCNT > 60ns + 52*UI */ - val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk), - hsbyteclk_nsk) - 3; + val =3D tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps), + hsbyteclk_ps) - 3; dev_dbg(dev, "TCLK_POSTCNT: %u\n", val); tc358768_write(priv, TC358768_TCLK_POSTCNT, val); =20 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ - raw_val =3D tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk), - hsbyteclk_nsk) - 4; + raw_val =3D tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps), + hsbyteclk_ps) - 4; val =3D clamp(raw_val, 0, 15); dev_dbg(dev, "THS_TRAILCNT: %u\n", val); tc358768_write(priv, TC358768_THS_TRAILCNT, val); @@ -804,11 +802,11 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); =20 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ - val =3D tc358768_to_ns((lptxcnt + 1) * hsbyteclk_nsk * 4); - val =3D tc358768_ns_to_cnt(val, hsbyteclk_nsk) / 4 - 1; + val =3D tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4); + val =3D tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1; dev_dbg(dev, "TXTAGOCNT: %u\n", val); - val2 =3D tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * hsbyteclk_nsk), - hsbyteclk_nsk) - 2; + val2 =3D tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_p= s), + hsbyteclk_ps) - 2; dev_dbg(dev, "RXTASURECNT: %u\n", val2); val =3D val << 16 | val2; tc358768_write(priv, TC358768_BTACNTRL1, val); --=20 2.34.1 From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E03EEB8FAD for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-11-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1080; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=XUpZ1sa4som54e3a4sbbBeu8u2QabPMAMN6dfT5AT9Q=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFrGphoZYtbzABk2wlF1m3cpxJ82q2nsnlbt 5i/2HJ2+YGJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghawAKCRD6PaqMvJYe 9WZzEACNP9evo+i3NNY0kbRgECfMObxK0+VBI90Xp1PP7KT8Zg6MMA/yJaWCVkrhdl/UJ76eh4X aVL20gw2dxRN1QAPp2zSIwmKYd39PjguaLKWeHq4dy0k5t3/3pmflSb0bTu9Gx07wwGYw2DcHhK yQU8v6+0FJGMWzJ3eDaWxywF0kJcjeje+3ELw7zQnVgEBm+Nkv4crTofpq1WiNXo3gb3UvBPNAo Te5vhINcPMDyXHVM9x/SvpFbvg6179C7t/UPobzzMSAzV7YFqZ9TdSSVzaYR1JDYtrtOzqOJkPZ P/Y7iXkis9TNtbm8dXFji0ODzJ6ysdA0qlYXuSUW4OM2ZEj/Xw8cgEUw6TKTX12vj9g4gQdVZMu 6KN2Etu9KkEBX9Xo7ZN6P48lhKwALNXXH994eoHv9npO7Yp1K7nuedhloBMX7oq68aXg7YRE4kl KocmuRcHlWLmmiY18kx146/fqNgWO3DeaHI5d1e95EQFF0dBnQy045wSgrWuINBCswthl3yFAhU YZCpSq2hTHTu7R3uVGgjzuxMgBhhuJYH8uNCzOO5x9KS+lwG2TnHqKL9b8qurqjdfSWlrfqChU3 rYB09T+p64Gi8YmfptksPB0ngD64EB6N1G9ZCBaNZSBiaI0iuTMRb8tafAMP50exYvFPPrgvsRf 1hUuat8VnMo/pgw== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The tc358768_ns_to_cnt() is, most likely, supposed to do a div-round-up operation, but it misses subtracting one from the dividend. Fix this by just using DIV_ROUND_UP(). Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") Reviewed-by: Peter Ujfalusi Tested-by: Maxim Schwalm # Asus TF700T Tested-by: Marcel Ziswiler Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index 9ce8d120b50c..f41bf56b7d6b 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -630,7 +630,7 @@ static int tc358768_setup_pll(struct tc358768_priv *pri= v, =20 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) { - return (ns * 1000 + period_ps) / period_ps; + return DIV_ROUND_UP(ns * 1000, period_ps); } =20 static u32 tc358768_ps_to_ns(u32 ps) --=20 2.34.1 From nobody Thu Sep 11 14:52:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3C6FEB8FAD for ; Wed, 6 Sep 2023 06:52:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239961AbjIFGwQ (ORCPT ); Wed, 6 Sep 2023 02:52:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233784AbjIFGwN (ORCPT ); Wed, 6 Sep 2023 02:52:13 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEF8DE53 for ; Tue, 5 Sep 2023 23:51:47 -0700 (PDT) Received: from [127.0.1.1] (91-154-35-171.elisa-laajakaista.fi [91.154.35.171]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 200A03F1; Wed, 6 Sep 2023 08:50:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1693983013; bh=zCdE8XiOOATs6bq11J0QsPBhnlpTi/F5xNfjh4XmLPA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=wVepnI4Hc6wfK9eDD7XM9L4xRVAfD22MGHSGNGSTu2Irt32yU3SRpiTRxbMriIlHZ IrrI4vdz/ayOcn7eE6+raT9slJdopEfEbBMHcjLOYPUf9OvePhtEHzjT93Dj0uUe7r 8pqMY5U6gYBcXun3TQuaDJX57FJQtfix3l90oc5M= From: Tomi Valkeinen Date: Wed, 06 Sep 2023 09:50:59 +0300 Subject: [PATCH v4 12/12] drm/bridge: tc358768: Attempt to fix DSI horizontal timings MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230906-tc358768-v4-12-31725f008a50@ideasonboard.com> References: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> In-Reply-To: <20230906-tc358768-v4-0-31725f008a50@ideasonboard.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , =?utf-8?q?P=C3=A9ter_Ujfalusi?= , Maxim Schwalm , Francesco Dolcini Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Aradhya Bhatia , Tomi Valkeinen , Marcel Ziswiler X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=11895; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=zCdE8XiOOATs6bq11J0QsPBhnlpTi/F5xNfjh4XmLPA=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBk+CFsJctMykGU8ZjkqzadR65gx6uZ0FwXM43KS Y7Ehccod0OJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCZPghbAAKCRD6PaqMvJYe 9WydEACv4c8a/UYDlgak2KAPOYvdh/qdM+zM0Cb5AeMlsxKqcmotuNCmL/HrgaNdovl3J9iB431 x6DPh7YY4p8gsmhuBiM/5zFruqdBQ+Y1MidcFg/yjaaXzXm7QBD8Trjb4TPJ0UWGoyI9xTxiq2j U1h81EsMDa0lqKmUPPkQljlGohC5UqgJV1e3DoRkptyATyCnnNdgqLitVDDkrmFPdIuo/jJWuMy k2g5fMbE16NYa8L9KCfqAtwtcHgo9hYmLgCaenV02d2qS3ALD/S3KtDj3gywS4w7eB6d69f2ltS 6onIIrLTvlGypxuKETokcJgcbJD+OJVRvQiHBUksBiMp+SGy3EP9NxwUipxJEjEkFnOmTfqHFpz +5LMv5P2blrOHWrFH1pIXd2p68A9a1iTsf6ZatABreKFvjmScNRahKcju8oID5YGRbEBhkwKK1k nU5vTwX2x3BtFV/06rQjACVXEGGEMMiOlytxtekQRjnDvYU/7ogFrvj8QHt9BKzRXk5lCQDjUtC BkLc4tMyEO7JAVF5est7laWWjJxZUkLgobioNFpE0n6GGVA/8JGox3lgxui+6Sk6vhKVHsuwLJm vxKkV9HNv/TNj9qvTNzpNJPT0LDTJKyxp1awkAFi6FMSKLlY/EjJ4ugzBtK9VqJGaTLYQMg32hm B65DJJcGzM+CIZw== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The DSI horizontal timing calculations done by the driver seem to often lead to underflows or overflows, depending on the videomode. There are two main things the current driver doesn't seem to get right: DSI HSW and HFP, and VSDly. However, even following Toshiba's documentation it seems we don't always get a working display. This patch attempts to fix the horizontal timings for DSI event mode, and on a system with a DSI->HDMI encoder, a lot of standard HDMI modes now seem to work. The work relies on Toshiba's documentation, but also quite a bit on empirical testing. This also adds timing related debug prints to make it easier to improve on this later. The DSI pulse mode has only been tested with a fixed-resolution panel, which limits the testing of different modes on DSI pulse mode. However, as the VSDly calculation also affects pulse mode, so this might cause a regression. Reviewed-by: Peter Ujfalusi Tested-by: Marcel Ziswiler Tested-by: Maxim Schwalm # Asus TF700T Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358768.c | 211 +++++++++++++++++++++++++++++++++-= ---- 1 file changed, 183 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc3= 58768.c index f41bf56b7d6b..e5ecf1a79e82 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -157,6 +158,7 @@ struct tc358768_priv { u32 frs; /* PLL Freqency range for HSCK (post divider) */ =20 u32 dsiclk; /* pll_clk / 2 */ + u32 pclk; /* incoming pclk rate */ }; =20 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_h= ost @@ -380,6 +382,7 @@ static int tc358768_calc_pll(struct tc358768_priv *priv, priv->prd =3D best_prd; priv->frs =3D frs; priv->dsiclk =3D best_pll / 2; + priv->pclk =3D mode->clock * 1000; =20 return 0; } @@ -638,6 +641,28 @@ static u32 tc358768_ps_to_ns(u32 ps) return ps / 1000; } =20 +static u32 tc358768_dpi_to_ns(u32 val, u32 pclk) +{ + return (u32)div_u64((u64)val * NANO, pclk); +} + +/* Convert value in DPI pixel clock units to DSI byte count */ +static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val) +{ + u64 m =3D (u64)val * priv->dsiclk / 4 * priv->dsi_lanes; + u64 n =3D priv->pclk; + + return (u32)div_u64(m + n - 1, n); +} + +static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val) +{ + u64 m =3D (u64)val * NANO; + u64 n =3D priv->dsiclk / 4 * priv->dsi_lanes; + + return (u32)div_u64(m, n); +} + static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) { struct tc358768_priv *priv =3D bridge_to_tc358768(bridge); @@ -647,11 +672,19 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) s32 raw_val; const struct drm_display_mode *mode; u32 hsbyteclk_ps, dsiclk_ps, ui_ps; - u32 dsiclk, hsbyteclk, video_start; - const u32 internal_delay =3D 40; + u32 dsiclk, hsbyteclk; int ret, i; struct videomode vm; struct device *dev =3D priv->dev; + /* In pixelclock units */ + u32 dpi_htot, dpi_data_start; + /* In byte units */ + u32 dsi_dpi_htot, dsi_dpi_data_start; + u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp; + const u32 dsi_hss =3D 4; /* HSS is a short packet (4 bytes) */ + /* In hsbyteclk units */ + u32 dsi_vsdly; + const u32 internal_dly =3D 40; =20 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to c= ontinuous\n"); @@ -686,27 +719,23 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) case MIPI_DSI_FMT_RGB888: val |=3D (0x3 << 4); hact =3D vm.hactive * 3; - video_start =3D (vm.hsync_len + vm.hback_porch) * 3; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_24; break; case MIPI_DSI_FMT_RGB666: val |=3D (0x4 << 4); hact =3D vm.hactive * 3; - video_start =3D (vm.hsync_len + vm.hback_porch) * 3; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_18; break; =20 case MIPI_DSI_FMT_RGB666_PACKED: val |=3D (0x4 << 4) | BIT(3); hact =3D vm.hactive * 18 / 8; - video_start =3D (vm.hsync_len + vm.hback_porch) * 18 / 8; data_type =3D MIPI_DSI_PIXEL_STREAM_3BYTE_18; break; =20 case MIPI_DSI_FMT_RGB565: val |=3D (0x5 << 4); hact =3D vm.hactive * 2; - video_start =3D (vm.hsync_len + vm.hback_porch) * 2; data_type =3D MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: @@ -716,9 +745,150 @@ static void tc358768_bridge_pre_enable(struct drm_bri= dge *bridge) return; } =20 + /* + * There are three important things to make TC358768 work correctly, + * which are not trivial to manage: + * + * 1. Keep the DPI line-time and the DSI line-time as close to each + * other as possible. + * 2. TC358768 goes to LP mode after each line's active area. The DSI + * HFP period has to be long enough for entering and exiting LP mode. + * But it is not clear how to calculate this. + * 3. VSDly (video start delay) has to be long enough to ensure that the + * DSI TX does not start transmitting until we have started receiving + * pixel data from the DPI input. It is not clear how to calculate + * this either. + */ + + dpi_htot =3D vm.hactive + vm.hfront_porch + vm.hsync_len + vm.hback_porch; + dpi_data_start =3D vm.hsync_len + vm.hback_porch; + + dev_dbg(dev, "dpi horiz timing (pclk): %u + %u + %u + %u =3D %u\n", + vm.hsync_len, vm.hback_porch, vm.hactive, vm.hfront_porch, + dpi_htot); + + dev_dbg(dev, "dpi horiz timing (ns): %u + %u + %u + %u =3D %u\n", + tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), + tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), + tc358768_dpi_to_ns(vm.hactive, vm.pixelclock), + tc358768_dpi_to_ns(vm.hfront_porch, vm.pixelclock), + tc358768_dpi_to_ns(dpi_htot, vm.pixelclock)); + + dev_dbg(dev, "dpi data start (ns): %u + %u =3D %u\n", + tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), + tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), + tc358768_dpi_to_ns(dpi_data_start, vm.pixelclock)); + + dsi_dpi_htot =3D tc358768_dpi_to_dsi_bytes(priv, dpi_htot); + dsi_dpi_data_start =3D tc358768_dpi_to_dsi_bytes(priv, dpi_data_start); + + if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { + dsi_hsw =3D tc358768_dpi_to_dsi_bytes(priv, vm.hsync_len); + dsi_hbp =3D tc358768_dpi_to_dsi_bytes(priv, vm.hback_porch); + } else { + /* HBP is included in HSW in event mode */ + dsi_hbp =3D 0; + dsi_hsw =3D tc358768_dpi_to_dsi_bytes(priv, + vm.hsync_len + vm.hback_porch); + + /* + * The pixel packet includes the actual pixel data, and: + * DSI packet header =3D 4 bytes + * DCS code =3D 1 byte + * DSI packet footer =3D 2 bytes + */ + dsi_hact =3D hact + 4 + 1 + 2; + + dsi_hfp =3D dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; + + /* + * Here we should check if HFP is long enough for entering LP + * and exiting LP, but it's not clear how to calculate that. + * Instead, this is a naive algorithm that just adjusts the HFP + * and HSW so that HFP is (at least) roughly 2/3 of the total + * blanking time. + */ + if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) { + u32 old_hfp =3D dsi_hfp; + u32 old_hsw =3D dsi_hsw; + u32 tot =3D dsi_hfp + dsi_hsw + dsi_hss; + + dsi_hsw =3D tot / 3; + + /* + * Seems like sometimes HSW has to be divisible by num-lanes, but + * not always... + */ + dsi_hsw =3D roundup(dsi_hsw, priv->dsi_lanes); + + dsi_hfp =3D dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; + + dev_dbg(dev, + "hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n", + old_hfp, old_hsw, dsi_hfp, dsi_hsw); + } + + dev_dbg(dev, + "dsi horiz timing (bytes): %u, %u + %u + %u + %u =3D %u\n", + dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp, + dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp); + + dev_dbg(dev, "dsi horiz timing (ns): %u + %u + %u + %u + %u =3D %u\n", + tc358768_dsi_bytes_to_ns(priv, dsi_hss), + tc358768_dsi_bytes_to_ns(priv, dsi_hsw), + tc358768_dsi_bytes_to_ns(priv, dsi_hbp), + tc358768_dsi_bytes_to_ns(priv, dsi_hact), + tc358768_dsi_bytes_to_ns(priv, dsi_hfp), + tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw + dsi_hbp + dsi_hact += dsi_hfp)); + } + + /* VSDly calculation */ + + /* Start with the HW internal delay */ + dsi_vsdly =3D internal_dly; + + /* Convert to byte units as the other variables are in byte units */ + dsi_vsdly *=3D priv->dsi_lanes; + + /* Do we need more delay, in addition to the internal? */ + if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) { + dsi_vsdly =3D dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp; + dsi_vsdly =3D roundup(dsi_vsdly, priv->dsi_lanes); + } + + dev_dbg(dev, "dsi data start (bytes) %u + %u + %u + %u =3D %u\n", + dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp, + dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp); + + dev_dbg(dev, "dsi data start (ns) %u + %u + %u + %u =3D %u\n", + tc358768_dsi_bytes_to_ns(priv, dsi_vsdly), + tc358768_dsi_bytes_to_ns(priv, dsi_hss), + tc358768_dsi_bytes_to_ns(priv, dsi_hsw), + tc358768_dsi_bytes_to_ns(priv, dsi_hbp), + tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp)); + + /* Convert back to hsbyteclk */ + dsi_vsdly /=3D priv->dsi_lanes; + + /* + * The docs say that there is an internal delay of 40 cycles. + * However, we get underflows if we follow that rule. If we + * instead ignore the internal delay, things work. So either + * the docs are wrong or the calculations are wrong. + * + * As a temporary fix, add the internal delay here, to counter + * the subtraction when writing the register. + */ + dsi_vsdly +=3D internal_dly; + + /* Clamp to the register max */ + if (dsi_vsdly - internal_dly > 0x3ff) { + dev_warn(dev, "VSDly too high, underflows likely\n"); + dsi_vsdly =3D 0x3ff + internal_dly; + } + /* VSDly[9:0] */ - video_start =3D max(video_start, internal_delay + 1) - internal_delay; - tc358768_write(priv, TC358768_VSDLY, video_start); + tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly); =20 tc358768_write(priv, TC358768_DATAFMT, val); tc358768_write(priv, TC358768_DSITX_DT, data_type); @@ -826,18 +996,6 @@ static void tc358768_bridge_pre_enable(struct drm_brid= ge *bridge) =20 /* vbp */ tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch); - - /* hsw * byteclk * ndl / pclk */ - val =3D (u32)div_u64(vm.hsync_len * - (u64)hsbyteclk * priv->dsi_lanes, - vm.pixelclock); - tc358768_write(priv, TC358768_DSI_HSW, val); - - /* hbp * byteclk * ndl / pclk */ - val =3D (u32)div_u64(vm.hback_porch * - (u64)hsbyteclk * priv->dsi_lanes, - vm.pixelclock); - tc358768_write(priv, TC358768_DSI_HBPR, val); } else { /* Set event mode */ tc358768_write(priv, TC358768_DSI_EVENT, 1); @@ -851,16 +1009,13 @@ static void tc358768_bridge_pre_enable(struct drm_br= idge *bridge) =20 /* vbp (not used in event mode) */ tc358768_write(priv, TC358768_DSI_VBPR, 0); + } =20 - /* (hsw + hbp) * byteclk * ndl / pclk */ - val =3D (u32)div_u64((vm.hsync_len + vm.hback_porch) * - (u64)hsbyteclk * priv->dsi_lanes, - vm.pixelclock); - tc358768_write(priv, TC358768_DSI_HSW, val); + /* hsw (bytes) */ + tc358768_write(priv, TC358768_DSI_HSW, dsi_hsw); =20 - /* hbp (not used in event mode) */ - tc358768_write(priv, TC358768_DSI_HBPR, 0); - } + /* hbp (bytes) */ + tc358768_write(priv, TC358768_DSI_HBPR, dsi_hbp); =20 /* hact (bytes) */ tc358768_write(priv, TC358768_DSI_HACT, hact); --=20 2.34.1